eviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/inte
sed (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)
v9: Rebased (me)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++---
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 54 +++
From: Mahesh Kumar
This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar
able latency levels 1 through 7
(WM1 - WM7) on NV12 planes.
v2: Addressed review comments by Maarten.
Reviewed-by: Maarten Lankhorst
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/dri
From: Mahesh Kumar
NV12 formats have two registers for DDB. Verify both the registers for
NV12 during verify_wm_state.
v2: Addressed review comments by Maarten.
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.
wm compute func
drm/i915/skl+: make sure higher latency level has higher wm value
drm/i915/skl+: nv12 workaround disable WM level 1-7
drm/i915/skl: split skl_compute_ddb function
Vidya Srinivas (1):
drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
drivers/gpu/drm/i915/i915_dr
been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vi
: Rebased (me)
v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915
y all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: V
rten Lankhorst
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 121 ---
3 files changed, 64 insertions(+), 62 deletions(-)
diff --g
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
mat_is_yuv function from
static to non-static. We need to use it later from
other files for check.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gp
ff-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 833b4ad..f6f2ee8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+
: Rebased (me)
v10: Rebased (me)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 33 +++--
drivers/gpu/drm/i915/intel_drv.h
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++---
duru
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 16
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f36023..c4af05e 100644
--- a/dri
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_atomic.c | 5 ++---
drivers/gpu/drm/i915/intel_display.c | 7 ++-
drivers/gpu/drm/i915/intel_sprite.c | 4
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 24 +---
drivers/gpu/drm/i915/intel_sprite.c | 12 +---
include/uapi/drm/drm_fourcc.h| 3
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 42 +++-
drivers/gpu/drm/i915/intel_sprite.c | 7 +-
include/uapi/drm/drm_fourcc.h
From: Mahesh Kumar
NV12 formats have two registers for DDB. Verify both the registers for
NV12 during verify_wm_state.
v2: Addressed review comments by Maarten.
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915
From: Mahesh Kumar
This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++---
ssed review comments by Maarten
Reviewed-by: Maarten Lankhorst
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 121 ---
3 f
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 54 +++
higher wm value
drm/i915/skl+: nv12 workaround disable WM level 1-7
drm/i915/skl: split skl_compute_ddb function
Vidya Srinivas (1):
drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
drivers/gpu/drm/i915/i915_drv.h | 9 +-
drivers/gpu/drm/i915/i915_reg.h | 7 +
drivers/gpu
ff-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index f2e144b..f359b22 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+
able latency levels 1 through 7
(WM1 - WM7) on NV12 planes.
v2: Addressed review comments by Maarten.
Reviewed-by: Maarten Lankhorst
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/dri
: Rebased (me)
v10: Rebased (me)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 33 +++--
drivers/gpu/drm/i915/intel_drv.h
been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vi
: Rebased (me)
v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915
y all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: V
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
mat_is_yuv function from
static to non-static. We need to use it later from
other files for check.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gp
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.
From: Mahesh Kumar
This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.
From: Mahesh Kumar
NV12 formats have two registers for DDB. Verify both the registers for
NV12 during verify_wm_state.
v2: Addressed review comments by Maarten.
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 54 +++
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
higher wm value
drm/i915/skl+: nv12 workaround disable WM level 1-7
drm/i915/skl: split skl_compute_ddb function
Vidya Srinivas (1):
drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
drivers/gpu/drm/i915/i915_drv.h | 9 +-
drivers/gpu/drm/i915/i915_reg.h | 7 +
drivers/gpu
: Rebased (me)
v10: Rebased (me)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 33 +++--
drivers/gpu/drm/i915/intel_drv.h
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar
ssed review comments by Maarten
Reviewed-by: Maarten Lankhorst
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 121 ---
3 f
ff-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index f2e144b..f359b22 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+
: Rebased (me)
v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915
able latency levels 1 through 7
(WM1 - WM7) on NV12 planes.
v2: Addressed review comments by Maarten.
Reviewed-by: Maarten Lankhorst
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/dri
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++---
mat_is_yuv function from
static to non-static. We need to use it later from
other files for check.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gp
y all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: V
been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vi
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
sure higher latency level has higher wm value
drm/i915/skl+: nv12 workaround disable WM level 1-7
drm/i915/skl: split skl_compute_ddb function
Vidya Srinivas (1):
drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
ode to be applicable to all
Gen.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_atomic.c | 8 ++--
2 files changed
able latency levels 1 through 7
(WM1 - WM7) on NV12 planes.
v2: Addressed review comments by Maarten.
Reviewed-by: Maarten Lankhorst
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/dri
ssed review comments by Maarten
Reviewed-by: Maarten Lankhorst
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 121 ---
3 f
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.
Signed-off
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++---
From: Mahesh Kumar
For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Conf
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.
Sharma
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a77d572..414832a 100644
--- a
: Rebased (me)
v10: Rebased (me)
v11: Addressed review comments from Shashank Sharma
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 40
mat_is_yuv function from
static to non-static. We need to use it later from
other files for check.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Reviewed-by: Shashank Sharma
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
v2: Addressed review comments from Shashank Sharma.
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_drv.h | 1
: Rebased (me)
v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Reviewed-by: Shashank Sharma
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
inton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 77a5433..
u
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4ab51f0..4fb17f5 100644
--- a/drivers
From: Uma Shankar
In case of DSI, DDI PLL is not required.
Handle the same as part of DDI PLL handling.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
mode change 100644 => 100755 drivers/gpu/drm/
Fix the Sequence to program BXT DSI Latch and ULPS.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 23 +--
1 file changed, 5 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 27d8f95..5fa0
From: Uma Shankar
Panel GPIO control should be done based on platform. Add a check
to restrict VLV and CHT specific GPIO confirguration, so that
they dont apply to other platforms.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 delet
Panel Power On/Off sequences are part of Panel spec.
Enabling the support of same in DRM layer for fine grained
panel control.
Signed-off-by: Uma Shankar
---
include/drm/drm_panel.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include/drm/drm_panel.h b/include/drm/drm_
From: Uma Shankar
MIPI Video Mode for high res panels (requiring dual link), need a
8X/3 divider to be programmed as 0x2. Modifying the same
in this patch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
di
From: Uma Shankar
Disable device ready before MIPI port shutdown command.
This helps to avoid mipi split screen issues.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gp
Panel Power On/Off sequences are part of Panel spec.
These are present in VBT v3 of the Intel VBT spec.
Enabling the support of same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i9
Add the call back for MIPI reset sequence in drm for
fine grained panel control. This is needed to
reset the panel based on the panel schematics.
Signed-off-by: Uma Shankar
---
include/drm/drm_panel.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm/drm_panel.h b/include/
From: Uma Shankar
Enable support for BXT DSI dual link mode.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_dsi.c | 27 ++-
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_
From: Uma Shankar
Fix BXT DSI disable sequence as per latest updates in BSpec.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/dr
Enable the call back for MIPI reset sequence. This is needed to
reset the panel, and is part of the VBT spec.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 6 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 9 -
2 files changed, 14 insertions(+), 1 delet
From: Uma Shankar
Enable MIPI IO WA for BXT DSI as per bspec.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_dsi.c | 9 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg
Add the support for backlight sequences in drm layer
to configure the backlight settings during
backlight on/off sequences.
Signed-off-by: Uma Shankar
---
include/drm/drm_panel.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include/drm/drm_panel.h b/include/drm/drm_pan
Enable the support for backlight sequences to configure
backlight settings based on VBT Backlight on/off sequence.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 2 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16
2 files changed, 18 insertions(+
From: Uma Shankar
Enable MIPI IO WA for BXT DSI as per bspec and
program the DSI regulators.
v2: Moved IO enable to pre-enable as per Mika's
review comments. Also reused the existing register
definition for BXT_P_CR_GT_DISP_PWRON.
v3: Added Programming the DSI regulators as per disable/enable
s
From: Uma Shankar
Enable MIPI IO WA for BXT DSI as per bspec and
program the DSI regulators.
v2: Moved IO enable to pre-enable as per Mika's
review comments. Also reused the existing register
definition for BXT_P_CR_GT_DISP_PWRON.
v3: Added Programming the DSI regulators as per disable/enable
s
nable
sequences.
v4: Restricting regulator changes to BXT as suggested by
Jani/Mika
v5: Removed redundant read/modify for regulator register as
per Jani's comment. Maintain enable/disable symmetry as per spec.
Signed-off-by: Uma Shankar
Signed-off-by: Vidya Srinivas
---
drivers/gp
v2: Add Jani Nikula's change for quirk for sync polarity
CC: Jani Nikula
Credits-to: Jani Nikula
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_panel.c | 10 ++
2 files changed, 7 insertions(+), 5 dele
Series reverts rejection of modes on MST monitors that need bigjoiner
and adds MST bigjoiner functionality
Vidya Srinivas (2):
Revert "drm/i915/mst: Reject modes that require the bigjoiner"
drm/i915: Allow bigjoiner for MST
drivers/gpu/drm/i915/display/intel_dp_
This reverts commit 9c058492b16f90bb772cb0dad567e8acc68e155d.
Reverting for adding MST bigjoiner functionality.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b
We need bigjoiner support with MST functionality
for MST monitor resolutions > 5K to work.
Adding support for the same.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/driv
Support resolutions > 5k on MST monitors that need bigjoiner
by adding MST bigjoiner functionality
Vidya Srinivas (1):
drm/i915: Allow bigjoiner for MST
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
--
2.33.0
We need bigjoiner support with MST functionality
for MST monitor resolutions > 5K to work.
Adding support for the same.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/
Support resolutions > 5k on MST monitors that need bigjoiner
by adding MST bigjoiner functionality
Vidya Srinivas (1):
drm/i915: Allow bigjoiner for MST
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
--
2.33.0
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