Reviewed-by: Sivakumar Thulasimani
On Tuesday 03 May 2016 09:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
If there's a fence on the object it will be aligned to the start
of the object, and hence CPU rendering to any fb that straddles
the fence edge will come out wron
Reviewed-by: Sivakumar Thulasimani
On Tuesday 03 May 2016 09:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
To make life less surprising we can make intel_adjust_tile_offset()
deal with linear buffers as well. Currently it doesn't seem like there's
a real need for
Reviewed-by: Sivakumar Thulasimani
On Tuesday 03 May 2016 09:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
SKL has nasty limitations with the display surface offsets:
* source x offset + width must be less than the stride for X tiled
surfaces or the display engine falls
On 3/20/2015 11:27 AM, Sonika Jindal wrote:
+#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
+#define EDP_PSR2_TP2_TIME_500(0<<8)
+#define EDP_PSR2_TP2_TIME_100(1<<8)
+#define EDP_PSR2_TP2_TIME_250(2<<8)
Better to make all values inline, 5
Reviewed-by: Sivakumar Thulasimani
On 3/17/2015 3:09 PM, Imre Deak wrote:
From: Satheeshakrishna M
Adding IS_BROXTON macro for broxton specific implementation.
Signed-off-by: Satheeshakrishna M
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1
ue;
+
+ intel_prepare_ddi_buffers(dev, intel_dig_port);
+ visited[intel_dig_port->port] = true;
+ }
}
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
is visited[] for handling MST scenarios ?if s
Reviewed-by: Sivakumar Thulasimani
On 3/17/2015 3:10 PM, Imre Deak wrote:
From: Damien Lespiau
We don't actually need to write the HDMI entry on DDIs that have no
chance to be used as HDMI ports.
While this patch shouldn't change the current behaviour, it makes
further enabling w
Reviewed-by: Sivakumar Thulasimani
On 3/23/2015 11:12 PM, Ramalingam C wrote:
As part of allocation of the drm_i915_private variable, drrs capability
enum is initialized to DRRS_NOT_SUPPORTED. Hence need not initialize at
each connector init.
Moreover initializing this enum at connector init
since drrs struct is used primarily in intel_dp.c file alone can it be
moved to intel_dp ?
On 3/23/2015 11:12 PM, Ramalingam C wrote:
In case of multiple eDP panels, only one can have
the DRRS enabled on it.
In future eDP DRRS will be extended for multiple panels.
Signed-off-by: Ramalingam C
ith the changes.
Reviewed-by: Sivakumar Thulasimani
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Reviewed-by: Sivakumar Thulasimani
On 3/17/2015 3:10 PM, Imre Deak wrote:
From: Vandana Kannan
Broxton supports 3 voltage swing levels on all DP ports.
Max level of pre-emphasis will be taken care with the existing code.
v2: Patch rebased
v3: (imre)
- keep existing behavior for other
_crtc_state *pipe_config)
{
@@ -5812,6 +5844,8 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
pipe_config->pipe_bpp = 8*3;
}
+ intel_compute_psr_config(crtc, pipe_config);
+
if (HAS_IPS(dev))
hsw_compute_ips_config(crtc, pi
to a propper place as pointed out by Sivakumar.
Use a better name as pointed out by Ram.
Cc: Sivakumar Thulasimani
Cc: Ramalingam C
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_
On 3/27/2015 2:02 PM, Daniel Vetter wrote:
On Fri, Mar 27, 2015 at 11:37:09AM +0530, Sivakumar Thulasimani wrote:
On 3/27/2015 12:50 AM, Rodrigo Vivi wrote:
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func th
On 3/31/2015 4:44 PM, Mika Kahola wrote:
Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this, so we can follow their
example for the most part. Only the actual hardware programming differs,
the rest is pretty much the same.
The pipe p
sorry if i am missing something, HSW and BDW requires display audio
controller to be updated with new values once CD clock is modified. how
is this accomplished here ?
regards,
Sivakumar
On 4/7/2015 11:57 AM, Sivakumar Thulasimani wrote:
On 3/31/2015 4:44 PM, Mika Kahola wrote:
Implement
+0530, Sivakumar Thulasimani wrote:
sorry if i am missing something, HSW and BDW requires display audio
controller to be updated with new values once CD clock is modified. how
is this accomplished here ?
I'm hoping the audio driver will query the cdclk frequency after eve
audio in place. With this setup in my HSW
machine I can hear the pink noise played back with DP-HDMI cable
attatched.
speaker-test -c 2 -r 48000 -F S16_LE -t pink --device=plughw:0,7
Cheers,
Mika
On Tue, 2015-04-07 at 14:06 +0530, Sivakumar Thulasimani wrote:
where can i check this (audio
Thanks for the confirmation, Mika :). then this change is fine
not sure if it is still relevant but you can add rb if possible
Reviewed-by: Sivakumar Thulasimani
On 4/14/2015 12:36 PM, Mika Kahola wrote:
With pink noise you can't tell if the audio is played faster or slower.
I tested th
From: "Thulasimani, Sivakumar"
HPD storm is detected in intel_hpd_irq_handler and disabled for respective
port immediately but polling is enabled only in i915_hotplug_work_func and
not in i915_digport_work_func. This will result in disabled hpd never enabled
back again. This is fixed by calling t
DPLL_REFA_CLK_ENABLE_VLV |
DPLL_INTEGRATED_CRI_CLK_VLV);
}
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
since we keep DPLL_VGA_MODE_DIS always set, even during disable is this
needed explicitly again here ? other than this i am fine with this.
Reviewed-by: Sivakumar
Reviewed-by: Sivakumar Thulasimani
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Drop the spurious 'A' from the VLV/CHV ref clock enable define,
and add the "REF" to the VLV ref clock selection bit. Also
s/CLOCK/CLK/ for extra consist
On 6/29/2015 10:07 PM, Daniel Vetter wrote:
On Mon, Jun 29, 2015 at 04:30:40PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani, Sivakumar"
HPD storm is detected in intel_hpd_irq_handler and disabled for respective
port immediately but polling is enabled only in i915_hotplug
On 7/1/2015 11:04 AM, Vandana Kannan wrote:
This patch contains changes based on 2 updates to the spec:
Port PLL VCO restriction raised up to 6700.
Port PLL now needs DCO amp override enable for all VCO frequencies.
v2: Sonika's review comment addressed
- dcoampovr_en_h variable not re
thanks for the changes.
Reviewed-by: Sivakumar Thulasimani
On 7/1/2015 5:02 PM, Vandana Kannan wrote:
This patch contains changes based on 2 updates to the spec:
Port PLL VCO restriction raised up to 6700.
Port PLL now needs DCO amp override enable for all VCO frequencies.
v2: Sonika&#
, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 08:45:48AM +0530, Sivakumar Thulasimani wrote:
On 6/29/2015 10:07 PM, Daniel Vetter wrote:
On Mon, Jun 29, 2015 at 04:30:40PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani, Sivakumar"
HPD storm is detected in intel_hpd_irq_h
On 7/3/2015 6:27 PM, Ville Syrjälä wrote:
On Fri, Jul 03, 2015 at 02:35:49PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The req
On 7/2/2015 6:35 PM, Jani Nikula wrote:
Add an overview of the drm/i915 hotplug handling.
Signed-off-by: Jani Nikula
---
Documentation/DocBook/drm.tmpl | 5 +
drivers/gpu/drm/i915/intel_hotplug.c | 39
2 files changed, 44 insertions(+)
diff
Reviewed-by: Sivakumar Thulasimani
On 7/6/2015 5:40 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Use port_clock instead of link_bw when picking the PLL parameters for
DP. link_bw may be zero with an eDP 1.4 sink that supports
DP_LINK_RATE_SET so we shouln't use i
Reviewed-by: Sivakumar Thulasimani
On 7/6/2015 5:40 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
All the *_ddi_pll_select() functions get passed the port_clock and pipe
config as parameters. We only need to pass the pipe config, and the
functions can dig up the port_clock
Reviewed-by: Sivakumar Thulasimani
On 7/6/2015 5:40 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Use a separate variable for the TRANS_DP_CTL value instead of reusing
'tmp' that otherwise contains the DP port register value.
Signed-off-by: Ville Syrjälä
---
d
Reviewed-by: Sivakumar Thulasimani
On 7/6/2015 5:40 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
intel_dp->link_bw is going away, so consul the port_clock instead when
choosing between TP1 and TP3.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c
Reviewed-by: Sivakumar Thulasimani
On 7/6/2015 5:40 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
We only need the link_bw/rate_select parameters when starting link
training, and they should be computed based on the currently active
config, so throw them out from intel_dp
On 7/6/2015 5:42 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
DP dongles may signal downstream HPD via short HPD pulses. If we know
the device has a HPD capable downstream port, make sure we kick off the
full hotplug processing even for short HPDs.
Additonally setting the sin
From: "Thulasimani,Sivakumar"
Update the hotplug documentation to explain that hotplug storm
is not expected for Display port panels and hence is not handled
in current code.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_hotplug.c |4
1 file
On 7/7/2015 4:40 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 03:26:36PM +0530, Sivakumar Thulasimani wrote:
On 7/6/2015 5:42 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
DP dongles may signal downstream HPD via short HPD pulses. If we know
the device has a HPD capable
On 7/7/2015 5:24 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 02:37:46PM +0300, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 04:45:11PM +0530, Sivakumar Thulasimani wrote:
On 7/7/2015 4:40 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 03:26:36PM +0530, Sivakumar Thulasimani wrote
On 7/7/2015 5:50 PM, Sivakumar Thulasimani wrote:
On 7/7/2015 5:24 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 02:37:46PM +0300, Ville Syrjälä wrote:
On Tue, Jul 07, 2015 at 04:45:11PM +0530, Sivakumar Thulasimani wrote:
On 7/7/2015 4:40 PM, Ville Syrjälä wrote:
On Tue, Jul 07, 2015
On 7/7/2015 5:01 PM, Daniel Vetter wrote:
On Tue, Jul 07, 2015 at 04:10:49PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
Update the hotplug documentation to explain that hotplug storm
is not expected for Display port panels and hence is not handled
in cu
dropping this patch as i understood more about
SINK_COUNT dpcd and DOWNSTREAM_PORT_PRESENT dpcd.
will upload a new series with proper fix.
On 8/17/2015 6:21 PM, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
Compliance test 4.2.2.8 requires driver to read the sink_count
From: "Thulasimani,Sivakumar"
These patches together help detect DP displays on short pulse HPD
and pass the respective compliance test case (4.2.2.8)
v2: modifed first patch so we will read sink_count independent of
downstream ports availablility.
Thulasimani,Sivakumar (3):
drm/i915: read s
ned-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 33 ++---
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8a66a44..9e4e27d 100644
--- a/drivers/gpu/drm/i915/intel_
From: "Thulasimani,Sivakumar"
Sink count can change between short pulse hpd hence this patch
adds a member variable to intel_dp so we can track any changes
between short pulse interrupts.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |5 ++---
drive
unplug of panels
through dongles that give only short pulse for such events.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/
On 8/26/2015 3:17 PM, Jani Nikula wrote:
On Tue, 25 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port dpcd. Also
we should read it irrespective of current
On 8/26/2015 3:32 PM, Jani Nikula wrote:
On Tue, 25 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change. This will
result in compliance test ca
On 8/26/2015 3:32 PM, Jani Nikula wrote:
On Tue, 25 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change. This will
result in compliance test ca
On 8/26/2015 5:21 PM, Ville Syrjälä wrote:
On Tue, Aug 25, 2015 at 05:20:36PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port dpcd. Also
we should read it ir
On 8/18/2015 1:36 AM, Benjamin Tissoires wrote:
On Aug 14 2015 or thereabouts, Stéphane Marchesin wrote:
On Wed, Aug 5, 2015 at 12:34 PM, Benjamin Tissoires
wrote:
On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote:
On 7/29/2015 8:52 PM, Benjamin Tissoires wrote:
On Jul 29 2015
On 8/20/2015 1:17 PM, Jani Nikula wrote:
Add a common intel_digital_port_connected() that splits out to functions
for different platforms. No functional changes.
v2: make the function return a boolean
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 41 +
On 8/26/2015 7:59 PM, Benjamin Tissoires wrote:
On Aug 26 2015 or thereabouts, Sivakumar Thulasimani wrote:
On 8/18/2015 1:36 AM, Benjamin Tissoires wrote:
On Aug 14 2015 or thereabouts, Stéphane Marchesin wrote:
On Wed, Aug 5, 2015 at 12:34 PM, Benjamin Tissoires
wrote:
On Jul 30 2015
On 8/27/2015 12:30 PM, Jani Nikula wrote:
On Wed, 26 Aug 2015, Sivakumar Thulasimani
wrote:
On 8/20/2015 1:17 PM, Jani Nikula wrote:
Add a common intel_digital_port_connected() that splits out to functions
for different platforms. No functional changes.
v2: make the function return a
On 8/27/2015 1:38 PM, Jani Nikula wrote:
On Thu, 27 Aug 2015, Sivakumar Thulasimani
wrote:
On 8/27/2015 12:30 PM, Jani Nikula wrote:
On Wed, 26 Aug 2015, Sivakumar Thulasimani
wrote:
On 8/20/2015 1:17 PM, Jani Nikula wrote:
Add a common intel_digital_port_connected() that splits out to
From: "Thulasimani,Sivakumar"
These patches together help detect DP displays on short pulse HPD
and pass the respective compliance test case (4.2.2.8)
v2: modifed first patch so we will read sink_count independent of
downstream ports availablility.
v3: split first patch so crtc enabled check is
iable type from u8 to bool (Jani)
return immediately if perform_full_detect is set(Siva)
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
0 no display is attached
0 1 dongle is connected without display
1 0 display connected directly
1 1 display connected through dongle
v2: moved out crtc enabled checks to prior patch(Jani)
Signed-off-by:
From: "Thulasimani,Sivakumar"
sink count can change between short pulse hpd hence this patch
adds a member variable to intel_dp so we can track any changes
between short pulse interrupts.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |5 ++---
drive
2.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8a66a44..76561e0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++
On 9/1/2015 4:12 PM, Jani Nikula wrote:
On Thu, 27 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change.
This will allow both detection of hotplug
On 9/1/2015 3:59 PM, Jani Nikula wrote:
On Thu, 27 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port dpcd.
SINK_COUNT dpcd is not de
On 9/1/2015 6:45 PM, Jani Nikula wrote:
On Tue, 01 Sep 2015, Sivakumar Thulasimani
wrote:
On 9/1/2015 3:59 PM, Jani Nikula wrote:
On Thu, 27 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch reads sink_count dpcd always and removes its
read
On 8/20/2015 10:07 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
We are no longer checkling the DP link status on long hpd. We used to do
that from the .hot_plug() handler, but it was removed when MST got
introduced.
If there's no userspace we now fail to retrain the link if t
On 9/2/2015 2:43 PM, Daniel Vetter wrote:
On Thu, Aug 27, 2015 at 02:18:32PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change.
This will allow both
g
Reviewed-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c |6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b1fe32b..3e277c4 100644
--- a/drive
Reviewed-by: Sivakumar Thulasimani
On 9/18/2015 2:11 PM, Sonika Jindal wrote:
Bspec update tells that we have to enable oscaledcompmethod instead of
ouniqetrangenmethod for enabling scale value during swing programming.
Also, scale value is 'don't care' for other levels except
Reviewed-by: Sivakumar Thulasimani
On 9/18/2015 2:11 PM, Sonika Jindal wrote:
Adding voltage swing table for edp to support low vswings.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff
On 9/22/2015 6:32 PM, Imre Deak wrote:
On ma, 2015-09-21 at 23:00 +0530, Sivakumar Thulasimani wrote:
Reviewed-by: Sivakumar Thulasimani
On 9/18/2015 2:11 PM, Sonika Jindal wrote:
Bspec update tells that we have to enable oscaledcompmethod instead of
ouniqetrangenmethod for enabling scale
Reviewed-by: Sivakumar Thulasimani
On 4/20/2015 5:08 PM, Durgadoss R wrote:
This patch creates a connector specific debugfs
interface to read any particular DPCD register.
The DPCD register address (hex format) is written
to 'i915_dpcd_addr' interface and the corresponding
value c
we still don't have code to enumerate DDI E or DDI D. but this will
handle them when this bit is missed by GOP/VBIOS during boot up.
Reviewed-by: Sivakumar Thulasimani
On 4/23/2015 5:58 PM, Sonika Jindal wrote:
Currently, if bios fails to drive an edp panel due to any reason,
the ddi b
On 4/28/2015 12:13 PM, Mika Kahola wrote:
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
On 4/28/2015 1:44 PM, Mika Kahola wrote:
On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
On 4/28/2015 12:13 PM, Mika Kahola wrote:
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
Signed-off-by: Mika Kahola
On 4/28/2015 3:12 PM, Mika Kahola wrote:
On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote:
On 4/28/2015 1:44 PM, Mika Kahola wrote:
On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
On 4/28/2015 12:13 PM, Mika Kahola wrote:
This patch adds DP link training
Reviewed-by: Sivakumar Thulasimani
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.
In
Reviewed-by: Sivakumar Thulasimani
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
V4:
- when HPD long pulse is received, the flag is cleared
that indicates if DP link training is
Reviewed-by: Sivakumar Thulasimani
On 5/4/2015 8:50 PM, Vandana Kannan wrote:
BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.
VCO calculated based on the formula:
Desired Output = Port bit rate in MHz (DisplayPort
On 5/4/2015 7:50 PM, Jani Nikula wrote:
The eDP port A register on PCH split platforms has a slightly different
register layout from the other ports, with bit 6 being either alternate
scrambler reset or reserved, depending on the generation. Our
misinterpretation of the bit as audio has lead to
Reviewed-by: Sivakumar Thulasimani
On 5/4/2015 7:50 PM, Jani Nikula wrote:
We should no longer enter the codec enable/disable functions in question
with port A anyway, but to err on the safe side, keep the warnings. Just
bail out early without messing with the registers.
Signed-off-by: Jani
Nikula wrote:
On Tue, 05 May 2015, Sivakumar Thulasimani
wrote:
On 5/4/2015 7:50 PM, Jani Nikula wrote:
The eDP port A register on PCH split platforms has a slightly different
register layout from the other ports, with bit 6 being either alternate
scrambler reset or reserved, depending on the
sure, you can check for port A alone then. DDI A will have edp in all
SKUs so checking for eDP should ideally be the same as DDIA.
On 5/5/2015 7:02 PM, Jani Nikula wrote:
On Tue, 05 May 2015, Sivakumar Thulasimani
wrote:
two points
1) The eDP spec says Audio is optional so it is allowed to
missed the changes attached. so adding rb tag
Reviewed-by: Sivakumar Thulasimani
On 5/5/2015 7:02 PM, Jani Nikula wrote:
On Tue, 05 May 2015, Sivakumar Thulasimani
wrote:
two points
1) The eDP spec says Audio is optional so it is allowed to have audio,
but i am yet to come across any eDP
On 2/27/2015 1:14 PM, Jani Nikula wrote:
On Fri, 27 Feb 2015, Todd Previte wrote:
Hi Mika,
On 2/26/2015 2:26 AM, Mika Kahola wrote:
In a case when DP link has been once trained we can reuse
the existing link training parameters i.e. voltage swing
and pre-emphasis levels from cache when there
On 7/8/2015 8:50 PM, Daniel Vetter wrote:
On Wed, Jul 08, 2015 at 06:54:06PM +0530, Sivakumar Thulasimani wrote:
On 7/7/2015 5:01 PM, Daniel Vetter wrote:
On Tue, Jul 07, 2015 at 04:10:49PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
Update the hotplug doc
From: "Thulasimani,Sivakumar"
Update the hotplug documentation to explain that hotplug storm
is not expected for Display port panels and hence is not handled
in current code.
v2: update the statements as recommended by Daniel
Signed-off-by: Sivakumar Thulasimani
---
drivers/gp
Reviewed-by: Sivakumar Thulasimani
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
The pipe A power well is the "disp2d" well on CHV and pipe B and C wells
don't even exist. Thereforce we can remove the checks for pipe A vs.
others and just ass
Reviewed-by: Sivakumar Thulasimani
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
We do the exact same steps around the disp2d/pipe A power well
enable/disable on VLV and CHV. Refactor the shared code into
some helpers.
Note that this means we now call
Reviewed-by: Sivakumar Thulasimani
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
VLV/CHV don't use the DPLL with DSI, so just clear out the DPLL state
from the pipe_config in intel_dsi_get_config(). This avoids spurious
state checker warnings. We al
On 7/1/2015 6:12 PM, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 02:50:33PM +0300, Ville Syrjälä wrote:
On Tue, Jun 30, 2015 at 12:13:37PM +0200, Daniel Vetter wrote:
On Mon, Jun 29, 2015 at 08:08:27PM +0300, Ville Syrjälä wrote:
On Mon, Jun 29, 2015 at 07:56:05PM +0300, Ville Syrjälä wrote
Reviewed-by: Sivakumar Thulasimani
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
and having VGA mode enabled causes some problems for CHV. So let's just
pull the code to configure those
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
DPLL_MD(PIPE_C) is AWOL on CHV. Instead of fixing it someone added
chicken bits to propagate the pixel multiplier from DPLL_MD(PIPE_B)
to either pipe B or C. So do that to make pixel repeat work on pipes
B and C. P
Reviewed-by: Sivakumar Thulasimani
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
The BIOS maybe leave the DSI PLL enabled even if the port is disabled.
The PLL doesn't seem to like being reconfigured while it's enabled so
make sure it's
On 7/13/2015 9:47 AM, Sonika Jindal wrote:
As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic
and interrupts to check the external panel connection.
And remove the redundant comment.
v2: Remove redundant IS_BROXTON check, Add comment about port C not
connected, and rephrase the co
On 7/13/2015 2:21 PM, Daniel Vetter wrote:
On Fri, Jul 10, 2015 at 05:37:07PM +0530, Sivakumar Thulasimani wrote:
On 7/1/2015 6:12 PM, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 02:50:33PM +0300, Ville Syrjälä wrote:
On Tue, Jun 30, 2015 at 12:13:37PM +0200, Daniel Vetter wrote:
On Mon
On 7/13/2015 3:10 PM, Daniel Vetter wrote:
On Mon, Jul 13, 2015 at 02:10:09PM +0530, Sonika Jindal wrote:
As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic
and interrupts to check the external panel connection.
And remove the redundant comment.
v2: Remove redundant IS_BROXTON ch
On 7/21/2015 3:13 AM, Imre Deak wrote:
These functions are quite similar, so combine them with the use of a new
argument for a function that detects long pulses. This will be also
needed by an upcoming patch adding support for BXT long pulse detection.
No functional change.
Signed-off-by: Imr
his change looks good.
Reviewed-by: Sivakumar Thulasimani
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 3c53aac..8cda7b9 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -29,17 +29,23 @@
On 7/21/2015 11:28 PM, Imre Deak wrote:
On Tue, 2015-07-21 at 13:50 +0530, Sivakumar Thulasimani wrote:
On 7/21/2015 3:13 AM, Imre Deak wrote:
These functions are quite similar, so combine them with the use of a new
argument for a function that detects long pulses. This will be also
needed
5_WRITE(BXT_HOTPLUG_CTL, hp_control);
- pch_get_hpd_pins(&pin_mask, &long_mask, hp_trigger, hp_control, hpd_bxt);
+ intel_get_hpd_pins(&pin_mask, &long_mask, hp_trigger, hp_control,
+ hpd_bxt, pch_port_hotplug_long_detect);
intel_h
.
No functional change.
v2:
- rebase on top of -nightly (Daniel)
- make the check for intel_hpd_pin_to_port() return value more readable
(Sivakumar)
Signed-off-by: Imre Deak
Reviewed-by: Sonika Jindal
Reviewed-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gp
DURATION_2ms(0)
#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
Reviewed-by: Sivakumar Thulasimani
--
regards,
Sivakumar
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From: "Thulasimani,Sivakumar"
DP spec requires the checksum of the last block read to be written
when replying to TEST_EDID_READ. This patch fixes the current code
to do the same.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 11 ++-
1 file c
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