On 09/05/2014 22:18, Volkin, Bradley D wrote:
On Mon, Apr 28, 2014 at 08:01:29AM -0700, arun.siluv...@linux.intel.com wrote:
From: "Siluvery, Arun"
This patch adds support to have gem objects of variable size.
The size of the gem object obj->size is always constant and this fa
On 12/05/2014 18:02, Eric Anholt wrote:
arun.siluv...@linux.intel.com writes:
From: "Siluvery, Arun"
This patch adds support to have gem objects of variable size.
The size of the gem object obj->size is always constant and this fact
is tightly coupled in the driver; this i
Hi,
I am working on a feature to implement support for gem objects to have
variable size and realized a problem with the current implementation.
Please advice me how to handle this situation efficiently.
In this implementation the backing store of the object is replaced with
scratch pages acc
On 12/06/2014 08:26, Daniel Vetter wrote:
On Thu, Jun 12, 2014 at 12:49:47AM +0100, Siluvery, Arun wrote:
Hi,
I am working on a feature to implement support for gem objects to have
variable size and realized a problem with the current implementation.
Please advice me how to handle this
> > On Tue, 2014-02-25 at 11:52 +, Arun Siluvery wrote:
> >> >Hi Everyone,
> >> >
> >> >There is a requirement to defer physical mapping of higher level
> >> >mipmaps. Texture download and usage are separate and you cannot know
> >> >beforehand whether higher level mipmaps are required at the t
On 27/03/2014 22:23, Chris Wilson wrote:
On Thu, Mar 27, 2014 at 03:28:26PM +, arun.siluv...@linux.intel.com wrote:
From: "Siluvery, Arun"
This patch series adds a new ioctl to resize a gem object.
I'm tired, but off the top of my head, I think you can do away with the
On 27/03/2014 22:23, Chris Wilson wrote:
On Thu, Mar 27, 2014 at 03:28:26PM +, arun.siluv...@linux.intel.com wrote:
From: "Siluvery, Arun"
This patch series adds a new ioctl to resize a gem object.
I'm tired, but off the top of my head, I think you can do away with the
Hi All,
I am running a repetitive test on HSW with max available RAM limited to
1GB (max TOLUD is 1GB) and it fails with NULL pointer dereference in
execbuf ioctl.
Debug showed that the batch_obj->gtt_space which was valid becomes NULL
before it is dispatched. During debug I stored batch_obj->gtt
From: "Siluvery, Arun"
When a mapping is requested and if there is no space the mapping fails
and the region is not physically backed. This results in
signal 7(SIGBUS), code 2 (BUS_ADRERR) when it is actually accessed.
This patch handles this error, continues to wait and retries to
From: "Siluvery, Arun"
This patchset contains changes for Timeout detection and recovery (TDR) which
provides per-engine hang detection and recovery.
The current driver performs full gpu reset in case of a hang, TDR attempts to
only reset the engine that is hung and it falls back to
From: "Siluvery, Arun"
Instead of full GPU reset, where possible a single ring can be reset
individually. This patch adds functions to save ring's current state and
it will be restored with the same state after reset. The state comprises
of a set of ring specific registers. T
From: "Siluvery, Arun"
TDR provides per-engine hang detection and recovery. If an engine hangs then
the TDR will attempt to reset the engine and advance the command streamer to
the next instruction in the ring. If it was in the middle of processing a
batch buffer then control retu
From: "Siluvery, Arun"
This patch adds changes to keep track of the number of the times TDR is
triggered and the results for each ring are made available through debugfs.
Signed-off-by: Siluvery, Arun
---
drivers/gpu/drm/i915/i915_debugfs.c | 62
On Mon, 2013-11-11 at 16:31 +0100, Daniel Vetter wrote:
> On Mon, Nov 11, 2013 at 02:58:31PM +0000, Siluvery, Arun wrote:
> > From: "Siluvery, Arun"
> >
> > This patchset contains changes for Timeout detection and recovery (TDR)
> > which
> > prov
On 02/03/2015 10:10, Michel Thierry wrote:
On 25/02/15 17:54, Arun Siluvery wrote:
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround batch buffers are create
On 02/03/2015 11:02, Arun Siluvery wrote:
Please ignore this one. I used message id of cover letter instead of v1
of this patch. Latest patches are sent in reply to their initial revisions.
regards
Arun
From: Namrta
This can be used to enable WA BB infrastructure for features like
RC6, SSE
On 02/03/2015 17:43, Daniel Vetter wrote:
On Mon, Mar 02, 2015 at 11:07:20AM +, Arun Siluvery wrote:
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround batc
On 28/10/2014 12:23, Ville Syrjälä wrote:
On Tue, Oct 28, 2014 at 11:57:50AM +, Arun Siluvery wrote:
WaDisableInstructionShootdown:chv
WaForceEnableNonCoherent:chv
WaHdcDisableFetchWhenMasked:chv
WaDisableFenceDestinationToSLM:chv (pre-production)
s/WaDisableDopClockGating/WaDisableRowChick
On 28/10/2014 17:06, Ville Syrjälä wrote:
On Tue, Oct 28, 2014 at 03:48:24PM +, Arun Siluvery wrote:
+WaForceEnableNonCoherent:chv
+WaHdcDisableFetchWhenMasked:chv
-WaDisableDopClockGating:chv
-WaDisableSamplerPowerBypass:chv
-WaDisableGunitClockGating:chv
-WaDisableFfDopClockGating:chv
-WaD
On 28/10/2014 18:33, Arun Siluvery wrote:
The patches in this series adds two new workarounds for CHV and
removes pre-production ones.
Based on review comments from Ville, add/remove patches are split-up
which helps in reverting them if required.
The initial patch can be found at,
https://patch
On 04/11/2014 19:23, Rodrigo Vivi wrote:
These patches got listed to -collector but got a huge conflict. If it
is still relevant please rebase it.
This patch is currently not relevant, rebased version is already sent to
the list for review.
https://patchwork.kernel.org/patch/5178771/
regards
On 17/11/2014 15:54, Daniel, Thomas wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Arun Siluvery
Sent: Monday, November 17, 2014 3:48 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Free
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for
On 05/12/2014 17:36, Jani Nikula wrote:
On Fri, 05 Dec 2014, "Siluvery, Arun" wrote:
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel cl
On 25/06/2014 12:14, Damien Lespiau wrote:
On Wed, Jun 25, 2014 at 11:51:33AM +0100, Damien Lespiau wrote:
(This is not necessarily things one would need to take into account for
this work, just a few thoughts).
One thing I'm wondering is how fitting the "size" parameter really is
when talking
On 07/07/2014 22:24, Daniel Vetter wrote:
On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes wrote:
I don't think it's unreasonable to use a macro that checks a global
list for whether to apply a given WA. They'll be scattered all over,
but at least it'll be easy to see:
1) whether we implement
On 24/07/2014 13:33, Daniel Vetter wrote:
On Thu, Jul 24, 2014 at 11:43:11AM +0100, Siluvery, Arun wrote:
On 07/07/2014 22:24, Daniel Vetter wrote:
On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes wrote:
I don't think it's unreasonable to use a macro that checks a global
list for
On 28/07/2014 20:22, Daniel Vetter wrote:
On Mon, Jul 28, 2014 at 08:00:39PM +0300, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 05:31:46PM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery
The workarounds at the moment are initialized in init_clock_gating() but
they are lost du
On 28/07/2014 18:00, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 05:31:46PM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery
The workarounds at the moment are initialized in init_clock_gating() but
they are lost during reset; In case of execlists some workarounds modify
registe
On 28/07/2014 18:26, Ville Syrjälä wrote:
On Mon, Jul 28, 2014 at 05:31:45PM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery
This patch moves BDW workarounds from init_clock_gating() to render ring
init fn otherwise they are lost when gpu is reset.
In case of execlists, some of
On 08/08/2014 10:57, Chris Wilson wrote:
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the registers are part of register
state
On 08/08/2014 13:20, Ville Syrjälä wrote:
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the registers are part of register
stat
On 08/08/2014 15:12, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 10:54:56AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which captures register state before and after
the test
On 05/06/2015 11:56, Chris Wilson wrote:
On Fri, Jun 05, 2015 at 11:34:01AM +0100, Arun Siluvery wrote:
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are crea
On 05/06/2015 12:36, Chris Wilson wrote:
On Fri, Jun 05, 2015 at 12:24:58PM +0100, Siluvery, Arun wrote:
ok, it is possible to do the allocation and setup in
logical_ring_init() itself. I wanted to group it with other wa which
are setup in init_context().
Phew, I had worried I had missed
On 09/06/2015 16:27, Dave Gordon wrote:
On 05/06/15 11:34, Arun Siluvery wrote:
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scra
On 05/06/2015 15:48, Ville Syrjälä wrote:
On Fri, Jun 05, 2015 at 02:56:48PM +0100, Arun Siluvery wrote:
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
so as to not break a
On 12/06/2015 18:03, Dave Gordon wrote:
On 12/06/15 12:58, Siluvery, Arun wrote:
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
On 15/06/2015 11:41, Daniel Vetter wrote:
On Thu, Jun 04, 2015 at 03:30:56PM +0100, Siluvery, Arun wrote:
On 02/06/2015 19:47, Dave Gordon wrote:
On 02/06/15 19:36, Siluvery, Arun wrote:
On 01/06/2015 11:22, Daniel, Thomas wrote:
Indeed, allocating an extra scratch page in the context would
On 15/06/2015 16:22, Daniel Vetter wrote:
On Fri, Jun 05, 2015 at 12:00:54PM +0100, Chris Wilson wrote:
On Fri, Jun 05, 2015 at 11:34:01AM +0100, Arun Siluvery wrote:
+ /* FIXME: fill unused locations with NOOPs.
+* Replace these instructions with WA
+*/
+while (in
On 15/06/2015 18:29, Dave Gordon wrote:
On 15/06/15 15:10, Siluvery, Arun wrote:
On 12/06/2015 18:03, Dave Gordon wrote:
On 12/06/15 12:58, Siluvery, Arun wrote:
On 09/06/2015 19:43, Dave Gordon wrote:
On 05/06/15 14:57, Arun Siluvery wrote:
In Per context w/a batch buffer
On 16/06/2015 21:33, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
+{
+ int ret;
+ struct drm_device *dev = ring->dev;
You only use it once, keeping it as a local seems cou
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
+ uint32_t offset,
+ uint32_t *num_dwords)
+{
+ uin
On 17/06/2015 19:48, Siluvery, Arun wrote:
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
+ uint32_t offset
On 17/06/2015 21:21, Chris Wilson wrote:
On Wed, Jun 17, 2015 at 07:48:16PM +0100, Siluvery, Arun wrote:
On 16/06/2015 21:25, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
+static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring
On 15/06/2015 06:20, Daniel Vetter wrote:
On Wed, Jun 3, 2015 at 6:14 PM, Ville Syrjälä
wrote:
I was going to suggest removing the same thing from the
lrc_setup_hardware_status_page(), but after another look it seems we
sometimes call .init_hw() before the context setup. Would be nice to
have a
On 19/06/2015 10:27, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 06:33:24PM +0100, Arun Siluvery wrote:
Totally minor worries now.
+/**
+ * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
+ *
+ * @ring: only applicable for RCS
+ * @wa_ctx_batch: page in which WA are loaded
+
On 19/06/2015 19:09, Chris Wilson wrote:
On Fri, Jun 19, 2015 at 06:37:14PM +0100, Arun Siluvery wrote:
In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with th
On 19/06/2015 18:37, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
On 22/06/2015 16:36, Daniel Vetter wrote:
On Fri, Jun 19, 2015 at 06:50:36PM +0100, Chris Wilson wrote:
On Fri, Jun 19, 2015 at 06:37:10PM +0100, Arun Siluvery wrote:
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before e
On 22/06/2015 16:41, Daniel Vetter wrote:
On Fri, Jun 19, 2015 at 07:07:01PM +0100, Arun Siluvery wrote:
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are cre
On 22/06/2015 17:21, Ville Syrjälä wrote:
On Fri, Jun 19, 2015 at 06:37:15PM +0100, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.
v2
On 22/06/2015 17:59, Siluvery, Arun wrote:
On 22/06/2015 17:21, Ville Syrjälä wrote:
On Fri, Jun 19, 2015 at 06:37:15PM +0100, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
This WA performs writes to scratch page so it must be valid, this check
is performed
On 23/06/2015 15:36, Imre Deak wrote:
On ti, 2015-06-23 at 15:31 +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 05:26:13PM +0300, Imre Deak wrote:
On the GEN!=8 error path we call kmap_atomic() which returns in atomic
context and then lrc_destroy_wa_ctx_obj() which can be called only in
pro
On 23/06/2015 17:01, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 06:58:42PM +0300, Imre Deak wrote:
On ti, 2015-06-23 at 16:44 +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 06:18:21PM +0300, Imre Deak wrote:
On ti, 2015-06-23 at 16:13 +0100, Siluvery, Arun wrote:
On 23/06/2015 15:36
On 16/06/2015 11:39, Abdiel Janulgue wrote:
GEN8 and above uses Execlists by default instead of the legacy
ringbuffer for batch execution. This patch enables the resource
streamer bits when required.
Patch is based on the initial work by Minu Mathai
This version also adds the required bits to e
On 03/07/2015 17:57, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 05:53:38PM +0100, Arun Siluvery wrote:
This patch only enables support for Gen9, the actual WA will be
initialized in subsequent patches.
The WARN that we use to warn user if WA batch support is not available
for a particular Gen
On 06/07/2015 12:52, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
instruction but there is a slight complication as this is applied in WA b
On 07/07/2015 20:13, Francisco Jerez wrote:
From: Peter Antoine
This change adds the programming of the MOCS registers to the gen 9+
platforms. This change set programs the MOCS register values to a set
of values that are defined to be optimal.
It creates a fixed register set that is programme
On 24/08/2015 12:58, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma
This patch provides support for the User to populate the object
with system pages at its creation time. Since this can be safely
performed without holding the 'struct_mutex', it would help to reduce
the time 'st
On 29/05/2015 19:16, Chris Wilson wrote:
On Fri, May 29, 2015 at 07:03:19PM +0100, Arun Siluvery wrote:
This patch adds functions to setup WA batch buffers but they are not yet
enabled in this patch. Some of the WA are to be applied during context save
but before restore and some at the end of c
On 01/06/2015 11:22, Daniel, Thomas wrote:
Indeed, allocating an extra scratch page in the context would simplify
vma/mm management. A trick might be to allocate the scratch page at the
start, then offset the lrc regs etc - that would then be consistent
amongst gen and be easy enough to extend i
On 02/06/2015 19:47, Dave Gordon wrote:
On 02/06/15 19:36, Siluvery, Arun wrote:
On 01/06/2015 11:22, Daniel, Thomas wrote:
Indeed, allocating an extra scratch page in the context would simplify
vma/mm management. A trick might be to allocate the scratch page at the
start, then offset the lrc
On 21/01/2015 17:37, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Wa4x4STCOptimizationDisable got only implemented for BDW, but according
to the w/a database CHV needs it too, so add it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4
1 file c
Hi,
Could someone explain the significance of Null context/Golden state?
I understand we are initializing 3D state in this batch and we send this
at the beginning to start the HW with a known state but what are
implications of not doing this? what kind of issues we can expect if we
don't do th
On 01/08/2014 17:34, Jesse Barnes wrote:
On Thu, 31 Jul 2014 12:08:20 -0700
Rodrigo Vivi wrote:
WA to skip the first page of stolen memory due to sporadic HW write on *CS Idle
v2: Improve variable names and fix allocated size.
Reviewed-by: Ben Widawsky
Signed-off-by: Rodrigo Vivi
---
dri
On 10/07/2015 09:25, Dan Carpenter wrote:
Hello Arun Siluvery,
The patch 9e00084750c0: "drm/i915: Update
WaFlushCoherentL3CacheLinesAtContextSwitch" from Jul 3, 2015, leads
to the following static checker warning:
drivers/gpu/drm/i915/intel_lrc.c:1188 gen8_init_indirectctx_bb()
On 10/07/2015 16:52, Mika Kuoppala wrote:
Arun Siluvery writes:
This patch only enables support for Gen9, the actual WA will be
initialized in subsequent patches.
The WARN that we use to warn user if WA batch support is not available
for a particular Gen is replaced with DRM_ERROR as warning
On 11/07/2015 20:09, Chris Wilson wrote:
On Sat, Jul 11, 2015 at 08:05:05PM +0100, Chris Wilson wrote:
On Fri, Jul 10, 2015 at 06:35:18PM +0100, Arun Siluvery wrote:
These patches enabled Pooled EU support for BXT, they are implemented
by Armin Reese. I am sending these patches in its current f
On 16/07/2015 15:36, Mika Kuoppala wrote:
Kunmap the renderstate page on error path.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/dr
On 17/07/2015 17:27, Chris Wilson wrote:
On Fri, Jul 17, 2015 at 05:08:53PM +0100, Arun Siluvery wrote:
This mode allows to assign EUs to pools.
The command to enable this mode is sent in auxiliary golden context batch
as this is only issued once with each context initialization. Thanks to
Mika
On 17/07/2015 19:13, Arun Siluvery wrote:
User space clients need to know when the pooled EU feature is present
and enabled on the hardware so that they can adapt work submissions.
Create a new device info flag for this purpose, and create a new GETPARAM
entry to allow user space to query its set
On 17/07/2015 21:03, Chris Wilson wrote:
On Fri, Jul 17, 2015 at 07:13:32PM +0100, Arun Siluvery wrote:
The Golden batch carries 3D state at the beginning so that HW starts with
a known state. It is carried as a binary blob which is auto-generated from
source. The idea was it would be easier to
On 16/07/2015 16:19, Arun Siluvery wrote:
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM instructions are not really
variable length instructions unlike MI_LOAD_REGISTER_IMM where it expects
(reg, addr) pairs so use fixed length for these instructions.
Cc: Dave Gordon
Signed-off-by: Arun Siluvery
On 04/08/2015 09:58, Mika Kuoppala wrote:
Ben Widawsky writes:
On Mon, Aug 03, 2015 at 08:24:56PM +0100, Arun Siluvery wrote:
Cc: Ben Widawsky
Cc: Joonas Lahtinen
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 fil
On 04/08/2015 00:21, Ben Widawsky wrote:
On Mon, Aug 03, 2015 at 08:24:57PM +0100, Arun Siluvery wrote:
This WA is implemented in init_context as well as WA batch init.
There are also some dependent bits need to be set in other registers
for this to be complete.
Cc: Ben Widawsky
Cc: Joonas Lah
On 05/08/2015 15:45, Mika Kuoppala wrote:
Arun Siluvery writes:
This WA is implemented in init_context as well as WA batch init.
There are also some dependent bits need to be set in other registers
for this to be complete.
v2: behaviour of disable gather at set shader bit can be specified by
On 06/08/2015 14:51, Mika Kuoppala wrote:
Add WaDisableSbeCacheDispatchPortSharing:skl
Cc: Arun Siluvery
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu
On 06/08/2015 15:45, Mika Kuoppala wrote:
"Siluvery, Arun" writes:
On 06/08/2015 14:51, Mika Kuoppala wrote:
Add WaDisableSbeCacheDispatchPortSharing:skl
Cc: Arun Siluvery
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file
On 07/08/2015 12:52, Daniel Vetter wrote:
On Fri, Aug 07, 2015 at 11:15:56AM +0300, Mika Kuoppala wrote:
Daniel Vetter writes:
On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
If idle to active bit is set, the rest of the fields
in CSQ are not valid.
Bail out early if this is
On 08/08/2015 06:35, Ben Widawsky wrote:
On Fri, Aug 07, 2015 at 06:33:37PM +0100, Arun Siluvery wrote:
This WA doesn't have a name. According to the spec, driver need to reset
disable gather at set shader bit in per ctx WA batch. It is to be noted
that the default value is already '0' for this
On 11/08/2015 13:25, Mika Kuoppala wrote:
Don't set the size of bindless surface state on rendercopy.
And as of doing so, take into account the workaround for setting
the command size.
This was tried during hunting for
https://bugs.freedesktop.org/show_bug.cgi?id=89959. But no
impact was found.
On 11/08/2015 21:58, Timo Aaltonen wrote:
On 11.08.2015 17:44, Arun Siluvery wrote:
Patch1 fixes a simple compile error in Patch2
Patch2 fixes gpu hang observed with a subtest of gem_concurrent_blit.
Arun Siluvery (1):
drm/i915/gen9: Disable gather at set shader bit
Mika Kuoppala (1):
dr
On 12/08/2015 16:41, Dave Gordon wrote:
On 11/08/15 15:44, Arun Siluvery wrote:
From Gen9, Push constant instruction parsing behaviour varies
according to
whether set shader is enabled or not. If we want legacy behaviour then it
can be achieved by disabling set shader.
Bugzilla: https://bugs.f
On 20/08/2014 16:37, Thomas Wood wrote:
On 20 August 2014 15:52, Arun Siluvery wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test currently verifies only bdw workaro
On 22/08/2014 12:06, Mika Kuoppala wrote:
Ville Syrjälä writes:
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the WA registers are part of register
state context
On 25/08/2014 13:18, Ville Syrjälä wrote:
On Fri, Aug 22, 2014 at 08:39:11PM +0100, Arun Siluvery wrote:
For BDW workarounds are currently initialized in init_clock_gating() but
they are lost during reset, suspend/resume etc; this patch moves the WAs
that are part of register state context to re
On 26/08/2014 11:09, Chris Wilson wrote:
On Tue, Aug 26, 2014 at 10:33:16AM +0100, Arun Siluvery wrote:
For BDW workarounds are currently initialized in init_clock_gating() but
they are lost during reset, suspend/resume etc; this patch moves the WAs
that are part of register state context to ren
On 26/08/2014 11:34, Chris Wilson wrote:
On Tue, Aug 26, 2014 at 11:16:29AM +0100, Siluvery, Arun wrote:
On 26/08/2014 11:09, Chris Wilson wrote:
On Tue, Aug 26, 2014 at 10:33:16AM +0100, Arun Siluvery wrote:
For BDW workarounds are currently initialized in init_clock_gating() but
they are
On 26/08/2014 13:53, Daniel Vetter wrote:
On Fri, Aug 22, 2014 at 01:10:26PM +0100, Siluvery, Arun wrote:
On 22/08/2014 12:06, Mika Kuoppala wrote:
Ville Syrjälä writes:
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
Workarounds for bdw are currently applied in
On 26/08/2014 06:59, Chris Wilson wrote:
On Mon, Aug 25, 2014 at 10:39:39PM +0200, Daniel Vetter wrote:
On Wed, Aug 20, 2014 at 04:36:05PM +0100, Chris Wilson wrote:
On Wed, Aug 20, 2014 at 04:29:24PM +0100, Thomas Daniel wrote:
These two functions make no sense in an Logical Ring Context & Ex
On 26/08/2014 15:37, Ville Syrjälä wrote:
On Tue, Aug 26, 2014 at 02:44:50PM +0100, Arun Siluvery wrote:
For BDW workarounds are currently initialized in init_clock_gating() but
they are lost during reset, suspend/resume etc; this patch moves the WAs
that are part of register state context to re
On 27/08/2014 16:44, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:44:51PM +0100, Arun Siluvery wrote:
The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is only required to support i
On 27/08/2014 16:59, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state b
On 27/08/2014 17:23, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:17:11PM +0100, Siluvery, Arun wrote:
On 27/08/2014 16:59, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some of the
On 29/08/2014 11:16, Chris Wilson wrote:
On Fri, Aug 29, 2014 at 11:02:01AM +0100, Arun Siluvery wrote:
From: Garry Lancaster
libdrm includes a scheme where freed buffer objects (BOs)
are held in a cache. This allows incoming allocation requests to be
serviced by re-using an old BO, instead of
On 30/08/2014 16:50, Damien Lespiau wrote:
Hi Arun,
I've compiled a few patches that I think solve some small-ish issues around
your wa_regs series. Could you please have a look at them and comment/give your
r-b tag if you judge appropriate?
On top of those patches, I'd love some comments on th
On 30/08/2014 16:10, Damien Lespiau wrote:
On Tue, Aug 26, 2014 at 02:44:51PM +0100, Arun Siluvery wrote:
The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is only required to support
On 01/09/2014 10:08, Daniel Vetter wrote:
On Sun, Aug 31, 2014 at 08:32:55PM +0100, Siluvery, Arun wrote:
On 30/08/2014 16:50, Damien Lespiau wrote:
Hi Arun,
I've compiled a few patches that I think solve some small-ish issues around
your wa_regs series. Could you please have a look at
1 - 100 of 111 matches
Mail list logo
