On 06/29/2016 06:24 PM, Shobhit Kumar wrote:
From: Shobhit Kumar
CHV pipe C hits underrun when we get negative crtc_x values of cursor.
To avoid this we clip and shift the cursor image by negative crtc_x
value.
v2: Make a copy of cursor plane state and allocate new gem object and fb
for
On Wed, Jun 29, 2016 at 6:24 PM, Shobhit Kumar
wrote:
>
> From: Shobhit Kumar
>
> CHV pipe C hits underrun when we get negative crtc_x values of cursor.
> To avoid this we clip and shift the cursor image by negative crtc_x
> value.
>
> v2: Make a copy of cursor plane st
missed out
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 25 +++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 24
On Fri, Jul 15, 2016 at 2:33 PM, Shobhit Kumar wrote:
> On devices that have MIPI DSI panel control and PWM control comming from
> CRC PMIC, we need the gpio and pwm exported from the intel_soc_pmic
> driver. Defer probing for later in case we fail to get these devices.
>
> v2: Re
On Sat, Jul 16, 2016 at 3:12 AM, Stephen J wrote:
> On Fri, Jul 15, 2016 at 3:08 AM, Shobhit Kumar wrote:
>>
>> On Fri, Jul 15, 2016 at 2:33 PM, Shobhit Kumar
>> wrote:
>> > On devices that have MIPI DSI panel control and PWM control comming from
>>
On Mon, Jun 13, 2016 at 7:52 PM, Daniel Vetter wrote:
> On Fri, Jun 10, 2016 at 03:14:36PM +0530, Agrawal, Akshu wrote:
>> On 6/8/2016 2:10 PM, Daniel Vetter wrote:
>> > On Wed, Jun 08, 2016 at 01:57:44PM +0530, Akshu Agrawal wrote:
>> > > CHV pipe C hits underrun when we get -ve X values of curso
From: Shobhit Kumar
CHV pipe C hits underrun when we get negative crtc_x values of cursor.
To avoid this we clip and shift the cursor image by negative crtc_x
value.
v2: Make a copy of cursor plane state and allocate new gem object and fb
for clipped cursor and use that in case of negative
Daniel,
On 06/28/2016 05:57 PM, Shobhit Kumar wrote:
From: Shobhit Kumar
CHV pipe C hits underrun when we get negative crtc_x values of cursor.
To avoid this we clip and shift the cursor image by negative crtc_x
value.
v2: Make a copy of cursor plane state and allocate new gem object and fb
From: Shobhit Kumar
CHV pipe C hits underrun when we get negative crtc_x values of cursor.
To avoid this we clip and shift the cursor image by negative crtc_x
value.
v2: Make a copy of cursor plane state and allocate new gem object and fb
for clipped cursor and use that in case of negative
On 06/29/2016 06:24 PM, Shobhit Kumar wrote:
From: Shobhit Kumar
CHV pipe C hits underrun when we get negative crtc_x values of cursor.
To avoid this we clip and shift the cursor image by negative crtc_x
value.
v2: Make a copy of cursor plane state and allocate new gem object and fb
for
During resume, while turning the EDP panel power on, we need not wait
blindly for panel_power_cycle_delay. Check if panel power down sequence
in progress and then only wait. This improves our resume time significantly.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dp.c | 17
On Wed, Dec 9, 2015 at 7:27 PM, Ville Syrjälä
wrote:
> On Wed, Dec 09, 2015 at 06:51:48PM +0530, Shobhit Kumar wrote:
>> During resume, while turning the EDP panel power on, we need not wait
>> blindly for panel_power_cycle_delay. Check if panel power down sequence
>> in p
On Wed, Dec 9, 2015 at 8:34 PM, Chris Wilson wrote:
> On Wed, Dec 09, 2015 at 08:07:10PM +0530, Shobhit Kumar wrote:
>> On Wed, Dec 9, 2015 at 7:27 PM, Ville Syrjälä
>> wrote:
>> > On Wed, Dec 09, 2015 at 06:51:48PM +0530, Shobhit Kumar wrote:
>> >> During
d-off-by: Boris Brezillon
Reviewed-by: Jani Nikula
Cc: Shobhit, any additional comments?
Looks good to me.
Reviewed-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_panel.c | 39 +-
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/dr
expected
- Only do slk_init_cdclk if validation failed else reuse BIOS
programmed value
Cc: Imre Deak
Cc: Ville Syrjälä
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_ddi.c | 18 -
drivers/gpu/drm/i915/intel_display.c | 39
what it is expected
- Only do slk_init_cdclk if validation failed else reuse BIOS
programmed value
v3: Move the validation logic in a separate sanitize function (Ville)
Cc: Imre Deak
Cc: Ville Syrjälä
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_ddi.c | 12
Cc: Ville Syrjälä
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 31 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
directly from CDCLK_CTL (no pre-os display). That is not part of this patch.
Shobhit Kumar (1):
drm/i915/skl: While sanitizing cdclock check the SWF18 as well
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 8
2 files changed, 11 insertions
with other DPLL and CDCLK verification.
Cc: Ville Syrjälä
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
SWF18 is set and then follow through with other DPLL
and CDCLK verification. If not set then for sure we need to sanitize the
cdclock.
v2: Update the commit message for clarity (Siva)
Cc: Ville Syrjälä
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm
. Remaining are reserved (Siva)
Cc: Ville Syrjälä
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
. Remaining are reserved (Siva)
v4: Use ILK_SWF macro for SWF register definitions. Taken from Ville's patch
http://lists.freedesktop.org/archives/intel-gfx/2015-November/079480.html
Cc: Ville Syrjälä
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
driver
pwm_info helps in encapsulating the PWM period_ns values and will form
basis of adding new pwm devices which can then be genrically used by
initializing proper pwm_info structure in the backlight setup call.
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Signed-off-by: Shobhit Kumar
est the patches and see if they work at all for you. For testing Please
enable -
CONFIG_PWM_LPSS=y
CONFIG_PWM_LPSS_PLATFORM=y
Regards
Shobhit
Shobhit Kumar (3):
drm/i915: Encapsulate the pwm_device in a pwm_info structure
pwm: lpss: Add intel-gfx as consumer device in lookup table
drm/i915:
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Signed-off-by: Shobhit Kumar
---
drivers/pwm/pwm-lpss-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c
index 54433fc..910bc14 100644
--- a/drivers/pwm
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_panel.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 9e24c59
patches from Matt, or can be re-used if deemed necessary.
Especially "drm/i915/skl+: Use fb size for relative data rate calculation"
this already addresses some of Ville's comment on similar patch from Matt.
Regards
Shobhit
Kumar, Mahesh (6):
drm/i915/skl+: Use proper bytes_per_
From: "Kumar, Mahesh"
Use FB size for relative data rate calculation. don't always use
pipe source width & height.
adjust height & width according to rotation.
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 42 -
1 file changed, 33 in
From: "Kumar, Mahesh"
don't always use 8 ddb as minimum, instead calculate using proper
algorithm.
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 57 +++--
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i91
2: Update the commit message to explain the WA (shobhit)
Signed-off-by: Shobhit Kumar
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/intel_pm.c | 86 +
2 files changed, 95 insertions(+)
diff --git a/drivers
From: "Kumar, Mahesh"
Don't always use bytes_per_pixel using y_plane=0, instead use it
according to pixel format. If NV12 use y_plane eqal to 1
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
This is needed for WM computation workaround for arbitrated display
bandwidth.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_dma.c | 19 +++
drivers/gpu/drm/i915/i915_drv.h | 6 ++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c
From: "Kumar, Mahesh"
Don't use pipe pixel rate for plane pixel rate.
Calculate plane pixel according to formula
adjusted plane_pixel_rate = adjusted pipe_pixel_rate * downscale ammount
downscale amount = max[1, src_h/dst_h] * max[1, src_w/dst_w]
if 90/270 rotation use rotated width & height
S
From: "Kumar, Mahesh"
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ffcc56a..dc08494 100644
--- a/drivers/gpu/drm/i915/inte
enable) and PWM both are
exported by same intel_soc_pmic driver, just retrying for the driver to
load in intel_dsi_init is sufficient. By the time we come to
setup_backlight, pwm would have been exported as well.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 6 +-
1 file
On Fri, Jan 15, 2016 at 10:32 AM, Kumar, Shobhit <
shobhit.ku...@linux.intel.com> wrote:
> On 01/15/2016 07:18 AM, Matt Roper wrote:
>
>> On Thu, Jan 14, 2016 at 05:32:41PM +0530, Shobhit Kumar wrote:
>>
>>> Hi,
>>> This series add a set of upda
2: Update the commit message to explain the WA (shobhit)
v3: - Address Damien's comment, use DIV_ROUND_UP_ULL macro
- Check both mem_speed and mem_channel to be valid before applying
WA(shobhit)
Signed-off-by: Shobhit Kumar
Signed-off-by: Kumar, Mahesh
Signed-off-by: Shobhit Kumar
From: "Kumar, Mahesh"
Don't use pipe pixel rate for plane pixel rate. Calculate plane pixel according
to formula
adjusted plane_pixel_rate = adjusted pipe_pixel_rate * downscale ammount
downscale amount = max[1, src_h/dst_h] * max[1, src_w/dst_w]
if 90/270 rotation use rotated width & height
v
From: "Kumar, Mahesh"
don't always use 8 ddb as minimum, instead calculate using proper
algorithm.
v2: optimizations as per Matt's comments.
Cc: matthew.d.ro...@intel.com
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 50 ++---
1 file ch
From: "Kumar, Mahesh"
if downscaling is enabled plane data rate increases according to scaling
amount. take scaling amount under consideration while calculating plane
data rate
v2: Address Matt's comments, where data rate was overridden because of
missing else.
Cc: matthew.d.ro...@intel.com
Sig
From: "Kumar, Mahesh"
Use plane size for relative data rate calculation. don't always use
pipe source width & height.
adjust height & width according to rotation.
use plane size for watermark calculations also.
v2: Address Matt's comments.
Use intel_plane_state->visible to avoid divide-by-ze
l.com
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_dma.c | 47 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
2 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d70d96f..32
/show_bug.cgi?id=96571
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90075
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Tested-by: Lluís Batlle i Rossell
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_drv.h | 8 ++-
drivers/gpu/drm/i915/intel_panel.c | 47
again tested
with
latest drm-tip.
Module ordering problem remains still and for testing we should for now enable
LPSS_PWM as in built with i915 as module.
Regards
Shobhit
Shobhit Kumar (3):
drm/i915: Encapsulate the pwm_device in a pwm_info structure
pwm: lpss: Add intel-gfx as consumer device
v2: Add bugzilla links
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96571
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90075
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Tested-by: Lluís Batlle i Rossell
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915
...@linux.intel.com
Tested-by: Lluís Batlle i Rossell
Signed-off-by: Shobhit Kumar
---
drivers/pwm/pwm-lpss-platform.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c
index 5d6ed15..f157a6d 100644
--- a/drivers/pwm/pwm-lpss
/enable-back PSR
drm/intel: add enable_psr module option and disable psr by default
drm/i915: Adding global I915_PARAM for PSR ENABLED.
drm/i915: Add functions to force psr exit
drm/i915: Hook PSR functionality
Shobhit Kumar (2):
drm: Added SDP and VSC structures for handling PSR f
and memcpy
v3: More strict check while parsing VBT
- Ensure that at anytime we do not go beyond sequence block
while parsing
- On unknown element fail the whole parsing
v4: Style changes and spell check mostly as suggested by Jani
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani
panel driver
are done.
Regards
Shobhit
Shobhit Kumar (4):
drm/i915: Correct MIPI operation mode as per expected values from VBT
drm/i915: MIPI init count programming as generic parameter
drm/i915: MIPI PPS delays added
drm/i915: Add support for Generic MIPI panel driver
drivers/gpu/drm/i915
review comments by Jani
- Move all of the things in driver c file from header
- Make all functions static
- Make use of video/mipi_display.c instead of redefining
- Null checks during sequence execution
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/Makefile
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 3 +++
drivers/gpu/drm/i915/intel_dsi.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 2795782..09b9318 100644
--- a/drivers/gpu/drm/i915
In VBT fields operation mode is 0 for Video mode and 1 for command mode.
This field will be directly used as is in generic panel driver. So
adjust accordingly.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_dsi.c | 4 ++--
drivers/gpu/drm
Added as generic parameters which will be initialized in the panel
driver and are specific to panels.
Backlight delays have also kept as placeholders and will be used used
once we have MIPI backlight enabling support
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 5
This cleans up the checkpatch errors for the merged commit -
commit d3b542fcfc72d7724585e3fd2c5e75351bc3df47
Author: Shobhit Kumar
Date: Mon Apr 14 11:00:34 2014 +0530
drm/i915: Add parsing support for new MIPI blocks in VBT
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915
/i915: Extract vlv_prepare_pll
gmch pll moved out of crtc mode_set callbacks into ->enable hooks
Reviewer: Shobhit Kumar
I will be on vacation till next weekend, so will get to these after
that. Keep on my name if that is okay.
Regards
Shob
Thanks Damien for your review
On Thursday 15 May 2014 10:18 PM, Damien Lespiau wrote:
On Mon, Apr 14, 2014 at 11:18:27AM +0530, Shobhit Kumar wrote:
>This driver makes use of the generic panel information from the VBT.
>Panel information is classified into two - panel configuration and
On Monday 19 May 2014 07:53 PM, Damien Lespiau wrote:
On Mon, Apr 14, 2014 at 11:18:27AM +0530, Shobhit Kumar wrote:
+#define NS_MHZ_RATIO 100
[...]
+static bool generic_init(struct intel_dsi_device *dsi)
+{
[...]
+ /*
+* ui(s) = 1/f [f in hz]
+* ui(ns) = 10^9
max of lp_to_hs switch and hs_to_lp switch while computing
hs_lp_switch_count
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 5 +
drivers/gpu/drm/i915/intel_dsi.h | 2 +
drivers/gpu/dr
we can figure out what is the LFP type and initialize MIPI only if MIPI
is found.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_bios.c| 20 +++-
drivers/gpu/drm/i915/intel_display.c | 4 +++-
3 files changed, 24
parse_mipi and intel_dsi_init insted of outside
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_bios.c | 14 ++
drivers/gpu/drm/i915/intel_bios.h | 4
drivers/gpu/drm/i915/intel_dsi.c | 4
4 files changed, 24 insertions
Fix warnings introduced by the following commit -
commit 9c92da2c7c17eea79b6321b37592df0a002d24df
Author: Shobhit Kumar
Date: Fri May 23 21:35:27 2014 +0530
drm/i915: Add support for Generic MIPI panel driver
Fixed all except the DRM logging which go beyond line 80
Signed-off-by
parse_mipi and intel_dsi_init insted of outside
v3: Make has_mipi as a bitfield as suggested
Signed-off-by: Shobhit Kumar
Reviewed-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_bios.c | 14 ++
drivers/gpu/drm/i915/intel_bios.h | 4
detection works across platforms
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_bios.h | 10 +-
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
2 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/drm/i915/intel_bios.h
MIPI Block #52 which provides configuration details for the MIPI panel
including dphy settings as per panel and tcon specs
Block #53 gives information on panel enable sequences
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_bios.c | 5 +-
drivers/gpu/drm/i915/intel_bios.h | 152
-encoder driver in the existing design
to support
MIPI. Followup patches for this driver will come next.
Regards
Shobhit
Shobhit Kumar (2):
drm/i915: Update VBT data structures to have MIPI block enhancements
drm/i915: Add parsing support for new MIPI blocks in VBT
drivers/gpu/drm/i915
The parser extracts the config block(#52) and sequence(#53) data
and store in private data structures.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_bios.c | 175 --
drivers/gpu/drm/i915/intel_bios.h
Hi
On Thursday 13 February 2014 12:47 PM, Jani Nikula wrote:
On Thu, 13 Feb 2014, Shobhit Kumar wrote:
MIPI Block #52 which provides configuration details for the MIPI panel
including dphy settings as per panel and tcon specs
Block #53 gives information on panel enable sequences
Signed-off
and memcpy
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_bios.c | 162 --
drivers/gpu/drm/i915/intel_bios.h | 34
3 files changed, 197 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
structure improvements for cleaner code
- Adding units for the pps delays, all in ms
- change data structure to be more cleaner and simple
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_bios.c | 4 +-
drivers/gpu/drm/i915/intel_bios.h | 174
error detection during parsing MIPI sequence block
Regards
Shobhit
Shobhit Kumar (2):
drm/i915: Update VBT data structures to have MIPI block enhancements
drm/i915: Add parsing support for new MIPI blocks in VBT
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_bios.c | 164
On Thursday 27 February 2014 08:18 PM, Jani Nikula wrote:
On Thu, 20 Feb 2014, Shobhit Kumar wrote:
+/* Block 52 contains MIPI configuration block
+ * 6 * bdb_mipi_config, followed by 6 pps data
+ * block below
+ *
+ * all delays in ms
The spec you sent me has "... delay in 100us unit
structure improvements for cleaner code
- Adding units for the pps delays, all in ms
- change data structure to be more cleaner and simple
v3: Corrected the unit for pps delays as 100us
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_bios.c | 4
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3365664..7ceb8c6 100644
--- a/drivers/gpu/drm
Some MIPI panels might not have resolution which is a multiple of 64 like
1366x768. Enable this feature for such panels by default
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index dfcdb10..d8eccda 100644
--- a/drivers/gpu/drm/i915
Shobhit Kumar (7):
drm/i915: Program Rcomp and band gap reset everytime we resume from power gate
drm/i915: Enable MIPI port before the plane and pipe enable
drm/i915: Disable DPOunit clock gating
drm/i915: Parameterize the Clockstop and escape_clk_div
drm/i915: Panel commands can be sent
In preparation for Generic driver
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 11 +--
drivers/gpu/drm/i915/intel_dsi.h | 4 +++-
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers
As per the hw team's recommendation we need to enable the MIPI port
before enabling the plane and pipe. So call MIPI port enable in
pre_enable phase itself
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c
Otherwise, this can stall pipe. We also need DPLL REFA always
enabled
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b
Though HS mode also should work.
v2: Change parameter as "bool hs" as suggested by Jani
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 5 +++--
drivers/gpu/drm/i915/intel_dsi_cmd.c | 4 ++--
drivers/gpu/drm/i915/intel_dsi_cmd.h |
On Friday 15 November 2013 02:25 PM, Daniel Vetter wrote:
On Fri, Nov 15, 2013 at 10:27:25AM +0200, Jani Nikula wrote:
On Sat, 09 Nov 2013, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also
On Wednesday 20 November 2013 07:09 AM, Shobhit Kumar wrote:
On Friday 15 November 2013 02:25 PM, Daniel Vetter wrote:
On Fri, Nov 15, 2013 at 10:27:25AM +0200, Jani Nikula wrote:
On Sat, 09 Nov 2013, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
On Friday 15 November 2013 01:57 PM, Jani Nikula wrote:
On Sat, 09 Nov 2013, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable phase. The ULPS entry/exit
nel_power hook to dsi_post_disable
- Replace hardcoding with AFE_LATCHOUT
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 110 +++
drivers/gpu/drm/i915/intel_dsi.h | 2 +
2 files changed, 79 insertions
-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 89 +---
1 file changed, 31 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 44279b2..0d1b17f 100
implemntation based on VBT design enhancments to support multiple panels
v2: Mask away the port_bits before use
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 29 ++---
drivers/gpu/drm/i915/intel_dsi.h | 14 ++
2
v2: Rebased on latest code
Signed-off-by: Shobhit Kumar
Signed-off-by: Yogesh Mohan Marimuthu
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 47
with more details
- Move the new parameters out of this patch
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 9 -
drivers/gpu/drm/i915/intel_dsi.h | 5 +
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/driver
that we need not do
read/modify/write and
can just write the value
- Moved the sub-encoder hook in dsi_pre_enable and dsi_post_enable
- Minor coding tidbits are fixed
Regards
Shobhit
Shobhit Kumar (7):
drm/i915: Add more dev ops for MIPI sub encoder
drm/i915: Use FLISDSI interfac
DSI PLL will get configured during crtc_enable using ->pre_pll_enable
and no need to do in ->mode_set
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drive
-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 0d1b17f..ba79ec1 100644
--- a/drivers/gpu/drm/i915
On Wednesday 11 December 2013 04:32 PM, Jani Nikula wrote:
On Tue, 10 Dec 2013, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable phase. The ULPS entry/exit
nel_power hook to dsi_post_disable
- Replace hardcoding with AFE_LATCHOUT
v4: Make intel_dsi_device_ready and intel_dsi_clear_device_ready static
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/
On Wednesday 11 December 2013 06:36 PM, Daniel Vetter wrote:
On Wed, Dec 11, 2013 at 05:52:05PM +0530, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable phase
a panel sub-encoder driver is added. Proper detection or VBT is still
pending.
Regards
Shobhit
Shobhit Kumar (4):
drm/i915: Add more dev ops for MIPI sub encoder
drm/i915: Use FLISDSI interface for band gap reset
drm/i915: Compute dsi_clk from pixel clock
drm/i915: Parameterize the MIPI
Also add new fields in intel_dsi to have all dphy related parameters.
These will be useful even when we go for pure generic MIPI design
Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c |9 -
drivers/gpu/drm/i915/intel_dsi.h | 29
Signed-off-by: Shobhit Kumar
Signed-off-by: Yogesh Mohan Marimuthu
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dsi.c | 47 ++---
drivers/gpu/drm/i915/intel_sideband.c | 14
Has been tested on couple of panels now.
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Vijaykumar Balakrishnan
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 11 ++
drivers/gpu/drm/i915/intel_dsi.c | 334 +-
2 files changed
Minor modification to m_n_p calculations as well
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 75 --
1 file changed, 63 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915
On 10/21/2013 6:53 PM, Ville Syrjälä wrote:
On Mon, Oct 21, 2013 at 05:51:07PM +0530, Shobhit Kumar wrote:
Has been tested on couple of panels now.
While it's nice to get patches, I can't say I'm very happy about the
shape of this one.
The patch contains several changes i
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