From: Oscar Mateo
Gen11 has up to 4 VCS and up to 2 VECS engines, this patch adds mmio
base definitions for all of them.
Bspec: 20944
Bspec: 7021
v2: Set the correct mmio_base in intel_engines_init_mmio; updating the
base mmio values any later would cause incorrect reads in
i915_gem_sanitize (M
ile (Paulo).
v5: Remove comments (Lucas).
v6: Multile rebases (Paulo).
Reviewed-by: Anuj Phogat (v1)
Signed-off-by: Paulo Zanoni
Signed-off-by: Oscar Mateo
Signed-off-by: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h
From: Michel Thierry
v2: rebased to intel_lr_indirect_ctx_offset
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_lrc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/
From: "Ceraolo Spurio, Daniele"
Starting from Gen11 the context descriptor format has been updated in
the HW. The hw_id field has been considerably reduced in size and engine
class and instance fields have been added.
There is a slight name clashing issue because the field that we call
hw_id is
From: Tvrtko Ursulin
The current size may be bigger than the correct one, this needs to be
revisited later.
v2: Rebase.
Acked-by: Ben Widawsky
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
1 file changed, 2 insertions(+)
diff -
From: Thomas Daniel
Supports two-element submission using the new enhanced execlist mechanism
v2: Rebase.
v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio).
v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio)
Signed-off-by: Thomas Daniel
Signed-off-by: Rodrigo Viv
.
v9: fix rebase issue, change check in fw_domains_init from IS_GEN11
to GEN >= 11
Cc: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Paulo Zanoni
Acked-by: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h |
): fix indentation.
v3 (from Paulo): rebase.
Signed-off-by: kgardine
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_lrc.c | 10 --
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
/i915: Simplify intel_engines_init")
v6: Fix v5. Remove info->num_rings. (by Oscar)
v7: Rebase (Rodrigo).
Cc: Paulo Zanoni
Cc: Vinay Belgaumkar
Cc: Tvrtko Ursulin
Cc: Michal Wajdeczko
Signed-off-by: Oscar Mateo
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c |
From: Kelvin Gardiner
ICL 11 has a greater number of maximum subslices. This patch updates the
subslice max define to reflect this.
Bspec: 21139
Reviewed-by: Oscar Mateo
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Kelvin Gardiner
---
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
1
From: Oscar Mateo
Using the new hierarchical interrupt infrastructure.
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Cc: Paulo Zanoni
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_irq.c | 68 +---
drivers/gpu/drm/i915
From: Tomasz Lis
In Icelake, there are more engines on which Memory Object Control States need
to be configured. Besides adding Icelake under Skylake config, the patch makes
sure MOCS register addresses for the new engines are properly defined.
Additional patch might be need later, in case the s
This enables the Mesa driver to advertise support for ARB_timer_query,
and thus an OpenGL version higher than 3.2.
Based on the CNL patch by Nanley Chery.
v2: Rebase.
Cc: Anuj Phogat
Cc: Nanley Chery
Cc: Rodrigo Vivi
Requested-by: Anuj Phogat
Tested-by: Anuj Phogat
Signed-off-by: Paulo
(Daniele).
v4: Do not call intel_uncore_forcewake_reset after reset, we may be
using the forcewake to read protected registers elsewhere and those
results may be clobbered by the concurrent dropping of forcewake.
bspec: 19212
Cc: Oscar Mateo
Cc: Antonio Argenziano
Cc: Paulo Zanoni
Cc: Daniele
From: Kelvin Gardiner
This patch adds support to detect ICL, slice, subslice and EU fuse
settings.
Add addresses for ICL 11 slice, subslice and EU fuses registers.
These register addresses are the same as previous platforms but the
format and / or the meaning of the information is different. The
From: Oscar Mateo
AFAICT, once the new interrupt is in place, the rest should behave the
same as Gen10.
v2: Update ring frequencies (Sagar)
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Cc: Paulo Zanoni
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_debugfs.c | 10
From: Oscar Mateo
Both for clarity and so that we can reuse it later on.
v2:
- local_clock returns a u64 (Tvrtko)
- Use the funky BIT(bit) version (Tvrtko)
- wait_start not required (Tvrtko)
- Use time_after64 (Oscar)
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Oscar
The only thing that differs here is that the crystal clock freq now
has four possible values.
This patch gets rid of the "Unknown gen, unable to compute..." message
at boot for gen11.
Reviewed-by: Lionel Landwerlin
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h
From: Oscar Mateo
The new context descriptor format in Gen11 contains two assignable fields: the
SW Context ID (technically 11 bits, but practically limited to 2032 entries due
to some being reserved for future use by the GuC) and the SW Counter (6 bits).
We don't want to limit ourselves too muc
From: Oscar Mateo
Icelake 11 has one vebox and two vdboxes (0 and 2).
Bspec: 21140
v2: Split out in two (Daniele)
Cc: Daniele Ceraolo Spurio
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/d
Em Ter, 2018-01-09 às 17:07 -0800, Oscar Mateo escreveu:
>
> On 01/09/2018 05:02 PM, De Marchi, Lucas wrote:
> > On Tue, 2018-01-09 at 16:09 -0800, Oscar Mateo wrote:
> > > On 01/09/2018 03:23 PM, Paulo Zanoni wrote:
> > > > This is the current
Em Ter, 2018-01-09 às 15:59 -0800, Oscar Mateo escreveu:
>
> On 01/09/2018 03:23 PM, Paulo Zanoni wrote:
> > From: Rodrigo Vivi
> >
> > Icelake is a Intel® Processor containing Intel® HD Graphics.
> >
> > This is just an initial Icelake definition. PCI
Em Qua, 2018-01-10 às 10:15 +, Chris Wilson escreveu:
> Quoting Paulo Zanoni (2018-01-09 23:23:10)
> > From: Rodrigo Vivi
> >
> > Icelake is a Intel® Processor containing Intel® HD Graphics.
>
> One thing to check, is the marketing term now UHD Graphics?
Market
Em Qua, 2018-01-10 às 10:22 -0800, Rodrigo Vivi escreveu:
> On Wed, Jan 10, 2018 at 06:08:21PM +, Oscar Mateo wrote:
> >
> >
> > On 01/10/2018 09:57 AM, Paulo Zanoni wrote:
> > > Em Ter, 2018-01-09 às 15:59 -0800, Oscar Mateo escreveu:
> > > >
Em Qua, 2018-01-10 às 11:39 +0200, Joonas Lahtinen escreveu:
> On Tue, 2018-01-09 at 21:23 -0200, Paulo Zanoni wrote:
> > For now it does nothing, except for avoiding a MISSING_CASE.
> >
> > v2: Rebase.
> >
> > Signed-off-by: Paulo Zanoni
>
>
>
>
Em Qua, 2018-01-10 às 09:02 +, Tvrtko Ursulin escreveu:
> On 09/01/2018 23:23, Paulo Zanoni wrote:
> > From: Tvrtko Ursulin
> >
> > v2: Update for POR changes. (Daniele Ceraolo Spurio)
> >
> > Signed-off-by: Tvrtko Ursulin
> > Signed-off-by: Rodrig
Em Qua, 2018-01-10 às 12:16 +0200, Joonas Lahtinen escreveu:
> On Tue, 2018-01-09 at 21:23 -0200, Paulo Zanoni wrote:
> > From: Tvrtko Ursulin
> >
> > v2: Rebase.
> >
> > v3:
> > * Remove DPF, it has been removed from SKL+.
> > * Fix -inte
(Kelvin Gardiner).
v4 (from Paulo): Add missing __initconst (Paulo) and say "graphics
controller" instead of something that looks like an official marketing
name but isn't (Chris).
Reviewed-by: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
Signed-off-b
Em Ter, 2018-01-09 às 21:23 -0200, Paulo Zanoni escreveu:
> From: Tvrtko Ursulin
>
> MMIO addresses and register definition for the new interrupt
> registers in Gen11.
>
> v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter)
> v3: Adjust VCS and VECS. (D
Em Sex, 2017-12-22 às 15:18 -0800, Rodrigo Vivi escreveu:
> On CNP Pin 3 is for misc of Port F usage depending on the
> configuration. For CNL that uses Port F, pin 3 is the one.
>
> v2: Make it more generic and update commit message.
Reviewed-by: Paulo Zanoni
>
> Cc: Anu
intel_vbt_defs.h
> @@ -299,6 +299,8 @@ struct bdb_general_features {
> #define DVO_PORT_DPA 10
> #define DVO_PORT_DPE 11
> /* 193 */
> #define DVO_PORT_HDMIE 12
> /* 193 */
> +
(Kelvin Gardiner).
v4 (from Paulo): Add missing __initconst (Paulo) and say "graphics
controller" instead of something that looks like an official marketing
name but isn't (Chris).
Reviewed-by: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
Signed-off-b
Hi
This series adds the initial support for ICP. No conflicts with the other
series. Patches 1 and 2 are parts of other series that we've already been
discussing on this mailing list, but I put them here so CI can do the right
thing.
I have just re-reviewed all of Anusha's patches and my reviewed
From: Anusha Srivatsa
Add the enum additions to ICP PCH.
v2 (from Paulo): don't set any platforms to it yet since ICP support is
incomplete.
v3 (from Rodrigo): Fix ICP name.
Reviewed-by: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm
From: Anusha Srivatsa
Add the PCI ID for the ICL PCH - ICP.
v2: rebased.
v3: rebased.
v4: fix ICP name.
v5: fix the ID mask (Fei Li).
v6 (from Paulo): bikesheds.
Cc: Li, Fei
Reviewed-by: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915
nd by Ander.
v3: Adding missing cases from intel_bios.c for Port_F
v4: Adding other missing cases and fix the commit message.
v5: Rebase on top of display headers rework.
v6 (from Paulo): improve commit message, bikeshed bit definitions.
Cc: Lucas De Marchi
Cc: Manasi Navare
Reviewed-by: Paulo Z
, GMBUS_PIN_NUM (Paulo)
v7 (from Paulo):
- Make it apply.
v8 (from Paulo):
- Maintain consistent if ladder ordering.
Suggested by: Ville Syrjala
Cc: Jani Nikula
Reviewed-by: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 7
Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_panel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index fa6831f8c004..ad80cca8c110 100644
--- a
From: Anusha Srivatsa
Add register definitions for setting the rawclock.
Set the numerator,denominator and divider values.
v2: Simplify the commit message. Simplify the math.
Add register bits for numerator. (Paulo)
v3 (from Paulo): coding style bikesheds.
Reviewed-by: Paulo Zanoni
Signed
CFL uses
CNP and per platform check makes sense in that case.
v6 (from Paulo):
- v5 was a patch on top of v4, not a new version. Now v6 is correctly
a new version of the original patch.
Cc: Ville Syrjala
Reviewed-by: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zan
Em Qui, 2018-01-11 às 15:57 -0800, Rodrigo Vivi escreveu:
> On Thu, Jan 11, 2018 at 09:48:57PM +, James Ausmus wrote:
> > On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote:
> > > From: Anusha Srivatsa
> > >
> > > ICP has two backlight control
Em Sex, 2018-01-19 às 17:30 +, Tvrtko Ursulin escreveu:
> On 10/01/2018 10:16, Joonas Lahtinen wrote:
> > On Tue, 2018-01-09 at 21:23 -0200, Paulo Zanoni wrote:
> > > From: Tvrtko Ursulin
> > >
> > > v2: Rebase.
> > >
> > > v
Em Sex, 2018-01-19 às 09:56 -0800, Rodrigo Vivi escreveu:
> On Fri, Jan 19, 2018 at 05:26:02PM +, Anusha Srivatsa wrote:
> > On Fri, Jan 19, 2018 at 02:40:41PM -0200, Paulo Zanoni wrote:
> > > Em Qui, 2018-01-11 às 15:57 -0800, Rodrigo Vivi escreveu:
> > > > On T
(from Paulo): Rebase.
v4 (from Paulo): adjust commit message (James) and comment (Rodrigo).
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: James Ausmus
Cc: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_panel.c | 8
Em Qui, 2018-01-11 às 16:00 -0200, Paulo Zanoni escreveu:
> Hi
>
> This series adds the initial support for ICP. No conflicts with the
> other
> series. Patches 1 and 2 are parts of other series that we've already
> been
> discussing on this mailing list, but I put
initialize MBus during display init
drm/i915/icl: program mbus during pipe enable
drm/i915/icl: track dbuf slice-2 status
drm/i915/icl: Enable 2nd DBuf slice only when needed
drm/i915/icl: update ddb entry start/end mask during hw ddb readout
drm/i915/icl: enable SAGV for ICL platform
Paulo
This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.
v2:
- Implement the voltage levels.
- Rebase.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h| 10 +-
drivers/gpu/drm/i915/intel_cdclk.c
ed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b92ea1dbd40..11aac65d1543 100644
--- a/driver
ower wells and the mbus code, so leave those
pieces with a FIXME comment while they're not here yet.
v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 16 ++-
drivers/gpu/dr
move extra parentheses
- Use FP16.16 only when absolutely necessary (Paulo)
Changes Since V3:
- Rebase
Changes since v4 (from Paulo)
- Coding style issue.
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel
e it compile.
- Fix a few coding style issues.
v3
- Rebase on top of upstream patches
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 27 ---
2 files changed, 21 insertions(+), 7 delet
port A. This way, we'll be able to easily reuse
the function on ICL when we add icl_display_core_init().
v2: Don't use _PICK() when you can use a ternary operator.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 26 ++
drivers/gp
mment.
- Reorganize where things are defined.
- Fix indentation.
- Remove unnecessary POSTING_READ() calls.
- Improve the commit message.
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_runtime_pm.c
From: Mahesh Kumar
This patch initializes MBus during display initialization.
Changes since V2 (from Paulo):
- Don't forget to remove the WARN_ON(1) call.
Changes since V1:
- Rebase to use function like Macros
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off-by:
From: Mahesh Kumar
This patch program default values of MBus credit during pipe enable.
Changes since V2:
- We don't need to do anything when disabling the pipe
Changes Since V1:
- Add WARN_ON (Paulo)
- Remove TODO comment
- Program 0 during pipe disable
- Rebase
Reviewed-by: Paulo Z
It's 10us for gen 11.
Reviewed-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84a5b13fdee2..1edd1445ab5b 1
From: Mahesh Kumar
This patch adds support to start tracking status of DBUF slices.
This is foundation to introduce support for enabling/disabling second
DBUF slice dynamically for ICL.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_d
From: Mahesh Kumar
Enable SAGV for ICL platform.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1edd1445ab5b..dedc76781524 100644
--- a/d
From: Mahesh Kumar
Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
11 bits. This patch make changes to use proper mask for ICL+ during
hardware ddb value readout.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++
1 file changed, 14
: Change new definition name, drop comment (Rodrigo)
Cc: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
Signed-off-by: James Ausmus
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 5 -
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers
From: Mahesh Kumar
ICL has two slices of DBuf, each slice of size 1024 blocks.
We should not always enable slice-2. It should be enabled only if
display total required BW is > 12GBps OR more than 1 pipes are enabled.
Changes since V1:
- typecast total_data_rate to u64 before multiplication to s
From: Mahesh Kumar
This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL
Changes Since V1:
- Use function like macros (Paulo)
- fix copy-paste error (Paulo)
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off
removed in ICL.
This patch removes the PLANE_NV12_BUF_CFG write for ICL.
Changes Since V1:
- Improve commit message as per Paulo's comment
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 6 --
1 file change
ince it doesn't matter here (Paulo)
> Also move IS_CNL_WITH_PORT_F macro to this patch to
> make it easier for review this part and also to get
> used sooner.
>
Reviewed-by: Paulo Zanoni
(although I still would have preferred the split)
> Cc: Dhinakaran Pandiyan
>
Em Ter, 2018-01-23 às 16:32 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote:
> > On ICL we have two sets of registers: one for port A and another
> > for
> > port B. The set of port A registers is the same as the CNL
> > re
Em Ter, 2018-01-23 às 16:49 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> > From: Mahesh Kumar
> >
> > ICL has 2 slices of DBuf, enable both the slices during display
> > init.
> >
> > Ideally we should o
Em Sex, 2018-01-26 às 18:50 -0200, Paulo Zanoni escreveu:
> Em Ter, 2018-01-23 às 16:49 -0800, James Ausmus escreveu:
> > On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> > > From: Mahesh Kumar
> > >
> > > ICL has 2 slices of DBuf, enable both
Em Sex, 2018-01-26 às 15:50 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:26PM -0200, Paulo Zanoni wrote:
> > From: Mahesh Kumar
> >
> > ICL require DDB allocation of plane to be more than "minimum
> > display
> > buffer needed"
Em Ter, 2018-01-23 às 17:05 -0200, Paulo Zanoni escreveu:
> From: Mahesh Kumar
>
> Enable SAGV for ICL platform.
The requirements for enabling SAGV on ICL are different. We need to
implement them. While we don't have them, perhaps the best option is to
add ICL to intel_has_s
e it compile.
- Fix a few coding style issues.
v3:
- Rebase on top of upstream patches
v4 (from Paulo):
- Bikeshed if statements (James).
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_
move extra parentheses
- Use FP16.16 only when absolutely necessary (Paulo)
Changes Since V3:
- Rebase
Changes since v4 (from Paulo):
- Coding style issue.
Changes since v5 (from Paulo):
- Do the final checks according to BSpec.
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off
ed-by: Paulo Zanoni
Reviewed-by: James Ausmus
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b92ea1dbd40..11aac65
drm/i915/icl: NV12 y-plane ddb is not in same plane
drm/i915/icl: Introduce MBus related registers
Paulo Zanoni (2):
drm/i915/gen11: fix the SAGV block time for gen11
drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP
register
drivers/gpu/drm/i915/i915_drv.h | 1 +
d
e it compile.
- Fix a few coding style issues.
v3:
- Rebase on top of upstream patches
v4 (from Paulo):
- Bikeshed if statements (James).
Reviewed-by: Paulo Zanoni
Reviewed-by: James Ausmus
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h
-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_lrc.c | 18 --
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 05c57166eee3..3b457990b73c 100644
--- a/driv
From: Mahesh Kumar
This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL
Changes Since V1:
- Use function like macros (Paulo)
- fix copy-paste error (Paulo)
Reviewed-by: Paulo Zanoni
Reviewed-by: James Ausmus
Signed-off-by
move extra parentheses
- Use FP16.16 only when absolutely necessary (Paulo)
Changes Since V3:
- Rebase
Changes since v4 (from Paulo):
- Coding style issue.
Changes since v5 (from Paulo):
- Do the final checks according to BSpec.
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off
removed in ICL.
This patch removes the PLANE_NV12_BUF_CFG write for ICL.
Changes Since V1:
- Improve commit message as per Paulo's comment
Reviewed-by: Paulo Zanoni
Reviewed-by: James Ausmus
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 6
: Change new definition name, drop comment (Rodrigo)
Cc: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
Signed-off-by: James Ausmus
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 5 -
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers
It's 10us for gen 11.
Reviewed-by: Mahesh Kumar
Reviewed-by: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
Vivi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1c524ed1e1da..164dbb8cfa36 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
Em Seg, 2018-01-29 às 12:51 +0200, Imre Deak escreveu:
> On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote:
> > This commit adds the basic CDCLK functions, but it's still missing
> > pieces of the display initialization sequence.
> >
> > v2:
>
Em Sex, 2018-01-26 às 15:14 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote:
> > This commit adds the basic CDCLK functions, but it's still missing
> > pieces of the display initialization sequence.
> >
> > v2:
>
assing PORT_A (James).
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++---
2 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/
avoid confusion.
- Simplify the DVFS part.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h| 10 +-
drivers/gpu/drm/i915/intel_cdclk.c | 235 -
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 243 insertions(+), 4 deletions(-)
diff --gi
avoid confusion.
- Simplify the DVFS part.
v4:
- Remove wrong bit definition (James).
- Also drive-by fix the coding style for the register definition we
touched.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h| 35 +++---
drivers/gpu/drm/i91
investigate the problem later.
Thanks,
Paulo
Mahesh Kumar (3):
drm/i915/icl: Enable both DBuf slices during init
drm/i915/icl: initialize MBus during display init
drm/i915/icl: program mbus during pipe enable
Paulo Zanoni (3):
drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
dr
assing PORT_A (James).
Reviewed-by: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++---
2 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/d
From: Mahesh Kumar
This patch initializes MBus during display initialization.
Changes since V2 (from Paulo):
- Don't forget to remove the WARN_ON(1) call.
Changes since V1:
- Rebase to use function like Macros
Reviewed-by: Paulo Zanoni
Reviewed-by: James Ausmus
Signed-off-by: Mahesh
From: Mahesh Kumar
This patch program default values of MBus credit during pipe enable.
Changes since V2:
- We don't need to do anything when disabling the pipe
Changes Since V1:
- Add WARN_ON (Paulo)
- Remove TODO comment
- Program 0 during pipe disable
- Rebase
Reviewed-by: Paulo Z
ower wells and the mbus code, so leave those
pieces with a FIXME comment while they're not here yet.
v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits.
v3: Use _MMIO_PORT() (Ville).
Reviewed-by: James Ausmus (v2)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/dr
mment.
- Reorganize where things are defined.
- Fix indentation.
- Remove unnecessary POSTING_READ() calls.
- Improve the commit message.
Reviewed-by: Paulo Zanoni
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm
(from Paulo):
- Remove WARN() that we'll never be able to trigger (Ville).
Cc: Ville Syrjälä
Reviewed-by: Paulo Zanoni
Reviewed-by: James Ausmus
Signed-off-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 17 +
1 file changed, 17
Em Seg, 2018-02-05 às 15:13 -0800, Ausmus, James escreveu:
> On Mon, Feb 05, 2018 at 01:40:42PM -0200, Paulo Zanoni wrote:
> > This commit adds the basic CDCLK functions, but it's still missing
> > pieces of the display initialization sequence.
> >
> > v2:
>
avoid confusion.
- Simplify the DVFS part.
v4:
- Remove wrong bit definition (James).
- Also drive-by fix the coding style for the register definition we
touched.
v5:
- Comment style (checkpatch).
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915
Em Ter, 2018-02-06 às 19:54 +, Patchwork escreveu:
> == Series Details ==
>
> Series: ICL display initialization, selected patches (rev3)
> URL : https://patchwork.freedesktop.org/series/37668/
> State : warning
>
> == Summary ==
>
> Series 37668v3 ICL display initialization, selected patc
Em Ter, 2017-02-28 às 18:57 -0800, Dhinakaran Pandiyan escreveu:
> Implement GLK cdclk restriction for DP audio, similar to what's
> implemented
> for BDW and other GEN9 platforms. The cdclk restriction has been
> refactored out of max. pixel clock computation as the 1:1
> relationship
> between pi
; GLK generates.
>
> Separating min. cdclk and max. pixel_rate would be nicer, but let's
> defer that to future and fix the GLK bug for now.
Looks correct to me.
Reviewed-by: Paulo Zanoni
No cc:stable seems to be required due to GLK still being alpha_support.
>
>
req change
sequences. The funny thing is that the minimum CDCLK for SKL seems to
be 308.57, so that's still bigger than 96*2... Anyway, having this for
completeness would probably be good, just in case I'm missing some
detail that's important here.
I'd like to see the SKL additi
t; > intel.com> wrote:
> > > >
> > > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
> > > > >
> > > > > Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan
> > > > > escreveu:
> > > > > >
>
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