On Sat, May 25, 2019 at 10:43 PM Sam Ravnborg wrote:
>
> Just a quick (final) probe. If there are no further feedback I will
> commit this set sunday.
> Added intel-gfx@lists.freedesktop.org just to get a bit more coverage.
Hi Sam
v2 of this series is already applied to drm-misc-next
Thanks
Patr
On Jul 20, 2016 4:50 PM, "Dmitry V. Levin" wrote:
>
> On Mon, Sep 07, 2015 at 08:23:57PM +0200, Patrik Jakobsson wrote:
> > On Mon, Sep 7, 2015 at 6:51 PM, Dmitry V. Levin wrote:
> > > On Mon, Aug 31, 2015 at 02:37:07PM +0200, Patrik Jakobsson wrote:
> > &
E)
> |
> - memcpy(mode, E, S)
> + drm_mode_copy(mode, E)
> )
>
> @depends on !is_mode_copy@
> struct drm_display_mode mode;
> expression E;
> @@
> (
> - mode = E
> + drm_mode_copy(&mode, &E)
> |
> - memcpy(&mode, E, S)
> + drm_mode_copy(
On Mon, Jan 20, 2020 at 9:23 AM Thomas Zimmermann wrote:
>
> VBLANK callbacks in struct drm_driver are deprecated in favor of
> their equivalents in struct drm_crtc_funcs. Convert gma500 over.
>
> Signed-off-by: Thomas Zimmermann
Looks good. For this patch:
Acked-by: P
Linus Walleij
Both patches look good. Do you want me to take them through drm-misc? Otherwise:
Acked-by: Patrik Jakobsson
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Jan 22, 2021 at 3:51 PM Andy Shevchenko
wrote:
>
> On Fri, Jan 22, 2021 at 03:16:55PM +0100, Patrik Jakobsson wrote:
> > On Fri, Jan 22, 2021 at 12:39 PM Andy Shevchenko
> > wrote:
> > >
> > > Convert the GMA500 driver to use the new SCU IPC API. Th
On Fri, Feb 5, 2021 at 12:07 PM Andy Shevchenko
wrote:
>
> On Thu, Feb 4, 2021 at 11:04 AM Andy Shevchenko
> wrote:
> >> Today's linux-next merge of the drivers-x86 tree got a conflict in:
> >
> > Thanks. I already asked Patrik yesterday day if DRM missed to pull an
> > immutable tag I provided.
ivers, where an atomic commit can
> fail with -EINTR or -ENOMEM and should be restarted.
>
> Changes since v1:
> - Fix compiler warning. (Emil)
> - Fix commit message (Daniel)
>
> Cc: Alex Deucher
> Acked-by: Alex Deucher
> Cc: Christian König
> Cc: David Airlie
&
On Wed, Jun 15, 2016 at 12:11:55AM +, Vivi, Rodrigo wrote:
> On Mon, 2016-05-23 at 10:57 +0200, Patrik Jakobsson wrote:
> > On Wed, May 18, 2016 at 01:24:12PM +0300, Mika Kuoppala wrote:
> > > Patrik Jakobsson writes:
> > >
> > > > [ text/plain ]
>
or
>> > we
>> > release the 1.07 before.
>> 1.06 is already blacklisted, it has known problems.
>
> Oh! So I agree with the first statement. Let's merge this patch ;)
That was new info for me as well. I don't have commit access so anyone
who can, feel free to m
On Thu, Nov 19, 2015 at 04:06:47PM +0200, Imre Deak wrote:
> On to, 2015-11-19 at 14:34 +0100, Patrik Jakobsson wrote:
> > On Wed, Nov 18, 2015 at 06:44:43PM +0200, Imre Deak wrote:
> > > On ke, 2015-11-18 at 17:33 +0100, Daniel Vetter wrote:
> > > > On Wed, Nov 18,
On Wed, Nov 18, 2015 at 07:53:50PM +0200, Imre Deak wrote:
> Now that the known DMC/DC issues are fixed, let's try again and
> re-enable the power well support.
>
> Signed-off-by: Imre Deak
Together with the PC9/10 fix this is:
Reviewed-by: Patrik Jakobsson
> ---
>
On Wed, Nov 25, 2015 at 1:54 PM, Robert Fekete
wrote:
> On ons, 2015-11-18 at 10:17 +0100, Daniel Vetter wrote:
>> On Wed, Nov 04, 2015 at 10:59:28AM +0100, Patrik Jakobsson wrote:
>> > On Wed, Nov 04, 2015 at 10:35:19AM +0100, Robert Fekete wrote:
>> > > The ol
On Tue, Nov 24, 2015 at 6:46 AM, Dmitry V. Levin wrote:
> On Mon, Sep 07, 2015 at 08:23:57PM +0200, Patrik Jakobsson wrote:
>> On Mon, Sep 7, 2015 at 6:51 PM, Dmitry V. Levin wrote:
>> > On Mon, Aug 31, 2015 at 02:37:07PM +0200, Patrik Jakobsson wrote:
>> > [...]
&g
There is no dedicated aux channel for port E on SKL. Instead the VBT
describes which of the other aux channels to use. When grabbing an aux
power domain for port E we need to take this into account.
Cc: Ville Syrjälä
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c | 19
On Tue, Nov 1, 2016 at 4:40 PM, Jani Nikula wrote:
> If we define drm_compat_ioctl NULL on CONFIG_COMPAT=n, we don't have to
> check for the config everywhere.
>
> Signed-off-by: Jani Nikula
Looks good and I like the idea.
Reviewed-by: Patrik Jakobsson
> ---
>
&
The DMC can incorrectly run off and allow DC states on it's own. We
don't know the root-cause for this yet but this patch makes it more
visible.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c| 2 ++
drive
> On Thu, 2016-02-11 at 12:43 +0200, Mika Kuoppala wrote:
> > Patrik Jakobsson writes:
> >
> > > The DMC can incorrectly run off and allow DC states on it's own. We
> > > don't know the root-cause for this yet but this patch makes it more
> > >
On Thu, Feb 18, 2016 at 11:22 AM, Patrik Jakobsson
wrote:
> On Thu, Feb 18, 2016 at 12:16:40AM +, Vivi, Rodrigo wrote:
>> I was going to merge here but I saw on patchwork we got some warnings
>> so I'm not sure they are only false positives or this is exactly what
&
fix handling of the disable_power_well module
> option")
> CC: sta...@vger.kernel.org
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> 1 file changed, 3 insertions(+), 3
he
> i915.disable_power_well module option, added in the next patch.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 74
> +++--
> 2 files cha
power wells regardless of the disable_power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915
power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Nice to see these go.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 41
> +
> 1 file changed, 1 insertion(+), 40 deletions(-)
he
> i915.disable_power_well module option, added in the next patch.
>
> v2:
> - Print a debug message if the requested max DC value was adjusted due
> to a platform limit. Also debug print the calculated mask value. (Patrik)
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Dea
power wells regardless of the disable_power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915
On Wed, Mar 02, 2016 at 07:13:07PM +0200, Imre Deak wrote:
> On Fri, 2016-02-26 at 10:02 -0800, Rodrigo Vivi wrote:
> > [...]
> > Well, I have this tree:
> > https://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=rpm-domains-psr-vblank-counter-full
> > with mainly:
> > 1 - vblank domain on pre-enab
0x3);
> return (val & 0x3) == 0x3;
> }
>
> @@ -1354,11 +1352,9 @@ static void pci_d3_state_subtest(void)
> igt_require(has_runtime_pm);
>
> disable_all_screens_and_wait(&ms_data);
> -
> - igt_assert(device_in_pci_d3());
> + igt_assert(i
Left behind by DC state rework and is no longer needed.
Cc: Imre Deak
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_drv.h| 1 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ---
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers
DMC is
> "expected". Tune down the corresponding WARN to be a debug message. This
> was caught by CI suspend tests.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Was just about to bug you about this. You're one step ahead of me :)
Reviewed-by:
e regressions on stuff like this? And if so,
who do we ping about this?
OTOH impact should be really small and since this fixes a real problem:
Reviewed-by: Patrik Jakobsson
>
> These are the original EI/thresholds:
> LOW_POWER
> GEN6_RP_UP_EI 12500
> GEN6_RP_U
On Tue, Apr 19, 2016 at 09:52:23AM +0200, Maarten Lankhorst wrote:
> Instead of calling prepare_flip right before calling finish_page_flip
> do everything from prepare_page_flip in finish_page_flip.
>
> Putting prepare and finish page_flip in a single step removes the need
> for INTEL_FLIP_COMPLET
gt; Cc: Christophe Prigent
> Cc: Patrik Jakobsson
> Reviewed-by: Ben Widawsky (v1)
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_csr.c | 30 +++---
> 1 file changed, 19 insertions(+), 11 deletions(-)
>
> diff --git a/dr
t; v3: With right CSR_VERSION (Patrik).
>
> Cc: Christophe Prigent
> Cc: Patrik Jakobsson
> Reviewed-by: Ben Widawsky (v1)
> Signed-off-by: Rodrigo Vivi
As discussed on IRC, feel free to push this when satisfied with testing.
Reviewed-by: Patrik Jakobsson
&g
On Tue, Apr 19, 2016 at 09:52:22AM +0200, Maarten Lankhorst wrote:
> Both intel_unpin_work.pending and intel_unpin_work.enable_stall_check
> were used to see if work should be enabled. By only using pending
> some special cases are gone, and access to unpin_work can be simplified.
>
> Use this to
On Tue, Apr 19, 2016 at 09:52:24AM +0200, Maarten Lankhorst wrote:
> This uses the newly created drm_accurate_vblank_count_and_time to accurately
> get a vblank count when the hw counter is unavailable.
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++
> drivers/gpu/drm/i915/intel_drv.
On Thu, Apr 28, 2016 at 10:48:55AM +0200, Maarten Lankhorst wrote:
> Op 27-04-16 om 15:24 schreef Patrik Jakobsson:
> > On Tue, Apr 19, 2016 at 09:52:22AM +0200, Maarten Lankhorst wrote:
> >> Both intel_unpin_work.pending and intel_unpin_work.enable_stall_check
> >> were
; Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
> drivers/gpu/drm/i915/intel_display.c | 189
> +++
> drivers/gpu/drm/i915/intel_drv.h | 19 ++--
> drivers/gpu/drm/i
On Tue, Apr 19, 2016 at 09:52:28AM +0200, Maarten Lankhorst wrote:
> This will be required to allow more than 1 update in the future.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 90 +-
> drivers/gpu/drm/i915/i915_drv.h |
On Tue, Apr 19, 2016 at 09:52:29AM +0200, Maarten Lankhorst wrote:
> Set plane_state->base.fence to the dma_buf exclusive fence,
> and add a wait to the mmio function. This will make it easier
> to unify plane updates later on.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by
On Thu, Apr 28, 2016 at 12:20:09PM +0200, Maarten Lankhorst wrote:
> Op 28-04-16 om 11:54 schreef Patrik Jakobsson:
> > On Thu, Apr 28, 2016 at 10:48:55AM +0200, Maarten Lankhorst wrote:
> >> Op 27-04-16 om 15:24 schreef Patrik Jakobsson:
> >>> On Tue, Apr 19, 201
Load specific firmware versions for the DMC instead of using symbolic
links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
BXT 1.07.
Cc: Rodrigo Vivi
Cc: Imre Deak
Cc: Mika Kuoppala
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_csr.c | 29
On Wed, Apr 27, 2016 at 05:23:06PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 27, 2016 at 04:06:16PM +0200, Patrik Jakobsson wrote:
> > On Tue, Apr 19, 2016 at 09:52:24AM +0200, Maarten Lankhorst wrote:
> > > This uses the newly created drm_accurate_vblank_count_and_time to
arten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 1d7ef9fb526c..8b61a07c4c52 100644
> ---
On Tue, May 10, 2016 at 03:52:02PM +0300, Mika Kuoppala wrote:
> Patrik Jakobsson writes:
>
> > [ text/plain ]
> > Load specific firmware versions for the DMC instead of using symbolic
> > links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
> >
On Tue, Apr 19, 2016 at 09:52:32AM +0200, Maarten Lankhorst wrote:
> With the removal of cs flips this is always force enabled.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 -
> drivers/gpu/drm/i915
On Tue, Apr 19, 2016 at 09:52:33AM +0200, Maarten Lankhorst wrote:
> With the removal of cs support this is no longer reachable.
> Can be revived if needed.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_drv.h |
orst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +---
> drivers/gpu/drm/i915/intel_drv.h | 8 ++--
> drivers/gpu/drm/i915/intel_fbc.c | 39
> +---
> 3 files changed, 29 insertions(+),
On Tue, Apr 19, 2016 at 09:52:35AM +0200, Maarten Lankhorst wrote:
> check_connector_state might get called from unpin_work, which means
verify_connector_state and not check_connector_state?
Otherwise looks good
Reviewed-by: Patrik Jakobsson
> that the mst removal function has to fl
provide a tested and known working configuration we must lock down on
a specific DMC firmware version.
Cc: Rodrigo Vivi
Cc: Imre Deak
Cc: Mika Kuoppala
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_csr.c | 29 ++---
1 file changed, 14 insertions(+), 15
ad() needs a full smp_rmb.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 11 +++---
> drivers/gpu/drm/i915/intel_display.c | 71
> ++--
> drivers/gpu/drm/i915/intel_drv.h |
On Tue, May 17, 2016 at 03:07:46PM +0200, Maarten Lankhorst wrote:
> This function is duplicated with intel_finish_page_flip,
> and is only ever used from planes that could use the
> other function anyway.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
>
ing is turned into a bool.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +--
> drivers/gpu/drm/i915/i915_irq.c | 18 ++---
> drivers/gpu/drm/i915/intel_display.c | 72
> +++--
On Tue, May 17, 2016 at 03:07:48PM +0200, Maarten Lankhorst wrote:
> This uses the newly created drm_accurate_vblank_count_and_time to accurately
> get a vblank count when the hw counter is unavailable.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
MMIO flips get their own path through intel_finish_page_flip_mmio,
> handled on vblank. CS page flips go through *_cs.
>
> Changes since v1:
> - Clean up destinction between MMIO and CS flips.
>
> Signed-off-by: Maarten Lankhorst
Much nicer with the cs / mmio spli
arten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d349a8118a56..6526bb5a7afb 100644
> ---
ich update_plane can be called with a freed
> crtc_state. Because of this commit acf4e84d61673
> ("drm/i915: Avoid stalling on pending flips for legacy cursor updates")
> is temporarily reverted.
>
> Changes since v1:
> - Split out the flip_work rename.
>
> Signed-off
On Tue, May 17, 2016 at 03:07:52PM +0200, Maarten Lankhorst wrote:
> This will be required to allow more than 1 update in the future.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 90 +++--
>
On Tue, May 17, 2016 at 03:07:53PM +0200, Maarten Lankhorst wrote:
> Set plane_state->base.fence to the dma_buf exclusive fence,
> and add a wait to the mmio function. This will make it easier
> to unify plane updates later on.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by
On Tue, May 17, 2016 at 03:07:55PM +0200, Maarten Lankhorst wrote:
> With mmio flips now available on all platforms it's time to remove
> support for cs flips.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs
On Tue, May 17, 2016 at 03:07:56PM +0200, Maarten Lankhorst wrote:
> With the removal of cs flips this is always force enabled.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 -
> drivers/gpu/drm/i915
On Tue, May 17, 2016 at 03:07:57PM +0200, Maarten Lankhorst wrote:
> With the removal of cs support this is no longer reachable.
> Can be revived if needed.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_drv.h |
On Tue, May 17, 2016 at 03:07:58PM +0200, Maarten Lankhorst wrote:
> With the removal of cs-based flips all mmio waits will
> finish without requiring the reset counter, because the
> waits will complete during gpu reset.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: P
orst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +---
> drivers/gpu/drm/i915/intel_drv.h | 8 ++--
> drivers/gpu/drm/i915/intel_fbc.c | 39
> +---
> 3 files changed, 29 insertions(+),
On Tue, May 17, 2016 at 03:08:02PM +0200, Maarten Lankhorst wrote:
> This reapplies commit acf4e84d6167317ff21be5c03e1ea76ea5783701.
> With async unpin this should no longer break.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i9
is destroyed, so to find
> this add some checks when it happens.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel
e v2:
> - Add hunk for calling hw state verifier.
> - Add missing support for color spaces.
>
> Signed-off-by: Maarten Lankhorst
I would have liked this one to be split into smaller pieces but since I can't
find any good points to split at, I think this is good eno
fy.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 53
> ++--
> drivers/gpu/drm/i915/intel_drv.h | 4 +++
> 2 files changed, 43 insertions(+), 14 deletions(-)
&g
On Tue, May 17, 2016 at 03:08:01PM +0200, Maarten Lankhorst wrote:
> All of intel_post_plane_update is handled there now, so move it over.
> This is run after the hw state checker because it can't handle checking
> crtc's separately yet.
>
> Signed-off-by: Maarten Lankho
On Tue, May 17, 2016 at 03:08:04PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
We could have had a short note on what the patch does, though reading it is
quite straight forward. Either way is fine by me.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu
On Tue, May 17, 2016 at 03:07:43PM +0200, Maarten Lankhorst wrote:
> Connector lifetime patches forced a rethinking for handling connectors.
> Instead of flushing modesets from the connector destroy function this
> meant destroying the connector state inside the unpin_work function,
> similar to th
On Wed, May 18, 2016 at 01:24:12PM +0300, Mika Kuoppala wrote:
> Patrik Jakobsson writes:
>
> > [ text/plain ]
> > Load specific firmware versions for the DMC instead of using symbolic
> > links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
> >
t; disabling also synchronous.
>
> CC: Mika Kuoppala
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/
_can_enable_dc5() is incorrect. There is a more generic and
> correct assert for this already in gen9_set_dc_state(), so we can remove
> all the other ones.
>
> At the same time convert WARNs to WARN_ONCE for consistency with the
> other DC state asserts.
>
> CC: Patrik Jakobsson
d on a manual DC9 flow. For this we have to uninitialize the
> display following the BSpec display uninit sequence, just as during
> S3/S4, so make sure we follow this sequence.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
>
On Fri, Apr 01, 2016 at 04:02:39PM +0300, Imre Deak wrote:
> On Broxton we need to enable/disable power well 1 during the init/unit display
> sequence similarly to Skylake/Kabylake. The code for this will be added in a
> follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
enable vs. disable power well call in
> skl_display_core_uninit() (Patrik)
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_drv.h| 2 --
> drivers/gpu/drm/i915/intel_runtime_pm.c | 49
> -
> 2 files cha
On Mon, Apr 04, 2016 at 12:34:30PM +0200, Patrik Jakobsson wrote:
> On Fri, Apr 01, 2016 at 04:02:36PM +0300, Imre Deak wrote:
> > So far we only power well enabling was synchronous not disabling. Since
> > we don't exactly know how the firmware (both DMC and PCU) synchron
On Thu, Mar 31, 2016 at 06:46:36PM -0700, Matt Roper wrote:
> Moving watermark calculation into the check phase will allow us to to
> reject display configurations for which there are no valid watermark
> values before we start trying to program the hardware (although those
> tests will come in a s
expect any request bits in here either, so
> sanitize this register as well.
>
> v2:
> - apply the workaround on SKL as well
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Hmm, more DMC fun.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runt
PCH ports
>
> Cc: Daniel Vetter
> Signed-off-by: Ville Syrjälä
> Reviewed-by: Daniel Vetter (v1)
I've not been able to find any additional ILK hardware to test this on but LGTM
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 45
> +
ust prior to enabling the eDP PLL.
>
> Cc: Daniel Vetter
> Signed-off-by: Ville Syrjälä
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_dp.c | 36 +---
> 1 file changed, 9 insertions(+), 27 deletions(-)
>
> diff --git
programmed watermark levels intact.
>
> Fixes underruns on the already enabled pipe when programming watermarks
> while enabling the second pipe.
>
> Cc: Daniel Vetter
> Cc: Matt Roper
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93787
> Signed-off-by: V
and MISC IO
> power well disabling in the latest CI run.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Ok, so this seems to affect all DMC firmwares we have so far? Any news on the
bug report?
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_run
On Mon, Oct 12, 2015 at 05:07:13PM +0300, Imre Deak wrote:
> On ma, 2015-10-12 at 16:37 +0300, Imre Deak wrote:
> > On ma, 2015-08-03 at 21:55 +0530, Animesh Manna wrote:
> > > While display engine entering into low power state no need to disable
> > > cdclk pll as CSR firmware of dmc will take car
The current CSR loading code depends on the CSR program memory to be
cleared after boot. This is unfortunately not true on all hardware.
Instead make use of the FW_UNINITIALIZED state in init and check for
FW_LOADED to prevent init path from skipping the actual programming.
Signed-off-by: Patrik
On Thu, Oct 22, 2015 at 6:07 PM, Rodrigo Vivi wrote:
> regarding your offline question: yes, I had your patch applied here, so
>
> Tested-by: Rodrigo Vivi
>
> On Wed, Oct 21, 2015 at 7:57 AM, Patrik Jakobsson
> wrote:
>> The current CSR loading code depends on the
initialization of state to after HAS_CSR() check
Signed-off-by: Patrik Jakobsson
Tested-by: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
+0200, Patrik Jakobsson wrote:
> The current CSR loading code depends on the CSR program memory to be
> cleared after boot. This is unfortunately not true on all hardware.
> Instead make use of the FW_UNINITIALIZED state in init and check for
> FW_LOADED to prevent init path from skipping the a
On Sat, Oct 24, 2015 at 11:03:05AM +0530, Animesh Manna wrote:
>
>
> On 10/23/2015 3:11 PM, Patrik Jakobsson wrote:
> >The current CSR loading code depends on the CSR program memory to be
> >cleared after boot. This is unfortunately not true on all hardware.
>
On Tue, Oct 27, 2015 at 08:41:31PM +0200, Imre Deak wrote:
> On pe, 2015-10-23 at 11:41 +0200, Patrik Jakobsson wrote:
> > The current CSR loading code depends on the CSR program memory to be
> > cleared after boot. This is unfortunately not true on all hardware.
> > In
When booting (warm or cold) we must always program the csr. Previously
we checked if the CSR program memory matched with the firmware data but
this turned out to fail on warm boots.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_csr.c | 6
Aux A communication.
[1]
http://lists.freedesktop.org/archives/intel-gfx/2015-October/079041.html
[2]
http://lists.freedesktop.org/archives/intel-gfx/2015-October/078898.html
Patrik Jakobsson (5):
drm/i915: Add a modeset power domain
drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()
drm
: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
drivers/gpu/drm/i915/intel_display.c| 6 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 107 +---
3 files changed, 78 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 6 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm
power domains. We're already really close to the limit...
[Patrik: Add gmbus string to debugfs output]
Signed-off-by: Ville Syrjälä
Reviewed-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i
From: Ville Syrjälä
All the DDI power domains are already excluded from
SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS on account of
excluding SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS and
SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, no need to spell them out again.
Signed-off-by: Ville Syrjälä
Reviewed-by: Patrik
We need DC5/DC6 to be disabled around modesets to prevent confusing the
DMC. Also, we've run out of bits in the 32 bit power domain mask so now
it's a 64 bit mask.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h
ing for CHV at least. But I think it's still a
worthwile change.
Signed-off-by: Ville Syrjälä
Reviewed-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c | 40 ++
drivers/gpu/drm/i915/intel_dp.c | 48 +++-
drivers
PG2 enabled is not a requirement for disabling DC5. It's just one
of the reasons why we wouldn't enter DC5. During modeset we don't care
about PG2 from a DC perspective, only the fact that DC5/DC6 is not
allowed.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_r
On Tue, Nov 03, 2015 at 03:08:41PM +0200, Jani Nikula wrote:
> On Tue, 03 Nov 2015, Patrik Jakobsson
> wrote:
> > Signed-off-by: Patrik Jakobsson
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_params.c | 6 ++
1 - 100 of 266 matches
Mail list logo
