ICL DSI encoder needs to do the clock gating and
ungating slightly differently, and this allows its own handling in a
clean fashion.
Looks good to me,
Reviewed-by: Madhav Chauhan
Regards,
Madhav
Cc: Madhav Chauhan
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Add dummy debug logging GPIO element execution function for ICL.
Looks fine to me.
Reviewed-by: Madhav Chauhan
Regards,
Madhav
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +-
1 file changed, 9 insertions
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Add encoder specific pll mapping for DSI. The differences with the DDI
version are big enough to warrant a separate function.
Cc: Madhav Chauhan
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 24
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Some machines seem to have a broken opregion where the VBT overflows the
mailbox. Ignore this until properly fixed.
Right, otherwise DSI modeset doesn't progress further.
Acked-by: Madhav Chauhan
Regards,
Madhav
Signed-off-by: Jani N
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
Jani Nikula (1):
drm/i915/icl: add dummy DSI GPIO element execution function
Madhav Chauhan (14):
drm/i915/icl: Allocate DSI encoder/connector
drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Move DSI connector functions to intel_dsi.c and make them available to
both legacy and ICL DSI.
v2 by Jani:
- Move the functions to intel_dsi.c
- Don't reuse intel_dsi_connector_destroy()
Patch 1 & 2 v2 changes,
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
v3 by Jani:
- Add FIXME note.
Looks OK to me.
Regards
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.
As
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch disables transcoders by writing to TRANS_CONF
registers for each DSI ports.
v2 by Jani:
- Wait for pipeconf active to go low
Thanks for catching this, it has to be low.
Regards,
Madhav
Signed-off-by: Madhav
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
and DSI_TA_TO registers for DSI transcoders '0' and '1'.
They are used for contention recovery on DPHY.
v2: Define SHIFT for bitfields.
v3 by Jan
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Program the timeout values (in escape clock) for HS TX, LP RX and TA
timeout.
HX TX: Ensure that host does not continuously transmit in the HS
state. If this timer expires, then host will gracefully end its HS
transmission and
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch detects DSI presence for ICL platform
by reading VBT. DSI detection is done while initializing
DSI using newly added function intel_gen11_dsi_init.
v2 by Jani:
- Preserve old behavour of intel_bios_is_dsi_present
connector.
v2 by Jani:
- Drop GEN11 prefix from encoder name
- Drop extra parenthesis
- Drop extra local variable
- Squash encoder power domain here
Looks good to me.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 96
structure.
v2 by Jani:
- indentation
Looks fine.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.
v2 by Jani:
- Drop full register mask and shift for payload
- Use lower case for hex 0x
v2 change are fine.
Regards
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch retrieves DSI pkt (from DSI msg) to be
sent over DSI link using DRM DSI exported functions.
A wrapper function is also added as "DSI host transfer"
for sending DSI data/cmd.
v2 by Jani:
- Use the new credit
v2 changes are fine.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 57 ++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch read out the current hw state for DSI and
return true if encoder is active.
v2 by Jani:
- Squash connector get hw state hook here
- Squash encode get hw state fix here
Looks fine to me.
Regards,
Madhav
Signed
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch assigns connector functions for DSI to
DRM connector structure.
v2 by Jani:
- use common connector destroy hook
Looks OK to me.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch registers DSI connectors helper functions
with DRM driver.
v2 by Jani:
- Indentation change
Ok.
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 7
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch implements compute config and enable function
for Gen11 DSI encoder which is required at the time of
modeset. Enable function is empty as functionality is
implemented inside pre-enable function but still needed
otherwise
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch configures DSI video mode dual link by
programming DSS_CTL registers.
v2: Use new bitfield definitions from Anusha's patch
Correct register to be programmed and use max
depth buffer value (James)
v3 by
On 10/30/2018 7:31 PM, Ville Syrjälä wrote:
On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
From: Madhav Chauhan
For ICELAKE DSI, Display Pins are the only GPIOs
that need to be programmed. So DSI driver should have
its own implementation to toggle these pins based on
GPIO info
On 11/1/2018 9:03 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired
f comes in header and payload functionality :).
Regards,
Madhav
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 147 +
1 file changed, 147 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gp
On 11/1/2018 9:04 PM, Jani Nikula wrote:
From: Madhav Chauhan
For Gen11 DSI, we use similar registers like for eDP
to find if DSI encoder is connected or not to a pipe.
This patch refactors existing hsw_get_transcoder_state()
to handle this.
v2 by Jani:
- Add WARN_ON(dsi && edp
On 11/1/2018 9:04 PM, Jani Nikula wrote:
From: Madhav Chauhan
Transcoder timings for Gen11 DSI encoder
is available at pipe level unlike in older platform
where port specific registers need to be accessed.
v2 by Jani:
- get timings for (!dsi || icl) instead of (dsi && icl).
On 11/2/2018 5:17 PM, Jani Nikula wrote:
Add dummy debug logging GPIO element execution function for ICL.
Signed-off-by: Jani Nikula
Its kinda split of "drm/i915/icl: Add changes to program DSI panel GPIOs"
to pave out the way further. Looks good to me.
Reviewed-by: Madhav Chauhan
On 11/2/2018 5:17 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch implements compute config for Gen11 DSI encoder which is
required at the time of modeset.
v2 by Jani:
- drop the enable nop hook
- fixed_mode is always true
- HAS_GMCH_DISPLAY() is always false
v3 by Jani:
- set
On 11/2/2018 5:17 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch read out the current hw state for DSI and
return true if encoder is active.
v2 by Jani:
- Squash connector get hw state hook here
- Squash encode get hw state fix here
v3 by Jani:
- Add encoder->get_power_doma
On 11/2/2018 7:15 PM, Jani Nikula wrote:
On Fri, 02 Nov 2018, Jani Nikula wrote:
Next version of [1]. Sorry for the spam, needed to get the authorship
straight. Fixed power domains and compute config hook initialization.
It looks like DDI intel_ddi_get_hw_state() returns true for ICL DSI as
we
-working scenario in commit message
Cc: Ander Conselvan de Oliveira
Cc: Ville Syrjälä
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_cdclk.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions
screen flicker/shift issue while resuming from S3/S4.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 0dce779..7158c7c
As per BSEPC, if device ready bit is '0' in enable IO sequence
then its a cold boot/reset scenario eg: S3/S4 resume. In these
conditions we need to program certain registers and prepare port
from the middle of DSI enable sequence otherwise feature like S3/S4
doesn't work.
Signed
As per BSEPC, if device ready bit is '0' in enable IO sequence
then its a cold boot/reset scenario eg: S3/S4 resume. In these
conditions we need to program certain registers and prepare port
from the middle of DSI enable sequence otherwise feature like S3/S4
doesn't work.
Signed
screen flicker/shift issue while resuming from S3/S4.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 0dce779..7158c7c
rs_disable().I think, we need to put the check there as well.
With that fix,
Reviewed-by: Madhav Chauhan
Regards,
Madhav
}
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index bafeb2a19b90..dbca30460a6b 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/driver
On 10/15/2018 7:57 PM, Jani Nikula wrote:
Abstract bitrate calculation to a newly resurrected intel_dsi.c file
that will contain common code for VLV and ICL DSI.
No functional changes.
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile
On 10/15/2018 7:57 PM, Jani Nikula wrote:
intel_dsi_vbt_init() has grown too unwieldy, and it's about to be
modified due to ICL DSI. Abstract out the VLV specific dphy param
init. No functional changes. Intentionally no stylistic changes during
code movement.
Cc: Madhav Chauhan
Cc:
On 10/15/2018 7:57 PM, Jani Nikula wrote:
Will be needed in the future. No functional changes.
Agree, will be needing this while setting up DSI protocol timeouts for ICL.
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 13
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch moves couple of legacy DSI functions to header and common DSI
files so that they can be re-used by Gen11 DSI. No functional change.
v2 by Jani:
- Move intel_dsi_msleep() to intel_dsi_vbt.c
This will be used by icl
On 10/16/2018 6:14 PM, Jani Nikula wrote:
On Tue, 16 Oct 2018, Madhav Chauhan wrote:
On 10/15/2018 7:57 PM, Jani Nikula wrote:
Abstract bitrate calculation to a newly resurrected intel_dsi.c file
that will contain common code for VLV and ICL DSI.
No functional changes.
Cc: Madhav Chauhan
On 10/16/2018 6:09 PM, Jani Nikula wrote:
On Tue, 16 Oct 2018, Madhav Chauhan wrote:
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch moves couple of legacy DSI functions to header and common DSI
files so that they can be re-used by Gen11 DSI. No functional change
On 10/16/2018 6:36 PM, Jani Nikula wrote:
On Tue, 16 Oct 2018, Madhav Chauhan wrote:
On 10/15/2018 7:57 PM, Jani Nikula wrote:
Will be needed in the future. No functional changes.
Agree, will be needing this while setting up DSI protocol timeouts for ICL.
Cc: Madhav Chauhan
Cc: Ville
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller wit
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
v2: Changes (Jani N)
- Define _SHIFT and _MASK for bitfields
- Define
On 10/15/2018 7:57 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring
On 10/15/2018 7:58 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.
v2: Changes
On 10/15/2018 7:58 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch select input PIPE for DSI, data lanes width,
enable port sync mode and wait for DSI link to become ready.
v2 by Jani:
- Use MISSING_CASE with fallthrough instead of DRM_ERROR
- minor stylistic changes
v2 changes
On 10/15/2018 7:58 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines registers and bitfields used for
programming DSI transcoder's horizontal and vertical
timings.
v2: Remove TRANS_TIMING_SHIFT definition
v3 by Jani:
- Group macros by transcoder
Separation of DSI0 and
On 10/15/2018 7:58 PM, Jani Nikula wrote:
From: Madhav Chauhan
As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.
v2: Re
On 10/15/2018 7:58 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines TRANS_CONF registers for DSI ports
0 and 1. Bitfields of these registers used for enabling
and reading the current state of transcoder.
v2: Add blank line before comment
v3 by Jani:
- Move DSI specific
On 10/15/2018 7:58 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch enables DSI transcoders by writing to
TRANS_CONF registers and wait for its state to be enabled.
v2 by Jani:
- Rebase
Patch *17-23* changes like rebase, alignment, comments style changes looks
good to me.
Regards
This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b
Escape Clock is used for LP communication across the DSI
Link. To achieve the constant frequency of the escape clock
from the variable DPLL frequency output, a variable divider(M)
is needed. This patch programs the same.
v2: (Jani N) Don't end line with "(".
Signed-off-by:
This patch configures mode of operation for DSI
and enable DDI IO power by configuring power well.
v2: Use for_each_dsi_port() for power get (Jani N)
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 23 +++
1 file changed, 23 insertions(+)
diff
This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 40
1 file changed, 40 insertions
This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915
This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.
v2: Review comments from Jani N
- Fix spaces while defining ICL_ESC_CLK_DIV_MASK
- Define shift and mask for bitfields.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani
This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 38
1 file
- Define PWR_DOWN_LN* macros shifted in place
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dfd603c..3fa8f02 100644
--- a/drive
This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm
This patch defines DSI IO mode control register and it's bits
used while enabling IO power for DSI.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/dr
and rebase for some
other few patches.
Madhav Chauhan (20):
drm/i915/icl: Define register for DSI PLL
drm/i915/icl: Program DSI Escape clock Divider
drm/i915/icl: Define DSI mode ctl register
drm/i915/icl: Enable DSI IO power
drm/i915/icl: Define PORT_CL_DW_10 register
drm/i915/icl
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
Signed-off-by: Madhav Chauhan
---
drivers
This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 47 +
1 file changed, 47 insertions
This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915
To save power, unused lanes should be powered
down using the bitfield of PORT_CL_DW10.
v2: Review comments from Jani N
- Put default label next to case 4
- Include the shifts in the macros
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_new.c
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.
v2: Rebase
Signed-off-by: Madhav Chauhan
This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_display.h | 6 --
drivers/gpu/drm/i915/intel_dsi_new.c | 9 +
2 files changed, 13
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
Signed-off-by: Madhav Chauhan
---
driv
This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
DSI transcoder registers.
Credits-to: Jani N
Cc: Jani Nikula
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
and rebase for some
other few patches.
v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
Ville. Also addressed review comments for couple of patches.
Madhav Chauhan (20):
drm/i915/icl: Define register for DSI PLL
drm/i915/icl: Program DSI Escape clock Divider
This patch defines DSI IO mode control register and it's bits
used while enabling IO power for DSI.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/dr
This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.
v2: Review comments from Jani N
- Fix spaces while defining ICL_ESC_CLK_DIV_MASK
- Define shift and mask for bitfields.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani
This patch configures mode of operation for DSI
and enable DDI IO power by configuring power well.
v2: Use for_each_dsi_port() for power get (Jani N)
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/gen11_dsi.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a
- Define PWR_DOWN_LN* macros shifted in place
v3: Correct PWR_DOWN_LN_MASK value (Jani N)
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drive
Escape Clock is used for LP communication across the DSI
Link. To achieve the constant frequency of the escape clock
from the variable DPLL frequency output, a variable divider(M)
is needed. This patch programs the same.
v2: (Jani N) Don't end line with "(".
Signed-off-by:
This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/gen11_dsi.c | 38 ++
1 file changed
This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915
This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.
v2: Review comments from Jani N:
- Define _ICL_PORT_PCS_DW1_AUX_A for consistency
- Three spaces for bitfield definition.
Signed-off-by: Madhav Chauhan
Reviewed-by
This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/gen11_dsi.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915
To save power, unused lanes should be powered
down using the bitfield of PORT_CL_DW10.
v2: Review comments from Jani N
- Put default label next to case 4
- Include the shifts in the macros
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/gen11_dsi.c | 40
This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/gen11_dsi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/gen11_dsi.c b
This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 40
1 file changed, 40 insertions
This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
DSI transcoder registers.
Credits-to: Jani N
Cc: Jani Nikula
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
Signed-off-by: Madhav Chauhan
---
drivers
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
Signed-off-by: Madhav Chauhan
---
driv
This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/gen11_dsi.c | 9 +
drivers/gpu/drm/i915/intel_display.h | 6 --
2 files changed, 13
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 47 +
1 file changed, 47 insertions
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.
v2: Rebase
Signed-off-by: Madhav Chauhan
and rebase for some
other few patches.
v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
Ville. Also addressed review comments for couple of patches.
v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes.
Madhav Chauhan (20):
drm/i915/icl: Define
This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.
v2: Review comments from Jani N
- Fix spaces while defining ICL_ESC_CLK_DIV_MASK
- Define shift and mask for bitfields.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani
Escape Clock is used for LP communication across the DSI
Link. To achieve the constant frequency of the escape clock
from the variable DPLL frequency output, a variable divider(M)
is needed. This patch programs the same.
v2: (Jani N) Don't end line with "(".
Signed-off-by:
This patch defines DSI IO mode control register and it's bits
used while enabling IO power for DSI.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/dr
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