On 10/16/2023 15:55, Vinay Belgaumkar wrote:
This bit does not cause an explicit L3 flush. We already use
At all? Or only on newer hardware? And as a genuine spec change or as a
bug / workaround?
If the hardware has re-purposed the bit then it is probably worth at
least adding a comment to th
0-13 11:34:26
-0700)
----
John Harrison (1):
i915: Add GuC v70.13.1 for DG2, TGL, ADL-P and MTL
WHENCE | 8
i915/adlp_guc_70.bin | Bin 297984 -> 342848 bytes
i915/dg2_guc_70.bin | Bin 385856 -> 443200 bytes
value to the
user as is.
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_engine.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 12
drivers/gpu/drm/i915/gt
On 10/6/2023 17:10, Belgaumkar, Vinay wrote:
On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.
Signed-off-by: John
On 10/6/2023 17:38, Belgaumkar, Vinay wrote:
On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:
From: John Harrison
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
Signed-off-by: John Harrison
---
.../gpu/drm/i915
On 11/9/2023 12:33, Daniele Ceraolo Spurio wrote:
On 11/6/2023 3:59 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There is a mechanism for reporting errors from fire and forget H2G
messages. This is the only way to find out about almost any error in
the GuC backend submission path
m that supports neither HuC nor GuC. There
would be no GuC warning because GuC was not requested. But now there
would also be no HuC warning either.
John.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 5 -
1 file changed, 5 deletions
On 11/13/2023 07:36, Daniele Ceraolo Spurio wrote:
On 11/9/2023 6:06 PM, John Harrison wrote:
On 11/9/2023 15:54, Daniele Ceraolo Spurio wrote:
On MTL, the HuC is only supported on the media GT, so our validation
check on the module parameter detects an inconsistency on the root GT
(the
On 11/21/2023 10:55, Alan Previn wrote:
Add missing tag for "Wa_14019159160 - Case 2" (for existing
PXP code that ensures run alone mode bit is set to allow
PxP-decryption.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletio
R may have more success, but that is
not something that i915 currently does.
John.
v2: Improve commit message(Tvrtko)
Cc: Tvrtko Ursulin
Cc: John Harrison
Cc: Andi Shyti
Cc: Andrzej Hajda
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5591
Signed-off-by: Nirmoy Das
Review
On 12/5/2023 02:39, Nirmoy Das wrote:
Hi John,
On 12/5/2023 10:10 AM, John Harrison wrote:
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Convert the log
On 1/4/2024 12:34, Daniele Ceraolo Spurio wrote:
On 1/2/2024 2:22 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A failure to load the HuC is occasionally observed where the cause is
believed to be a low GT frequency leading to very long load times.
So a) increase the timeout so
ease that is not ancient.
Signed-off-by: Joonas Lahtinen
Cc: Kenneth Graunke
Cc: Jose Souza
Cc: Sagar Ghuge
Cc: Paulo Zanoni
Cc: John Harrison
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_getparam.c | 12
include/uapi/drm/i
On 9/14/2022 10:07, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Fix bug in version reduced firmware update (rev2)
*URL:* https://patchwork.freedesktop.org/series/108461/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/
On 9/15/2022 01:59, Tvrtko Ursulin wrote:
Hi,
On 15/09/2022 00:46, john.c.harri...@intel.com wrote:
From: John Harrison
Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This
On 9/16/2022 02:10, Tvrtko Ursulin wrote:
On 15/09/2022 21:03, John Harrison wrote:
On 9/15/2022 01:59, Tvrtko Ursulin wrote:
Hi,
On 15/09/2022 00:46, john.c.harri...@intel.com wrote:
From: John Harrison
Going forwards, the intention is for GuC firmware files to be named
for their major
On 9/22/2022 07:26, Dan Carpenter wrote:
Hello Matthew Brost,
The patch 6b540bf6f143: "drm/i915/guc: Implement multi-lrc
submission" from Oct 14, 2021, leads to the following Smatch static
checker warning:
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:752
__guc_add_request()
On 9/23/2022 00:48, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* DG2 fix for CCS starvation
*URL:* https://patchwork.freedesktop.org/series/108919/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108919v1/index.html
CI Bug
On 9/28/2022 00:19, Tvrtko Ursulin wrote:
On 27/09/2022 22:36, Ceraolo Spurio, Daniele wrote:
On 9/27/2022 12:45 AM, Tvrtko Ursulin wrote:
On 27/09/2022 07:49, Andrzej Hajda wrote:
On 27.09.2022 01:34, Ceraolo Spurio, Daniele wrote:
On 9/26/2022 3:44 PM, Andi Shyti wrote:
Hi Andrzej,
On Mon
On 9/29/2022 00:42, Tvrtko Ursulin wrote:
On 29/09/2022 03:18, john.c.harri...@intel.com wrote:
From: John Harrison
Compute workloads are inherently not pre-emptible for long periods on
current hardware. As a workaround for this, the pre-emption timeout
for compute capable engines was
On 9/29/2022 01:22, Tvrtko Ursulin wrote:
On 28/09/2022 19:27, John Harrison wrote:
On 9/28/2022 00:19, Tvrtko Ursulin wrote:
On 27/09/2022 22:36, Ceraolo Spurio, Daniele wrote:
On 9/27/2022 12:45 AM, Tvrtko Ursulin wrote:
On 27/09/2022 07:49, Andrzej Hajda wrote:
On 27.09.2022 01:34
On 9/30/2022 02:22, Tvrtko Ursulin wrote:
On 29/09/2022 17:21, John Harrison wrote:
On 9/29/2022 00:42, Tvrtko Ursulin wrote:
On 29/09/2022 03:18, john.c.harri...@intel.com wrote:
From: John Harrison
Compute workloads are inherently not pre-emptible for long periods on
current hardware. As
On 9/29/2022 18:05, Alan Previn wrote:
During GuC error capture initialization, we estimate the amount of size
we need for the error-capture-region of the shared GuC-log-buffer.
This calculation was incorrect so fix that. Additionally, if the size
was insufficient, don't drm_warn or drm_notice, j
On 9/30/2022 14:08, Teres Alexis, Alan Previn wrote:
I disagree because its unlikely that all engines can reset all at once (we
probably have bigger problems at the at
point) and if they all occurred within the same G2H handler scheduled worker
run, our current gpu_coredump framework
would just
MTL as well, given that the amount
of duplicated memory is relatively small (~500K).
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
city, instead of
calculating the exact required size, we reserve a 2MB slot for each fw.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
d
On 9/22/2022 15:11, Daniele Ceraolo Spurio wrote:
From: Stuart Summers
MTL supports GuC deprivilege. Add the feature flag to this platform.
Signed-off-by: Stuart Summers
Cc: Radhakrishna Sripada
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915
On 9/22/2022 15:11, Daniele Ceraolo Spurio wrote:
The media GT shares the G-unit with the root GT, so a second set of
communication registers is required for the media GuC.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers
On 10/3/2022 11:28, Teres Alexis, Alan Previn wrote:
On Fri, 2022-09-30 at 15:35 -0700, Harrison, John C wrote:
On 9/30/2022 14:08, Teres Alexis, Alan Previn wrote:
I disagree because its unlikely that all engines can reset all at once (we
probably have bigger problems at the at
point) and if
On 10/3/2022 14:10, Teres Alexis, Alan Previn wrote:
On Mon, 2022-10-03 at 12:47 -0700, Harrison, John C wrote:
On 10/3/2022 11:28, Teres Alexis, Alan Previn wrote:
On Fri, 2022-09-30 at 15:35 -0700, Harrison, John C wrote:
On 9/30/2022 14:08, Teres Alexis, Alan Previn wrote:
I disagree becau
On 10/3/2022 17:46, Teres Alexis, Alan Previn wrote:
So as per the last response and the offline conversation we had we agreed that:
1. we shall stick with drm_warn( ... maybe too small...) if the allocation
didn't meet min_size.
2. I'll model for PVC (since its better to look at the spec as op
On 10/3/2022 05:00, Tvrtko Ursulin wrote:
On 03/10/2022 08:53, Tvrtko Ursulin wrote:
On 30/09/2022 18:44, John Harrison wrote:
On 9/30/2022 02:22, Tvrtko Ursulin wrote:
On 29/09/2022 17:21, John Harrison wrote:
On 9/29/2022 00:42, Tvrtko Ursulin wrote:
On 29/09/2022 03:18, john.c.harri
On 9/21/2022 10:32, Alan Previn wrote:
From: Matthew Brost
Add a delay, configurable via debugfs (default 34ms), to disable
scheduling of a context after the pin count goes to zero. Disable
scheduling is a costly operation as it requires synchronizing with
the GuC. So the idea is that a delay a
PTURE_BUFFER_SIZESZ_1M
#else
#define GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE SZ_8K
#define GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE SZ_64K
-#define GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZESZ_2M
+#define GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZESZ_1M
#endif
I would have pulled these outside the if/
On 10/6/2022 10:20, Daniele Ceraolo Spurio wrote:
We're observing sporadic HuC delayed load timeouts in CI, due to mei_pxp
binding completing later than we expected. HuC is still still loaded
still still
when the bind occurs, but in the meantime i915 has started allowing
submission to the VCS
On 10/6/2022 13:16, Ceraolo Spurio, Daniele wrote:
On 10/6/2022 1:09 PM, John Harrison wrote:
On 10/6/2022 10:20, Daniele Ceraolo Spurio wrote:
We're observing sporadic HuC delayed load timeouts in CI, due to
mei_pxp
binding completing later than we expected. HuC is still still loaded
ule task
be flushed of it. Move them directly into the closed state after cancelling
the worker. This is okay because the existing flow flushes all
yet-to-arrive G2H's dropping them anyway.
Signed-off-by: Matthew Brost
Signed-off-by: Alan Previn
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-b
hange also closes the race for when
a new incoming request fails to cancel the pending
delayed disable-sched worker.
With these two complementary checks, we see no more
use for intel_context:guc_state:number_committed_requests.
Signed-off-by: Alan Previn
Reviewed-by: John Harrison
---
drive
On 11/17/2022 09:33, Matt Roper wrote:
...
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 830edffe88cc..d9a8ff9e5e57 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -730,17 +730,19 @@ void in
leak of debug object in huc load fence on
driver unload")
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 47 +++---
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915
On 11/30/2022 00:30, Tvrtko Ursulin wrote:
On 29/11/2022 21:12, john.c.harri...@intel.com wrote:
From: John Harrison
Engine resets are supposed to never happen. But in the case when one
Engine resets or engine reset failures? Hopefully the latter.
Oops. Yes, that was meant to say "e
On 11/30/2022 01:47, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* More GuC firmware version improvements (rev3)
*URL:* https://patchwork.freedesktop.org/series/111218/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111218v3/ind
On 11/29/2022 00:43, Tvrtko Ursulin wrote:
On 28/11/2022 16:52, Andrzej Hajda wrote:
In case context is exiting preempt_timeout_ms is used for timeout,
but since introduction of DRM_I915_PREEMPT_TIMEOUT_COMPUTE it increases
to 7.5 seconds. Heartbeat occurs earlier but it is still 2.5s.
Fixes: d
On 11/23/2022 12:45, Michal Wajdeczko wrote:
On 23.11.2022 02:25, John Harrison wrote:
On 11/22/2022 09:54, Michal Wajdeczko wrote:
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
From: John Harrison
Re-work the existing GuC CT printers and extend as required to match
the new wrapping
e the GuC objects.
In MTL, this fixes and issue where we try to overwrite the invalidation
function twice (once for each GuC), due to the GGTT being shared between
the primary and media GTs
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Cc: Radhakrishna Sripada
Cc: John Harrison
Cc: Ar
On 12/1/2022 04:01, Tvrtko Ursulin wrote:
On 01/12/2022 11:56, Michal Wajdeczko wrote:
On 01.12.2022 01:41, John Harrison wrote:
On 11/23/2022 12:45, Michal Wajdeczko wrote:
On 23.11.2022 02:25, John Harrison wrote:
On 11/22/2022 09:54, Michal Wajdeczko wrote:
On 18.11.2022 02:58
On 12/12/2022 17:52, Umesh Nerlige Ramappa wrote:
On Tue, Nov 29, 2022 at 01:12:52PM -0800, john.c.harri...@intel.com
wrote:
From: John Harrison
There was a report of error captures occurring without any hung
context being indicated despite the capture being initiated by a 'hung
co
On 9/30/2022 16:42, Ceraolo Spurio, Daniele wrote:
On 9/30/2022 4:24 PM, John Harrison wrote:
On 9/22/2022 15:11, Daniele Ceraolo Spurio wrote:
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This wor
On 10/6/2022 15:20, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Improve anti-pre-emption w/a for compute workloads (rev8)
*URL:* https://patchwork.freedesktop.org/series/100428/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1
#x27;m also reducing
the print verbosity from error to notice.
v2: use separate prints for MEI GSC and MEI PXP init timeouts (John)
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7033
Fixes: 27536e03271d ("drm/i915/huc: track delayed HuC load with a fence")
Signed-off-by: Danie
On 10/10/2022 15:57, Ceraolo Spurio, Daniele wrote:
On 10/10/2022 3:50 PM, John Harrison wrote:
On 10/10/2022 11:48, Daniele Ceraolo Spurio wrote:
We're observing sporadic HuC delayed load timeouts in CI, due to
mei_pxp
binding completing later than we expected. HuC is still loaded whe
On 10/13/2022 09:14, Andrzej Hajda wrote:
In case of catastrophic errors GuC is able to initate engine
reset immediately, instead of waiting for timeout.
Signed-off-by: Andrzej Hajda
---
Hi all,
I am new in the subject, so please be polite if this is mistake.
Tests shows that it allows to save
HuC load with a fence")
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: John Harrison
Cc: Tony Ye
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/i
On 10/14/2022 20:59, Alan Previn wrote:
If GuC is being used and we initialized GuC-error-capture,
we need to be warning if we don't provide an error-capture
register list in the firmware ADS, for valid GT engines.
A warning makes sense as this would impact debugability
without realizing why a re
improve comments (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 +---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 13 ++
2 files changed, 40 insertions(+), 3 deletions(-)
diff --git a
On 10/17/2022 16:36, Teres Alexis, Alan Previn wrote:
Agreed on all the others (as per my other reply to Tvrtko), but on that 2nd
last one:
On Mon, 2022-10-17 at 12:33 -0700, Harrison, John C wrote:
On 10/14/2022 20:59, Alan Previn wrote:
If GuC is being used and we initialized GuC-error-capt
are pre-locked
by the bios. Therefore, we can skip all the math for the partitioning
and just limit ourselves to sanity checking the values.
v2: fix makefile file ordering (Jani)
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Cc: John Harrison
Cc: A
On 10/19/2022 01:33, Andrzej Hajda wrote:
In case of catastrophic errors GuC sends notification, which results in
cryptic message. Let's add handler which, for starters, dumps state
of affected engine.
See below - the notification is sent by the GPU memory subsystem not the
GuC. Also, not sure w
On 10/19/2022 00:29, Alan Previn wrote:
We missed this at initial upstream because at that time
none of the GuC enabled platforms had a compute engine.
Add this now.
Signed-off-by: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 4
1 file
ter engine-class-registers (new) on top
of the legacy blitter engine-instance-register (HEAD, TAIL, etc.),
no warning is generated.
Signed-off-by: Alan Previn
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 78 ---
1 file changed, 69 insert
improve comments (John)
v3: more comment improvements (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 +---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 14 +
ing the values.
v2: fix makefile file ordering (Jani)
v3: drop XELPM_SAMEDIA_WOPCM_SIZE, check huc instead of VDBOX (John)
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Cc: John Harrison
Cc: Alan Previn
Cc: Jani Nikula
---
Documentation/gpu/i915.rst
On 10/24/2022 14:39, Ceraolo Spurio, Daniele wrote:
On 10/24/2022 2:33 PM, John Harrison wrote:
On 10/21/2022 17:10, Daniele Ceraolo Spurio wrote:
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed
with
separate partitioning in WOPCM for GCD/GT GuC
XELPM_SAMEDIA_WOPCM_SIZE, check huc instead of VDBOX (John)
v4: further clarify commit message, remove blank line (John)
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Cc: John Harrison
Cc: Alan Previn
Cc: Jani Nikula
Reviewed-by: John Harrison
---
Documentation/gpu
ags). I can fix that
when merging, though.
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 29 ---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 6 ++--
2 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu
On 10/31/2022 05:51, Tvrtko Ursulin wrote:
On 31/10/2022 10:09, Tvrtko Ursulin wrote:
On 28/10/2022 20:46, john.c.harri...@intel.com wrote:
From: John Harrison
The engine busyness stats has a worker function to do things like
64bit extend the 32bit hardware counters. The GuC's reset pr
On 3/3/2023 11:20, Ceraolo Spurio, Daniele wrote:
On 2/17/2023 3:47 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A failure to load the GuC is occasionally observed where the GuC log
actually showed that the GuC had loaded just fine. The implication
being that the load just took
On 3/15/2023 00:51, Greg KH wrote:
On Mon, Mar 13, 2023 at 07:22:11PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
Direction from hardware is that ring buffers should never be mapped
via the BAR on systems with LLC. There are too many caching pitfalls
due to the way BAR
On 3/15/2023 10:57, Greg KH wrote:
On Wed, Mar 15, 2023 at 10:07:53AM -0700, John Harrison wrote:
On 3/15/2023 00:51, Greg KH wrote:
On Mon, Mar 13, 2023 at 07:22:11PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
Direction from hardware is that ring buffers should never be
On 3/17/2023 05:58, Greg KH wrote:
On Thu, Mar 16, 2023 at 01:58:35PM -0700, John Harrison wrote:
On 3/15/2023 10:57, Greg KH wrote:
On Wed, Mar 15, 2023 at 10:07:53AM -0700, John Harrison wrote:
On 3/15/2023 00:51, Greg KH wrote:
On Mon, Mar 13, 2023 at 07:22:11PM -0700, john.c.harri
idle we already
skip the wait & reset entirely and that this reduced wait would still
likely be too long to use in resume paths, it's not worth adding support
for this reduced wait.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Cc: John Harrison
Cc: Rodrigo Vivi
---
drivers/g
atforms it is just easier to turn it off. The default on MTL is
also for GuC to own engine reset, with i915 only covering full-GT reset.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Andi Shyti
Cc: Mika Kuoppala
Cc: Gwan-gyeong Mun
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/intel
On 3/22/2023 13:59, Ceraolo Spurio, Daniele wrote:
On 3/22/2023 12:44 PM, John Harrison wrote:
On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
The WA states that we need to alert the GSC FW before doing a GSC
engine
reset and then wait for 200ms. The GuC owns engine reset, so on the
i915
On 3/22/2023 19:52, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Improvements to GuC load failure handling (rev3)
*URL:* https://patchwork.freedesktop.org/series/114168/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114168v3/i
On 3/22/2023 19:40, Patchwork wrote:
== Series Details ==
Series: Improvements to GuC load failure handling (rev3)
URL : https://patchwork.freedesktop.org/series/114168/
State : warning
== Summary ==
Error: dim checkpatch failed
b4df7f16c846 drm/i915/guc: Improve GuC load error reporting
2be
On 3/12/2023 12:56, Alexandre Oliva wrote:
If two or more suitable entries with the same filename are found in
__uc_fw_auto_select's fw_blobs, and that filename fails to load in the
first attempt and in the retry, when __uc_fw_auto_select is called for
the third time, the coincidence of strings w
On 3/26/2023 02:46, Alexandre Oliva wrote:
Hello, John,
On Mar 24, 2023, John Harrison wrote:
On 3/12/2023 12:56, Alexandre Oliva wrote:
If two or more suitable entries with the same filename are found in
__uc_fw_auto_select's fw_blobs, and that filename fails to load in the
first at
On 11/1/2022 08:27, Dixit, Ashutosh wrote:
On Mon, 31 Oct 2022 15:24:40 -0700, john.c.harri...@intel.com wrote:
From: John Harrison
Guc submission imposes new range limits on certain scheduling
parameters. The idempotent sections of the timeslice duration and
pre-emption timeout tests was
On 11/1/2022 02:58, Tvrtko Ursulin wrote:
On 31/10/2022 18:30, John Harrison wrote:
On 10/31/2022 05:51, Tvrtko Ursulin wrote:
On 31/10/2022 10:09, Tvrtko Ursulin wrote:
On 28/10/2022 20:46, john.c.harri...@intel.com wrote:
From: John Harrison
The engine busyness stats has a worker
raolo Spurio
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangch
On 11/2/2022 07:20, Tvrtko Ursulin wrote:
On 02/11/2022 12:12, Jani Nikula wrote:
On Tue, 01 Nov 2022, john.c.harri...@intel.com wrote:
From: John Harrison
At the end of each test, IGT does a drop caches call via sysfs with
sysfs?
Sorry, that was meant to say debugfs. I've also
On 11/3/2022 04:31, Tvrtko Ursulin wrote:
On 02/11/2022 19:21, john.c.harri...@intel.com wrote:
From: John Harrison
The engine busyness stats has a worker function to do things like
64bit extend the 32bit hardware counters. The GuC's reset prepare
function flushes out this worker functi
On 11/3/2022 02:38, Tvrtko Ursulin wrote:
On 03/11/2022 09:18, Tvrtko Ursulin wrote:
On 03/11/2022 01:33, John Harrison wrote:
On 11/2/2022 07:20, Tvrtko Ursulin wrote:
On 02/11/2022 12:12, Jani Nikula wrote:
On Tue, 01 Nov 2022, john.c.harri...@intel.com wrote:
From: John Harrison
At the
On 11/3/2022 02:18, Tvrtko Ursulin wrote:
On 03/11/2022 01:33, John Harrison wrote:
On 11/2/2022 07:20, Tvrtko Ursulin wrote:
On 02/11/2022 12:12, Jani Nikula wrote:
On Tue, 01 Nov 2022, john.c.harri...@intel.com wrote:
From: John Harrison
At the end of each test, IGT does a drop caches
On 11/3/2022 03:45, Jani Nikula wrote:
On Wed, 02 Nov 2022, John Harrison wrote:
On 11/2/2022 07:20, Tvrtko Ursulin wrote:
On 02/11/2022 12:12, Jani Nikula wrote:
On Tue, 01 Nov 2022, john.c.harri...@intel.com wrote:
From: John Harrison
At the end of each test, IGT does a drop caches
On 11/4/2022 03:01, Tvrtko Ursulin wrote:
On 03/11/2022 19:16, John Harrison wrote:
On 11/3/2022 02:38, Tvrtko Ursulin wrote:
On 03/11/2022 09:18, Tvrtko Ursulin wrote:
On 03/11/2022 01:33, John Harrison wrote:
On 11/2/2022 07:20, Tvrtko Ursulin wrote:
On 02/11/2022 12:12, Jani Nikula wrote
On 10/31/2022 18:26, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* drm/i915/guc: Remove excessive line feeds in state dumps
*URL:* https://patchwork.freedesktop.org/series/110343/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1
On 11/4/2022 11:53, Ceraolo Spurio, Daniele wrote:
On 11/2/2022 12:21 PM, john.c.harri...@intel.com wrote:
From: John Harrison
If a context has already been registered prior to first submission
then context init code was not being called. The noticeable effect of
that was the scheduling
On 11/2/2022 21:45, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Fix for two GuC issues (rev2)
*URL:* https://patchwork.freedesktop.org/series/110269/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v2/index.html
CI B
On 11/7/2022 08:17, Tvrtko Ursulin wrote:
On 07/11/2022 09:33, Tvrtko Ursulin wrote:
On 05/11/2022 01:03, Ceraolo Spurio, Daniele wrote:
On 11/4/2022 10:25 AM, john.c.harri...@intel.com wrote:
From: John Harrison
When trying to analyse bug reports from CI, customers, etc. it can be
On 11/7/2022 06:09, Tvrtko Ursulin wrote:
On 04/11/2022 17:45, John Harrison wrote:
On 11/4/2022 03:01, Tvrtko Ursulin wrote:
On 03/11/2022 19:16, John Harrison wrote:
On 11/3/2022 02:38, Tvrtko Ursulin wrote:
On 03/11/2022 09:18, Tvrtko Ursulin wrote:
On 03/11/2022 01:33, John Harrison
On 11/8/2022 01:08, Tvrtko Ursulin wrote:
On 07/11/2022 19:45, John Harrison wrote:
On 11/7/2022 06:09, Tvrtko Ursulin wrote:
On 04/11/2022 17:45, John Harrison wrote:
On 11/4/2022 03:01, Tvrtko Ursulin wrote:
On 03/11/2022 19:16, John Harrison wrote:
On 11/3/2022 02:38, Tvrtko Ursulin
ikula
Cc: John Harrison
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 26 +++
.../drm/i915/gt/intel_execlists_submission.c | 13 +++---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 +-
drivers/gpu/drm
On 11/8/2022 01:01, Tvrtko Ursulin wrote:
On 07/11/2022 19:14, John Harrison wrote:
On 11/7/2022 08:17, Tvrtko Ursulin wrote:
On 07/11/2022 09:33, Tvrtko Ursulin wrote:
On 05/11/2022 01:03, Ceraolo Spurio, Daniele wrote:
On 11/4/2022 10:25 AM, john.c.harri...@intel.com wrote:
From: John
On 11/9/2022 03:05, Tvrtko Ursulin wrote:
On 08/11/2022 20:15, John Harrison wrote:
On 11/8/2022 01:01, Tvrtko Ursulin wrote:
On 07/11/2022 19:14, John Harrison wrote:
On 11/7/2022 08:17, Tvrtko Ursulin wrote:
On 07/11/2022 09:33, Tvrtko Ursulin wrote:
On 05/11/2022 01:03, Ceraolo Spurio
On 11/9/2022 03:35, Tvrtko Ursulin wrote:
On 08/11/2022 19:37, John Harrison wrote:
On 11/8/2022 01:08, Tvrtko Ursulin wrote:
On 07/11/2022 19:45, John Harrison wrote:
On 11/7/2022 06:09, Tvrtko Ursulin wrote:
On 04/11/2022 17:45, John Harrison wrote:
On 11/4/2022 03:01, Tvrtko Ursulin
On 11/10/2022 02:33, Jani Nikula wrote:
On Wed, 09 Nov 2022, Michal Wajdeczko wrote:
Instead of merging this patch now, oriented on GT only, I would rather
wait until we discuss and plan solution for the all sub-components.
Once that's done (with agreement on naming and output) we can start
co
On 11/10/2022 01:43, Tvrtko Ursulin wrote:
On 09/11/2022 17:46, John Harrison wrote:
On 11/9/2022 03:05, Tvrtko Ursulin wrote:
On 08/11/2022 20:15, John Harrison wrote:
On 11/8/2022 01:01, Tvrtko Ursulin wrote:
On 07/11/2022 19:14, John Harrison wrote:
On 11/7/2022 08:17, Tvrtko Ursulin
On 11/18/2022 02:52, Jani Nikula wrote:
On Thu, 17 Nov 2022, john.c.harri...@intel.com wrote:
From: John Harrison
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug
On 11/22/2022 06:12, Jani Nikula wrote:
On Tue, 06 Sep 2022, Daniele Ceraolo Spurio
wrote:
From: John Harrison
There was a misunderstanding in how firmware file compatibility should
be managed within i915. This has been clarified as:
i915 must support all existing firmware releases
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