[Intel-gfx] [PATCH 4/8] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v12

nditional (Daniel) v12:fix up fb vs pipe size checking (Chris) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 1 - drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_fbdev.c | 174 +-- 3 files changed, 166 insertio

[Intel-gfx] [PATCH 2/8] drm/i915: get_plane_config for i9xx v13

S fbs (Kristian) pull out common bits (Jesse) v13: move fb obj alloc out to _init Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 63 1 file changed, 63 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 7/8] drm/i915: use current mode if the size matches the preferred mode

From: Kristian Høgsberg The BIOS may set a native mode that doesn't quite match the preferred mode timings. It should be ok to use however if it uses the same size, so try to avoid a mode set in that case. Signed-off-by: Kristian Høgsberg Signed-off-by: Jesse Barnes --- drivers/gp

[Intel-gfx] [PATCH 5/8] drm/i915: preserve SSC if previously set

Some machines may have a broken VBT or no VBT at all, but we still want to use SSC there. So check for it and keep it enabled if we see it already on. Based on an earlier fix from Kristian. Reported-by: Kristian Høgsberg Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c

Re: [Intel-gfx] [PATCH 8/8] drm/i915: remove early fb allocation dependency on CONFIG_FB v2

On Sat, 8 Mar 2014 11:33:15 +0100 Daniel Vetter wrote: > On Fri, Mar 07, 2014 at 08:57:55AM -0800, Jesse Barnes wrote: > > By stuffing the fb allocation into the crtc, we get mode set lifetime > > refcounting for free, but have to handle the initial pin & fence > > sligh

Re: [Intel-gfx] [PATCH 6/8] drm/i915: don't bother enabling swizzle bits on gen7+

On Sat, 8 Mar 2014 11:36:24 +0100 Daniel Vetter wrote: > On Fri, Mar 07, 2014 at 08:57:53AM -0800, Jesse Barnes wrote: > > As of IVB, the memory controller does internal swizzling already, so we > > shouldn't need to enable these. Based on an earlier fix from Kristian.

Re: [Intel-gfx] [RFC] Documentation requirements for drm/i915 feature work

n page updates. We need to be good about catching this on review for new stuff. For older stuff I think there was a bit of momentum awhile back, but it seems to have dissipated. We could try to extract it from kernel source somehow, but for user API stuff, I think we really want man pages in li

Re: [Intel-gfx] [RFC] Documentation requirements for drm/i915 feature work

On Fri, 14 Mar 2014 19:00:46 +0100 Daniel Vetter wrote: > On Fri, Mar 14, 2014 at 6:06 PM, Jesse Barnes > wrote: > >> 3) Documentating userspace ABIs like ioctls structures&flags, properties > >> and so on. > >> > >> I have no idea how to do 3

Re: [Intel-gfx] [RFC] Documentation requirements for drm/i915 feature work

On Fri, 14 Mar 2014 19:16:01 +0100 Daniel Vetter wrote: > On Fri, Mar 14, 2014 at 7:03 PM, Jesse Barnes > wrote: > > Yeah just saying a man page should be required as part of any new > > ioctl. > > Yeah I agree and long-term we'll get there. Otherwise I wouldn

Re: [Intel-gfx] [PATCH] drm/i915: Fix runtime pm inbalance due to reg I/O forcewake dance

t; > > That's what I meant. No delayed runtime_pm_put. > > Well I've figured we want to keep this ... have things changed > sufficiently meanwhile? I've lost a bit track in all that recent > shuffling ... Can we pull the forcewake bits out of the reg functions and

[Intel-gfx] [PATCH 1/4] drm/i915: preserve SSC if previously set v2

) Reported-by: Kristian Høgsberg Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h |2 ++ drivers/gpu/drm/i915/intel_display.c | 11 ++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 4/4] drm/i915: enable fastboot by default

Let them eat cake. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_params.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index a66ffb6..5f81047 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 3/4] drm/i915: use current mode if the size matches the preferred mode

From: Kristian Høgsberg The BIOS may set a native mode that doesn't quite match the preferred mode timings. It should be ok to use however if it uses the same size, so try to avoid a mode set in that case. Signed-off-by: Kristian Høgsberg Signed-off-by: Jesse Barnes --- drivers/gp

[Intel-gfx] [PATCH 2/4] drm/i915: don't bother enabling swizzle bits on gen7+ v2

As of IVB, the memory controller does internal swizzling already, so we shouldn't need to enable these. Based on an earlier fix from Kristian. v2: preserve swizzling if BIOS had it set (Daniel) Reported-by: Kristian Høgsberg Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_

Re: [Intel-gfx] [PATCH] drm/i915/vlv: no MCHBAR on VLV

Junxiao, can you add you reviewed-by to this patch? Thanks, Jesse On Mon, 3 Mar 2014 14:27:57 -0800 Jesse Barnes wrote: > So don't try to allocate and program it, we're only fooling ourselves. > > Reported-by: "Chang, Junxiao" > Signed-off-by: Jesse Barne

Re: [Intel-gfx] [PATCH 12/26] drm/i915: Page table helpers, and define renames

g the pd_mask. > > > + i915_pte_index(addr, pde_shift); > > + > > + return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); > > +} > > Otherwise the helpers look a useful improvement in readability. > -Chris > Can we use GTT_PAGE_SIZE here too? I'm worried the kernel PAGE_SIZE will change at some point and blow us up. At least in places where we're doing our own thing rather than using the x86 bits... -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Add a DRM property "psr"

Chromium for disabling PSR in cases where it doesn't work? Or to optimize power consumption when the kernel driver gets it wrong? Or just for debug? Seems potentially useful, just curious what motivated you guys. Thanks, -- Jesse Barnes, Intel Open Source Technology Center _

Re: [Intel-gfx] [PATCH 11/11] [v4] drm/i915/bdw: Ensure a context is loaded before RC6

imitive emission seems like it's going to keep power consumption in a terrible state on BDW for the forseeable future... moreover I guess this is something we need going back forever for RC6 stability, at least according to the hw team. So rather than blocking this, maybe we should commit it for all platforms! -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 11/11] [v4] drm/i915/bdw: Ensure a context is loaded before RC6

On Thu, 20 Mar 2014 10:30:32 -0700 Jesse Barnes wrote: > On Thu, 20 Mar 2014 14:42:32 +0100 > Daniel Vetter wrote: > > > On Wed, Mar 19, 2014 at 05:41:37PM -0700, Ben Widawsky wrote: > > > I can't say it's completely unexpected that this would be your respons

[Intel-gfx] [PATCH] drm/i915/vlv: use W_SYNC_SHIFT for interlaced modes on VLV

This makes HDMI testers happier on VLV platforms. It may be that we need it for any non-SVO platform, but I don't have any tests to back that up, so I'm leaving other pre-ILK platforms alone for now. Tested-by: "Clint Taylor " Signed-off-by: Jesse Barnes ---

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Program VSYNCSHIFT in a more consistent manner

intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) > + vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; > + else > + vsyncshift = adjusted_mode->crtc_hsync_start - > + adjusted_mode->crtc_htotal / 2; > } >

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Fix the interlace mode selection for gmch platforms

ited_color_range) Hooray for SDVO. I really hope no one tries to do that on VLV... (afaik it's unsupported but who knows the hw might work if someone solders such a board together). Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Make sure vsyncshift is positive

->gen > 3) Funky indeed. I wonder if we should congratulate the user if we detect this configuration. "Achievement unlocked: funky mode timings!". Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 2/3] drm/i915: correct BLC vs PWM enable/disable ordering

With the new checks in place, we can see we're doing things backwards, so fix them up per the spec. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gp

[Intel-gfx] [PATCH 1/3] drm/i915: add PWM and BLC assertion checks

To make sure we properly follow the enable/disable sequences. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c| 62 -- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_panel.c | 5 ++- 3 files changed, 65 insertions

[Intel-gfx] [PATCH 3/3] drm/i915/vlv: use min brightness from VBT

Going below the minimum value may affect the BLC_EN line, so try to use the VBT provided minimum where possible, otherwise use an experimentally derived value to prevent the panel from coming up. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h| 1 + drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH] drm/edid: Fill PAR in AVI infoframe based on CEA mode list

tions are > satisfied, PAR is NONE as per initialization. > > As a next step, create a property that would enable a user space app to set > aspect ratio. (will be pushed as a separate patch) > > Signed-off-by: Vandana Kannan > Cc: Jesse Barnes > Cc: Vijay Purushothaman >

Re: [Intel-gfx] [PATCH] drm/edid: Populate picture aspect ratio for CEA modes

nfoframe. > > > > v2: Ville's inputs incorporated. Added picture aspect ratio as part of > > edid_cea_modes instead of DRM_MODE > > > > Signed-off-by: Vandana Kannan > > Reviewed-by: Alex Deucher > > Reviewed-by: Ville Syrjälä Note this one is neede

Re: [Intel-gfx] [PATCH 3/3] drm/i915/vlv: use min brightness from VBT

On Mon, 31 Mar 2014 21:07:04 +0200 Daniel Vetter wrote: > On Mon, Mar 31, 2014 at 11:13:57AM -0700, Jesse Barnes wrote: > > Going below the minimum value may affect the BLC_EN line, so try to use > > the VBT provided minimum where possible, otherwise use an experimentally >

Re: [Intel-gfx] [PATCH 1/3] drm/i915: add PWM and BLC assertion checks

On Tue, 01 Apr 2014 10:19:29 +0300 Jani Nikula wrote: > On Mon, 31 Mar 2014, Jesse Barnes wrote: > > To make sure we properly follow the enable/disable sequences. > > > > Signed-off-by: Jesse Barnes > > --- > > driver

Re: [Intel-gfx] [PATCH 1/3] drm/i915: add PWM and BLC assertion checks

On Tue, 01 Apr 2014 12:27:43 +0300 Jani Nikula wrote: > On Tue, 01 Apr 2014, Jani Nikula wrote: > > On Mon, 31 Mar 2014, Jesse Barnes wrote: > >> To make sure we properly follow the enable/disable sequences. > >> > >> Signed-off-by: Jesse Barnes > >&

Re: [Intel-gfx] [PATCH 3/3] drm/i915/vlv: use min brightness from VBT

On Tue, 01 Apr 2014 11:08:13 +0300 Jani Nikula wrote: > On Mon, 31 Mar 2014, Jesse Barnes wrote: > > Going below the minimum value may affect the BLC_EN line, so try to use > > the VBT provided minimum where possible, otherwise use an experimentally > > derived value to p

Re: [Intel-gfx] [PATCH] drm/i915: Fix the computation of required fb size for pipe

gt; > > > > > commit d978ef14456a38034f6c0e94a794129501f89200 > > > Author: Jesse Barnes > > > Date: Fri Mar 7 08:57:51 2014 -0800 > > > > > > drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS > > > fbcon v12 > > > > > > is to

Re: [Intel-gfx] [PATCH] Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"

, Turbo freqs used on current machines matches. > --- I don't know what to do about this... I don't have a bunch of machines to test with, and the docs say different. But if you have feedback from the hw guys, I guess Acked-by: Jesse Barnes -- Jesse Barnes, I

[Intel-gfx] [PATCH 1/4] drm/i915/vlv: write the port field in the per-pipe DIP control reg

In case we end up bouncing these around between ports. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index b0413e1..ee892a4 100644 --- a

[Intel-gfx] [PATCH 3/4] drm/i915: enable HDMI mode on VLV when an HDMI sink is detected

Allows sending of the null packets for conformance. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 3b804fc..fb9839b 100644

[Intel-gfx] [PATCH 2/4] drm/i915/vlv: disable AVI infoframe emission when writing infoframes

We also do a disable later when we write a specific infoframe, but here we do it to prevent sending a stale one before updating the infoframes. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers

[Intel-gfx] [PATCH 4/4] drm/i915: move infoframe setting to after port enable

Needs to happen after clock is running or it doesn't behave correctly. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c

Re: [Intel-gfx] [PATCH 1/4] drm/i915/vlv: write the port field in the per-pipe DIP control reg

These all have a Tested-by: "Joon Jung " too. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Move DP M/N setup from update_pll to mode_set for gmch platforms

PE_B; > } > > + if (intel_crtc->config.has_dp_encoder) > + intel_dp_set_m_n(intel_crtc); > + > intel_set_pipe_timings(intel_crtc); > > /* pipesrc and dspsize control the size that is scaled from, Yeah I like it. Reviewed-by: Je

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Warn when DPIO read returns 0xffffffff

reg 0x%x == 0x%x\n", > + pipe_name(pipe), reg, val); > + > return val; > } > Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Provide a bit more info when pipestat bits are wrong

gt; + "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", > + pipe, enable_mask, status_mask)) > return; > > if ((pipestat & enable_mask) == 0) Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Fix framecount offset

IPE2(pipe, _PIPEA_FRMCOUNT_GM45) > > /* Cursor A & B regs */ > #define _CURACNTR (dev_priv->info.display_mmio_offset + 0x70080) Oh fun. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

> #include "i915_trace.h" > #include "intel_drv.h" > > +#define CACHELINE_BYTES 64 > + Are you sure it's 64 on every gen? It changes on the CPU side from time to time... I thought it might have changed over time on the GPU too but I haven't checked the s

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Move all ring resets before setting the HWS page

a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -34,6 +34,7 @@ struct intel_hw_status_page { > #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), > val) > > #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) > +#define I915_WRITE_MODE(ring, val) > I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) > > enum intel_ring_hangcheck_action { > HANGCHECK_IDLE = 0, Bad Chris, mixing a nice refactor and a nice fix in the same patch. I'll still give you a cookie though. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Preserve ring buffers objects across resume

it looks like this will still tear things down on suspend? Maybe it's all the refactoring making me miss it. :) -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Allow the module to load even if we fail to setup rings

otherwise, but not for KMS. > */ > if (!drm_core_check_feature(dev, DRIVER_MODESET)) > dev_priv->dri1.allow_batchbuffer = 1; > - return 0; > + return ret; > } > > void Will we still have some loud spewing into the log in this case? If so, then Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/4] drm/i915: move infoframe setting to after port enable

On Thu, 3 Apr 2014 17:19:56 +0200 Daniel Vetter wrote: > On Wed, Apr 02, 2014 at 10:08:54AM -0700, Jesse Barnes wrote: > > Needs to happen after clock is running or it doesn't behave correctly. > > > > Signed-off-by: Jesse Barnes > > --- > > dr

Re: [Intel-gfx] [PATCH 4/4] drm/i915: move infoframe setting to after port enable

On Thu, 3 Apr 2014 22:55:24 +0200 Daniel Vetter wrote: > On Thu, Apr 3, 2014 at 6:49 PM, Jesse Barnes wrote: > >> > static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, > >> > @@ -738,9 +736,13 @@ static void intel_enable_hdmi(struct int

[Intel-gfx] [PATCH] drm/i915: move infoframe setting to after pll enable v2

Needs to happen after clock is running or it doesn't behave correctly. v2: fix subject (Ville) make it clearer that this occurs in pre_enable (Paulo) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c | 18 -- 1 file changed, 16 insertions(+), 2 dele

[Intel-gfx] [PATCH] drm/i915: move infoframe setting to after pll enable v2

Needs to happen after clock is running or it doesn't behave correctly. v2: fix subject (Ville) make it clearer that this occurs in pre_enable (Paulo) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c | 18 -- 1 file changed, 16 insertions(+), 2 dele

[Intel-gfx] [PATCH 5/6] drm/i915/vlv: move DP enable after plane/pipe enable per latest spec

The spec changed the order awhile back to put the ports at the end again, but we never updated. Things seem to work ok either way, but apparently there are some failures fixed by the new order, so let's just go ahead and do it. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 3/6] drm/i915: warn when a vblank wait times out

This always indicates a bug somewhere. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6a6406f..c039f34 100644 --- a

[Intel-gfx] [PATCH 6/6] drm/i915/vlv: re-order TX lane reset per latest spec

This is supposed to fix some eDP PPS issues on some platforms. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 98cf24f..34d01be

[Intel-gfx] [PATCH 2/6] drm/i915: remove unnecessary delays in intel_dp_link_down

The reason for these is lost in the mists of time, and they don't seem to be necessary anymore, so drop them. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 1/6] drm/i915: use VBT to determine whether to enumerate the VGA port

Some platforms may not have it, and enumerating it is both confusing and time consuming due to the hotplug and DDC probing. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 4/6] drm/i915: don't set sink DPMS status on eDP

This only applies to external sinks. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7642415..df7cc11 100644 --- a/drivers/gpu/drm

Re: [Intel-gfx] [PATCH] drm/i915: move infoframe setting to after pll enable v2

On Sat, 5 Apr 2014 17:21:04 +0200 Daniel Vetter wrote: > On Fri, Apr 04, 2014 at 03:12:08PM -0700, Jesse Barnes wrote: > > Needs to happen after clock is running or it doesn't behave correctly. > > > > v2: fix subject (Ville) > > make it clearer that

[Intel-gfx] [PATCH] drm/i915: move infoframe setting to after pll enable v3

Needs to happen after clock is running or it doesn't behave correctly. v2: fix subject (Ville) make it clearer that this occurs in pre_enable (Paulo) misc bikesheds (Paulo) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c | 18 -- 1 file change

Re: [Intel-gfx] [PATCH 3/6] drm/i915: warn when a vblank wait times out

On Sat, 5 Apr 2014 17:22:40 +0200 Daniel Vetter wrote: > On Sat, Apr 05, 2014 at 07:29:22AM +0100, Chris Wilson wrote: > > On Fri, Apr 04, 2014 at 04:12:09PM -0700, Jesse Barnes wrote: > > > This always indicates a bug somewhere. > > > > We keep turning this off b

Re: [Intel-gfx] [PATCH 4/6] drm/i915: don't set sink DPMS status on eDP

On Mon, 07 Apr 2014 11:36:46 +0300 Jani Nikula wrote: > On Sat, 05 Apr 2014, Jesse Barnes wrote: > > This only applies to external sinks. > > [citation needed] > > eDP 1.3 has SET_POWER_CAPABLE (bit 7) in in DPCD > EDP_GENERAL_CAPABILITY_REGISTER_1 (register 0x702) w

Re: [Intel-gfx] [PATCH] drm/mm: Don't WARN if drm_mm_reserve_node

s > happens in intel_alloc_plane_obj in intel_display.c. > > Since no one else uses this we can savely remove the WARN without > repercursions. > > Reported-by: Ben Widawsky > Cc: Ben Widawsky > Cc: Jesse Barnes > Cc: Dave Airlie > Signed-off-by: Daniel Vetter > --- > dr

[Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset on resume

er domains looking for a match, then call a generic function which will warn. I'd prefer to just expose the specific domains directly for low level platform code like this. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c |4 ++-- drivers/gpu/drm/i915/intel_uncore.c

Re: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset on resume

On Fri, 11 Apr 2014 19:16:32 +0200 Daniel Vetter wrote: > On Fri, Apr 11, 2014 at 10:00:16AM -0700, Jesse Barnes wrote: > > This is a bit like the CMN reset de-assert we do in DPIO_CTL, except > > that it resets the whole common lane section of the PHY. This is > > requi

Re: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset on resume

On Fri, 11 Apr 2014 20:26:24 +0300 Ville Syrjälä wrote: > On Fri, Apr 11, 2014 at 10:00:16AM -0700, Jesse Barnes wrote: > > This is a bit like the CMN reset de-assert we do in DPIO_CTL, except > > that it resets the whole common lane section of the PHY. This is > > requi

Re: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset on resume

On Fri, 11 Apr 2014 21:10:21 +0300 Ville Syrjälä wrote: > On Fri, Apr 11, 2014 at 10:35:40AM -0700, Jesse Barnes wrote: > > On Fri, 11 Apr 2014 20:26:24 +0300 > > Ville Syrjälä wrote: > > > > > On Fri, Apr 11, 2014 at 10:00:16AM -0700, Jesse Barnes wrote: >

Re: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset on resume

On Fri, 11 Apr 2014 21:06:31 +0300 Ville Syrjälä wrote: > On Fri, Apr 11, 2014 at 10:34:19AM -0700, Jesse Barnes wrote: > > On Fri, 11 Apr 2014 19:16:32 +0200 > > Daniel Vetter wrote: > > > > > On Fri, Apr 11, 2014 at 10:00:16AM -0700, Jesse Barnes wrote: >

[Intel-gfx] [PATCH 2/2] drm/i915: remove misplaced panel wait in DP off code

We do this wait elsewhere, so drop it to speed things up a bit. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 728a5db..7642415 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH 1/2] drm/i915: remove unexplained vblank wait in the DP off code

I don't think this is necessary; at least it doesn't appear to be on my BYT. Dropping it speeds up our shutdown code a little, in some cases resulting in faster init times. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 3 --- 1 file changed, 3 deletions(-) di

[Intel-gfx] [PATCH] x86/early quirk: use gen6 stolen detection for VLV

We've always been able to use either method on VLV, but it appears more recent BIOSes only support the gen6 method, so switch over to that. References: https://bugs.freedesktop.org/show_bug.cgi?id=71370 Signed-off-by: Jesse Barnes --- arch/x86/kernel/early-quirks.c | 4 ++-- 1 file chang

[Intel-gfx] [PATCH] drm/i915: drop duplicate ggtt vma list add in setup_global_gtt

Preallocated, stolen objects will already be added to this list when we first create them. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_gem_gtt.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index

[Intel-gfx] BIOS fb wrapping

I split these out for clarity and ease of review. They seem to be working ok here now, and correctly taking the previous fb and using it. The memset patch makes plymouth look better on this machine (it doesn't flicker black near the end). I haven't tested this on as many configs as the old patch

[Intel-gfx] [PATCH 5/5] drm/i915: don't memset the fb buffer

It may be in use, let fbcon do it later if needed. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_fbdev.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index adf92dd..259f5ca 100644 --- a/drivers

[Intel-gfx] [PATCH 3/5] drm/i915: split fb allocation and initialization

If we use a stolen buffer, our probe callback shouldn't allocate a new buffer; we should re-use the one from the BIOS instead if possible. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_fbdev.c | 57 ++ 1 file changed, 45 insertions(+

[Intel-gfx] [PATCH 1/5] drm/i915: make pitch_for_width take a tiled arg

And move it up in the file for earlier usage. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

[Intel-gfx] [PATCH 4/5] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon

plit from plane_config readout and other display changes (Jesse) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c| 5 + drivers/gpu/drm/i915/i915_drv.h| 1 + drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_fbdev.c |

[Intel-gfx] [PATCH 2/5] drm/i915: retrieve current fb config into new plane_config structure at init

Read out the current plane configuration at init time into a new plane_config structure. This allows us to track any existing framebuffers attached to the plane and potentially re-use them in our fbdev code for a smooth handoff. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h

Re: [Intel-gfx] [PATCH 5/5] drm/i915: don't memset the fb buffer

On Wed, 13 Nov 2013 21:56:56 + Chris Wilson wrote: > On Wed, Nov 13, 2013 at 10:20:48AM -0800, Jesse Barnes wrote: > > It may be in use, let fbcon do it later if needed. > > Sadly we need to memset the stolen buffer in some circumstances, so we > need a bit more smarts.

Re: [Intel-gfx] [PATCH 1/5] drm/i915: make pitch_for_width take a tiled arg

On Wed, 13 Nov 2013 21:59:04 + Chris Wilson wrote: > On Wed, Nov 13, 2013 at 10:20:44AM -0800, Jesse Barnes wrote: > > And move it up in the file for earlier usage. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_display.c | 26

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon

On Wed, 13 Nov 2013 14:05:44 -0800 Bob Paauwe wrote: > On Wed, 13 Nov 2013 10:20:47 -0800 > Jesse Barnes wrote: > > > Retrieve current framebuffer config info from the regs and create an fb > > object for the buffer the BIOS or boot loader left us. This should > > a

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon

On Wed, 13 Nov 2013 22:07:26 + Chris Wilson wrote: > On Wed, Nov 13, 2013 at 10:20:47AM -0800, Jesse Barnes wrote: > > Retrieve current framebuffer config info from the regs and create an fb > > object for the buffer the BIOS or boot loader left us. This should >

Re: [Intel-gfx] [PATCH 2/5] drm/i915: retrieve current fb config into new plane_config structure at init

On Thu, 14 Nov 2013 15:06:59 + Chris Wilson wrote: > On Wed, Nov 13, 2013 at 10:20:45AM -0800, Jesse Barnes wrote: > > Read out the current plane configuration at init time into a new > > plane_config structure. This allows us to track any existing > > framebuffers atta

[Intel-gfx] [PATCH 1/5] drm/i915: make pitch_for_width take a tiled arg v2

And move it up in the file for earlier usage. v2: add pre-gen4 support as well (Chris) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 53 ++-- 1 file changed, 38 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 5/5] drm/i915: don't memset the fb buffer if preallocated

We want to preserve the BIOS/bootloader contents for later. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_fbdev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index 5ee5dc0..c7b1adf

[Intel-gfx] [PATCH 3/5] drm/i915: retrieve current fb config into new plane_config structure at init v2

get_plane_config works with shared fbs (Jesse) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/intel_display.c | 118 ++- drivers/gpu/drm/i915/intel_drv.h | 14 + 3 files changed, 133 insertions(+), 2

[Intel-gfx] [PATCH 4/5] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon

plit from plane_config readout and other display changes (Jesse) drop use_bios_fb option (Chris) update comments (Jesse) rework fbdev_init_bios for clarity (Jesse) drop fb obj ref under lock (Chris) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_drv.h | 2 + drivers

[Intel-gfx] [PATCH 2/5] drm/i915: split fb allocation and initialization v2

If we use a stolen buffer, our probe callback shouldn't allocate a new buffer; we should re-use the one from the BIOS instead if possible. v2: fix locking (Jesse) Reviewed-by: Chris Wilson Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_fbdev.c

[Intel-gfx] [PATCH 2/2] drm/i915/vlv: use parallel context restore when coming out of RC6

Setting this bit restores all ring contexts in parallel rather than serially. Matches current BWG recommendations. Tested-by: "Meng, Mengmeng" Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 +- 2 files changed, 2 insert

[Intel-gfx] [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV

ned-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 172efa0..5d3912a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH 3/5] drm/i915: retrieve current fb config into new plane_config structure at init v2

es, not the DRM fourcc > values. > Stale comment, I changed my mind on what to store here. Thanks for catching it. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Add VLV specific force wake routines.

On Thu, 14 Nov 2013 19:02:15 +0530 deepa...@intel.com wrote: > From: Deepak S > > Added media/render/common well VLV force wake routines to help > bring up the WELLS before access the register > - Refactor current vlv_forcewake get/put and added MEDIA or > RENDER specific Forcewake. > - Added

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Add VLV specific force wake routines.

ll arg, and another that adds the VLV support for the split? That would make it easier to review. Thanks, -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Prefer setting PTE cache age to 3

> default: > - pte |= HSW_WB_ELLC_LLC_AGE0; > + pte |= HSW_WB_ELLC_LLC_AGE3; > break; > } > Yeah I guess as long as userspace can override the default with MOCS, this is fine. Acked-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Te

Re: [Intel-gfx] [PATCH] drm/i915: Drop forcewake w/a for missed interrupts/seqno on Sandybridge

n the second workaround of forcing an UC read of the ACTHD before > reading back the seqno from the snooped HWS. Dropping the forcewake > should allow us to conserve a little power, not much as the GPU is meant > to be busy whilst we wait for it! > > Cc: Jesse Barnes > Signed-off-by:

Re: [Intel-gfx] [PATCH] drm/i915/vlv: Add VLV specific force wake routines.

ady pushed. Thanks, Jesse On Wed, 20 Nov 2013 16:33:22 + "S, Deepak" wrote: > Thanks Jesse, I wil split the patches and send it for review. > > Thanks > Deepak > > -----Original Message- > From: Jesse Barnes [mailto:jbar...@virtuousgeek.org] > Sent: Wednesda

Re: [Intel-gfx] [PATCH 2/5] drm/i915: retrieve current fb config into new plane_config structure at init

m the htotal/vtotal? But even in that case we just want the pipesrc. > > +struct intel_plane_config { > > + int pixel_format; /* DRM fourcc code */ > > The comment doesn't match how you do things in the code. Yeah, Bob mentioned that too, fixed. Does this look useful to

Re: [Intel-gfx] [PATCH 2/5] drm/i915: retrieve current fb config into new plane_config structure at init

On Sat, 23 Nov 2013 01:08:17 +0200 Ville Syrjälä wrote: > On Fri, Nov 22, 2013 at 01:55:35PM -0800, Jesse Barnes wrote: > > On Wed, 20 Nov 2013 15:10:39 +0200 > > Ville Syrjälä wrote: > > > > + case DISPPLANE_8BPP: > > > > + ret

Re: [Intel-gfx] [PATCH 2/5] drm/i915: retrieve current fb config into new plane_config structure at init

On Sat, 23 Nov 2013 01:26:34 +0200 Ville Syrjälä wrote: > On Fri, Nov 22, 2013 at 03:21:08PM -0800, Jesse Barnes wrote: > > On Sat, 23 Nov 2013 01:08:17 +0200 > > Ville Syrjälä wrote: > > > > > On Fri, Nov 22, 2013 at 01:55:35PM -0800, Jesse Barnes wrote: > &

Re: [Intel-gfx] [PATCH 2/3] drm/i915/vlv: Valleyview support for forcewake Individual power wells.

el can drop it. I'd have structured the force wake callbacks a little differently (still used the vfunc then split the routines into separate _locked variants for each of render and media), but that's just cosmetic. So: Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Enabling DebugFS for valleyview forcewake counts

ev_priv->pipe_crc[pipe]; > - u32 val; > + u32 val = 0; > int ret; > > if (pipe_crc->source == source) Spurious warning fix? Otherwise looks fine. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___

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