NTEXT_PARAM_BAN_PERIOD 0x1
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
+#define I915_CONTEXT_PARAM_HW_ID 0x4
__u64 value;
};
Patch looks good to me
Reviewed-by: Deepak S
___
Intel-gfx
DPIO_PHY_STATUS);
+ unsigned int mask;
+
+ mask = status & DPLL_PORTD_READY_MASK;
+
+ if (mask == 0xf)
+ mask = 0x0;
+ else
+ dev_priv->chv_phy_control |=
+ PHY_CH_POWER_DOWN_OVR
this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Patch looks fine. It does what it says. One Q, why only for port B? Port
C is also in same common lane right?
Reviewed-by: Deepak S
Signed-off-by: Ville Syrjälä
---
drive
pll_enabled) {
vlv_force_pll_off(dev, pipe);
+
+ if (release_cl_override)
+ chv_phy_powergate_ch(dev_priv, phy, ch, false);
+ }
}
static enum pipe
Change looks fine
Reviewed-by: Deepak S
v_priv, pipe, CHV_CMN_DW28, tmp);
if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
Changes looks fine as per Bspec.
Reviewed-by: Deepak S
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
*/
+ tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
+ tmp |= DPIO_CL2_LDOFUSE_PWRENB;
+ vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
}
Do we need to turn off CL2 each time we enable dpio cmn power wells?
btw, changes looks fin
On 08/17/2015 05:15 PM, Ville Syrjälä wrote:
On Mon, Aug 17, 2015 at 07:49:41AM +0530, Deepak wrote:
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
When fractional m2 divider isn't used on CHV the fractional part
is ignore by the hardware. Despite
On 08/17/2015 05:23 PM, Ville Syrjälä wrote:
On Mon, Aug 17, 2015 at 09:46:01AM +0530, Deepak wrote:
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Move the CHV clock buffer disable from chv_disable_pll() to the new
encoder .post_pll_disable() hook. This
hin same FB GTT offset
Reviewed-by: Deepak S
Signed-off-by: Chris Wilson
Cc: "Goel, Akash"
Cc: Daniel Vetter
Cc: Jesse Barnes
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/intel_fbdev.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/
/* Set the upar bit */
@@ -1855,6 +1865,9 @@ static void chv_hdmi_pre_enable(struct intel_encoder
*encoder)
DPIO_TX1_STAGGER_MULT(7) |
DPIO_TX2_STAGGER_MULT(5));
+ /* Deassert data lane reset */
+ chv_data_lane_soft_reset(encoder, f
On 07/09/2015 02:16 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Add some checks that the state of the DPIO lanes is more or less what we
expect based on the overrides.
The hardware only provides two bits per channel indicating whether all
or some of the lanes are powered dow
ower gating DPIO PHY%d CH%d lanes 0x%x
(PHY_CONTROL=0x%08x)\n",
phy, ch, mask, dev_priv->chv_phy_control);
+ assert_chv_phy_status(dev_priv);
+
Patch looks fine with assertion at right places
Reviewed-by: Deepak S
assert_chv_phy_powergate(dev_priv,
On 08/27/2015 04:32 PM, Ville Syrjälä wrote:
On Thu, Aug 27, 2015 at 10:06:09AM +0530, Deepak wrote:
On 07/09/2015 02:16 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Add some checks that the state of the DPIO lanes is more or less what we
expect based on the overrides
we add a Log to indicate what BIOS is configuring? I think it helps in
debugging?
Change looks fine.
Reviewed-by: Deepak S
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 5 -
drivers/gpu/drm/i915/intel_hdmi.c | 5 -
2 files changed, 10 deletions(-)
diff --git a/
trol |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
+
+ dev_priv->chv_phy_assert[DPIO_PHY1] = false;
+ } else {
+ dev_priv->chv_phy_assert[DPIO_PHY1] = true;
}
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
Change looks
repo [3] where it's
sitting on a few other patches, including my earlier DPLL cleanup
series [4]. However there should be no real dependency on this other
stuff apart from the already mentioned DP pipe config patches (which are
also included in the branch).
Deepak, perchance you would be
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
When fractional m2 divider isn't used on CHV the fractional part
is ignore by the hardware. Despite that, program the fractional
value (0 in this case) to the hardware register just to keep
things a bit more cons
te(dev_priv, pipe, VLV_TX_DW3(ch), val);
-
- vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
- vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
- (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
-#endif
/* Start swing calculation */
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Move the CHV clock buffer disable from chv_disable_pll() to the new
encoder .post_pll_disable() hook. This is more symmetric since the
clock buffer enable happens from the .pre_pll_enable() hook.
We'll have more
struct intel_crtc_state *pipe_config)
{
@@ -15049,8 +15029,6 @@ void intel_modeset_init(struct drm_device *dev)
}
}
- intel_init_dpio(dev);
-
intel_shared_dpll_init(dev);
/* Just disable it once at startup */
L
ock);
} else if (IS_VALLEYVIEW(dev)) {
mutex_lock(&power_domains->lock);
vlv_cmnlane_wa(dev_priv);
Looks fine to me :)
Reviewed-by: Deepak S
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.fr
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
With DPIO powergating active on CHV, we can't even access the DPIO PLL
registers until the lane power state overrides have been enabled. That
will happen from the encoder .pre_pll_enable() hook, so move
chv_prepa
fig);
- else
+ } else {
+ vlv_prepare_pll(intel_crtc, intel_crtc->config);
vlv_enable_pll(intel_crtc, intel_crtc->config);
+ }
}
for_each_encoder_on_crtc(dev, crtc, encoder)
Looks
O_PHY1;
+ default:
+ BUG();
+ }
+}
+
Looks fine here is my r-b tag
Reviewed-by: Deepak S
+static inline enum dpio_channel
vlv_pipe_to_channel(enum pipe pipe)
{
switch (pipe) {
___
Intel-gfx mailing list
Int
From: Deepak S
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This reverts commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44
Author:
From: Deepak S
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This reverts commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44
Author:
On 12/08/16 11:53 AM, Chris Wilson wrote:
On Fri, Aug 12, 2016 at 02:12:42PM +0800, kbuild test robot wrote:
Hi Deepak,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc1 next-20160811]
[if your patch is applied to the wrong git tree, please drop us a note
From: Deepak S
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This is not a 1:1 revert of the commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
You can refer to commit 5b5929cbe3f
On 12/08/16 1:04 PM, Jani Nikula wrote:
On Fri, 12 Aug 2016, deepa...@linux.intel.com wrote:
From: Deepak S
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
IOW, this patch will
On 20/08/16 10:39 AM, Sagar Arun Kamble wrote:
Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is l
For vmwgfx cairo surface creation fails due to stride mismatch, add a
igt_require_f() for surface.
v2: Check for surface creation failure.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 0248637c..0485708b
Add DRIVER_VMWGFX to represent vmwgfx device for running igt tests.
v2: Don't remove second virtio_gpu
Signed-off-by: Deepak Rawat
---
lib/drmtest.c | 8
lib/drmtest.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index fee9d33a..9d0
vmwgfx does not support GEM interface so calling gem_close on vmwgfx
results in error.
v2: Use drmIoctl with error when ioctl() failed.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 5 -
lib/igt_kms.c | 13 +
lib/igt_kms.h | 1 +
3 files changed, 18 insertions(+), 1
gem_set_domain() is gem specific and not needed for dumb buffers.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 0485708b..74a4b501 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
Some simple test cases to use FB_DAMAGE_CLIPS plane property.
Signed-off-by: Deepak Rawat
---
lib/igt_kms.c | 1 +
lib/igt_kms.h | 1 +
tests/kms_atomic.c | 260 +
3 files changed, 262 insertions(+)
diff --git a/lib/igt_kms.c b/lib
vmwgfx doesn't support fb modifier so skip igt_require_fb_modifiers()
when modifier are not passed.
Signed-off-by: Deepak Rawat
---
lib/ioctl_wrappers.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 0929c43f..3a1
Call kernel selftest module test-drm_damage_helper from igt.
Signed-off-by: Deepak Rawat
---
tests/Makefile.sources | 1 +
tests/drm_plane_damage.c | 10 ++
2 files changed, 11 insertions(+)
create mode 100644 tests/drm_plane_damage.c
diff --git a/tests/Makefile.sources b/tests
Selftest for drm damage helper iterator functions.
Cc: ville.syrj...@linux.intel.com
Cc: Daniel Vetter
Cc: Pekka Paalanen
Cc: Daniel Stone
Cc: intel-gfx@lists.freedesktop.org
Cc: igt-...@lists.freedesktop.org
Cc: petri.latv...@intel.com
Cc: ch...@chris-wilson.co.uk
Signed-off-by: Deepak Rawat
Add DRIVER_VMWGFX to represent vmwgfx device for running igt tests.
v2: Don't remove second virtio_gpu
Signed-off-by: Deepak Rawat
---
lib/drmtest.c | 8
lib/drmtest.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index fee9d33a..9d0
vmwgfx doesn't support fb modifier so skip igt_require_fb_modifiers()
when modifier are not passed.
Signed-off-by: Deepak Rawat
---
lib/ioctl_wrappers.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 0929c43f..3a1
For vmwgfx cairo surface creation fails due to stride mismatch, add a
igt_require_f() for surface.
v2: Check for surface creation failure.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 335ece69..1bb6d324
vmwgfx does not support GEM interface so calling gem_close on vmwgfx
results in error.
v2: Use drmIoctl with error when ioctl() failed.
v3: Seperate ioctl wrapper.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 5 -
lib/igt_kms.c | 22 ++
lib/igt_kms.h | 1 +
3
Some simple test cases to use FB_DAMAGE_CLIPS plane property.
Cc: ville.syrj...@linux.intel.com
Cc: Daniel Vetter
Cc: Pekka Paalanen
Cc: Daniel Stone
Signed-off-by: Deepak Rawat
---
lib/igt_kms.c | 1 +
lib/igt_kms.h | 1 +
tests/kms_atomic.c | 260
Call kernel selftest module test-drm_damage_helper from igt.
v2:
- Add test alphabetically.
- Add test to meson build.
Cc: ville.syrj...@linux.intel.com
Cc: Daniel Vetter
Cc: Pekka Paalanen
Cc: Daniel Stone
Signed-off-by: Deepak Rawat
---
tests/Makefile.sources| 1 +
tests
For vmwgfx cairo surface creation fails due to stride mismatch, add a
igt_require_f() for surface.
v2: Check for surface creation failure.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 335ece69..1bb6d324
vmwgfx does not support GEM interface so calling gem_close on vmwgfx
results in error.
v2: Use drmIoctl with error when ioctl() failed.
v3: Seperate ioctl wrapper.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 5 -
lib/igt_kms.c | 22 ++
lib/igt_kms.h | 1 +
3
Call kernel selftest module test-drm_modeset for testing KMS.
v2:
- Add test alphabetically.
- Add test to meson build.
v3: Rename to kms_selftest.
Signed-off-by: Deepak Rawat
---
tests/Makefile.sources| 1 +
tests/igt_command_line.sh | 2 +-
tests/kms_selftest.c | 10
kms_addfb(), remove the modifier flag iff the
driver doesn't support modifiers and the modifer is 0
* Don't modify the flag in kms_addfb().
Signed-off-by: Deepak Rawat
Signed-off-by: Leo Li
---
lib/igt_fb.c | 7 +--
lib/ioctl_wrappers.c | 24 +++-
lib/i
Some simple test cases to use FB_DAMAGE_CLIPS plane property.
Signed-off-by: Deepak Rawat
---
lib/igt_kms.c | 1 +
lib/igt_kms.h | 1 +
tests/kms_atomic.c | 260 +
3 files changed, 262 insertions(+)
diff --git a/lib/igt_kms.c b/lib
Cairo surface creation will fail if stride of provided buffer is not
same as expected by cairo. This fails for vmwgfx odd length framebuffer
as in vmwgfx stride is always width * bpp.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib
For a Xorg bug vmwgfx has a kernel workaround which reset the value of
mode::type. This will cause crtc state not to match what is expected.
Signed-off-by: Deepak Rawat
---
tests/kms_atomic.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tests/kms_atomic.c b/tests
specific tests in
future.
Thanks,
Deepak
Deepak Rawat (5):
lib/igt_vmwgfx: Add vmwgfx device
lib/igt_fb: Call dumb_destroy ioctl in case of dumb buffers
tests/kms: Don't check crtc state for vmwgfx legacy set_crtc
lib/igt_fb: Check for stride before creating cairo surface
tests/kms_a
Add DRIVER_VMWGFX to represent vmwgfx device for running igt tests.
Signed-off-by: Deepak Rawat
---
lib/drmtest.c | 9 -
lib/drmtest.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index bfa2e0f0..563d5b8b 100644
--- a/lib
vmwgfx does not support GEM interface so calling gem_close on vmwgfx
results in error. Call dumb destroy IOCTL in case have dumb buffer.
Signed-off-by: Deepak Rawat
---
lib/igt_fb.c | 5 -
lib/igt_kms.c | 15 +++
lib/igt_kms.h | 1 +
3 files changed, 20 insertions(+), 1
Some simple test cases to use FB_DAMAGE_CLIPS plane property.
Signed-off-by: Deepak Rawat
Cc: dri-de...@lists.freedesktop.org
Cc: Daniel Vetter
Cc: Lukasz Spintzyk
Cc: Rob Clark
Cc: Daniel Stone
Cc: Noralf Trønnes
Cc: Dave Airlie
---
lib/igt_kms.c | 1 +
lib/igt_kms.h
For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.
v2: Moving the comment to intel_dsi.h(Jani)
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Yetunde Adebisi
Signed-off-by: Deepak M
---
drivers/gpu
Adebisi
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 17 +++-
drivers/gpu/drm/i915/intel_dsi.h | 4 +
drivers/gpu/drm/i915/intel_dsi_cabc.c | 179
Mailbox 5 is BIOS to Driver Notification mailbox is intended
to support BIOS to Driver event notification or data storage
for BIOS to Driver data synchronization purpose. Mailbox 5 is
the extension of mailbox 3.
Cc: Jani Nikula
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_drv.h
v3: rebase
Cc: Jani Nikula
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/intel_opregion.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index e362a30..64efedf 100644
--- a/drivers/gpu/drm
: Deepak M
---
drivers/gpu/drm/i915/intel_bios.c | 6 +++
drivers/gpu/drm/i915/intel_bios.h | 1 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 60 ++
3 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915
.
Cc: Jani Nikula
Signed-off-by: vkorjani
Signed-off-by: Deepak M
---
Addressed most of the minor comments in this version,
except the one where Jani had suggested to change the
logic in the goto_next_sequence(), Thought of handling
this as a new patch after this series.
http
memory unmap in intel_opregion_fini
-removed the new file created for opregion macro`s
Cc: Jani Nikula
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/intel_opregion.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915
The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.
v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
Cc: Jani Nikula
Signed-off-by: Deepak M
Adding a argument to the gpio read/write functions
which accepts the block name.
v2: rebase
v3: rebase
Cc: Jani Nikula
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_drv.h| 5 +++--
drivers/gpu/drm/i915/i915_reg.h| 5 +
drivers/gpu/drm/i915
comments.
Deepak M (8):
drm/i915: Updating asle structure with new fields
drm/i915: Add Intel opregion mailbox 5 structure
drm/i915: Do opregion VBT validation during opregion setup
drm/i915: Add debug entry to get the opregion VBT blob
drm/i915: Parsing VBT if size of VBT exceeds 6KB
drm/i915
VBT offset.
Cc: Jani Nikula
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_debugfs.c | 29 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 1 +
drivers/gpu/drm/i915/intel_opregion.c | 3 +++
4 files changed, 34
Calling the validate_vbt before assiging the opregion vbt blob.
Size of the VBT blob cant be more than 6KB when VBT is present
in mailbox 4.
Cc: Jani Nikula
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_bios.c | 43
From: Gaurav K Singh
After sending SHUTDOWN or TURN ON packet,check the DPI
FIFO empty status.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the
correct value here.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd2699
Additional clock value divider should use the ceil
value of the calulation to get the correct divider value.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, December 4, 2015 3:20 PM
> To: Deepak, M
> Cc: intel-gfx@lists.freedesktop.org; Gaurav K Singh
>
> Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add DPI FIFO empty s
From: Gaurav K Singh
Before sending TURN ON packet,check the DPI
FIFO empty status.
v2: Change in commit message
Checking for FIFO empty only during TURN ON packet.
Signed-off-by: Gaurav K Singh
Signed-off-by: Deepak M
---
Got to know about the patch where they are removing this
DPI
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Friday, December 4, 2015 9:52 PM
> To: Ville Syrjälä
> Cc: Deepak, M ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915:
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, December 4, 2015 5:22 PM
> To: Deepak, M
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use the ceil value for the
> additiona
From: Gaurav K Singh
Before sending TURN ON packet,check the DPI
FIFO empty status.
v2: Change in commit message
Checking for FIFO empty only during TURN ON packet.
v3: Adding a new function for DPI FIFO empty check
Signed-off-by: Gaurav K Singh
Signed-off-by: Deepak M
---
drivers/gpu
For broxton dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the other platforms, hence
setting the same in this patch.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_dsi.c | 16 +---
2 files changed, 17
Pipe is assigned based on the port, but it should be
based on current crtc. Correcting the same in this patch.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/intel_dsi.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915
Pipe is assigned based on the port, but it should be
based on current crtc. Correcting the same in this patch.
v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel)
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_reg.h | 4 +---
drivers/gpu/drm/i915/intel_dsi.c | 15 +++
2 files
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Wednesday, December 9, 2015 1:50 PM
> To: Deepak, M
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [BXT MIPI PATCH 2/2] drm/i915: dual
memory unmap in intel_opregion_fini
-removed the new file created for opregion macro`s
v4: Moving the vbt assignment after the opregion fields are assigned
Cc: Mika Kahola
Cc: Jani Nikula
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/intel_opregion.c | 47
Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_dsi.c | 17 +
2 files changed, 15 insertions
The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_reg.h | 104 +--
drivers/gpu/drm/i915/intel_dsi_pll.c
The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.
v2: Fixing compilation warning.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_reg.h | 104
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Thursday, February 4, 2016 6:29 PM
> To: Deepak, M ; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Thursday, February 4, 2016 7:28 PM
> To: Deepak, M ; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider
> form B0 stepping o
The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.
v2: Fixing compilation warning.
v3: Retained the old Macros (Jani)
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_reg.h | 96
From: Yogesh Mohan Marimuthu
The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.
Cc: Jani Nikula
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915
From: Uma Shankar
Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.
Cc: Jani Nikula
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 46 ++
1 file changed, 46 insertions(+)
diff --git a/drivers/g
- don't return null on errors
v4 by Deepak
- rebase
- prefixed the VLV_ to all the GPIO macros
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h| 6 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 606 ++---
2 files ch
-off-by: Deepak M
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 48 ++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index c6e18fe..db8e210 100644
--- a/drivers/gpu/drm/i915
Currently there are few pair of functions which
are called during the panel enable/disable sequence.
To improve the granularity, adding few more wrapper
functions so that the functions are more specific
on what they are doing.
Cc: Jani Nikula
Signed-off-by: Deepak M
Signed-off-by: Gaurav K
> -Original Message-
> From: Nikula, Jani
> Sent: Friday, February 19, 2016 6:51 PM
> To: Deepak, M ; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M
> Subject: Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio
> sequence support and gpio table
>
- don't return null on errors
v4 by Deepak
- rebase
- prefixed the VLV_ to all the GPIO macros
v5 by deepak
- readded the checks which were removed in the
earlier patchset (Jani)
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h| 6 +
dr
Currently for executing the i2c MIPI sequence, we are
relaying on the i2c bus bunmber which is specified in the
VBT.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_dma.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/intel_acpi.c | 49
This patch reads the i2c bus number from the _CRS table of the display module
of the ACPI, which will be updated by the BIOS with the i2c info which is used
for this module.
> -Original Message-
> From: Deepak, M
> Sent: Friday, February 19, 2016 7:26 PM
> T
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, February 19, 2016 7:38 PM
> To: Deepak, M
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Get the i2c bus number from the
> ACPI
>
Marimuthu
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_reg.h| 20 ++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 107 ++---
2 files changed, 102 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
From: Uma Shankar
Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.
v2 by Deepak
- Added the GPIO table got BXT.
- Added gpio_free
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Uma Shankar
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915
: Jani Nikula
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 123 +++--
1 file changed, 98 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/i915
- don't return null on errors
v4 by Deepak
- rebase
- prefixed the VLV_ to all the GPIO macros
v5 by deepak
- readded the checks which were removed in the
earlier patchset (Jani)
Cc: Ville Syrjälä
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_
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