On 03/23/2017 10:23 AM, Jani Nikula wrote:
On Thu, 23 Mar 2017, Clint Taylor wrote:
On 03/23/2017 05:30 AM, Jani Nikula wrote:
On Thu, 23 Mar 2017, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
signal
On 03/24/2017 04:25 AM, Jani Nikula wrote:
On Thu, 23 Mar 2017, Clint Taylor wrote:
I would prefer a solution for B (rules for M/N), but the code doesn't
appear to be broken and I don't believe we should "Fix" something that
is working. The device also works by changing th
o loss in precision.
The DP spec even mentions sources making choices that "allow for static
and relatively small Mvid and Nvid values", thus reducing the link M/N
regardless of the sink in question seems justified.
Everything here is based on the work and information gathered by Cli
On 01/18/2017 01:52 AM, Chris Wilson wrote:
On Tue, Jan 17, 2017 at 04:37:28PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
The .disable_display parameter was causing a fatal crash when fbdev was
dereferenced during driver init.
The other guards are within intel_fbdev.c, it
);
+ intel_ddi_init(dev_priv, PORT_TC3);
+ intel_ddi_init(dev_priv, PORT_TC4);
Reviewed-by: Clint Taylor
-Clint
} else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
DDC pin mapping for DGFX cards uses direct VBT pin mapping
Cc: Lucas De Marchi
Cc: Matt Roper
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_bios.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers
Add the support macros to define/extract bits as 16bits.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg_defs.h | 49
1 file changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
b/drivers/gpu/drm/i915/i915_reg_defs.h
index
Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to
594000MHz modes. Add 16 Bit mask operators to support C20 phy
programming.
BSPEC: 64568
Cc: Imre Deak
Cc: Mika Kahola
Cc: Radhakrishna Sripada
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Clint Taylor (2):
drm/i915: Add
Use algorithm to generate HDMI C20 PLL clock frequencies.
BSPEC: 64568
Cc: Radhakrishna Sripada
Cc: Mika Kahola
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 89 +--
.../gpu/drm/i915/display
Use algorithm to generate HDMI C20 PLL clock frequencies.
i
v2: checkpatch fixes
BSPEC: 64568
Cc: Radhakrishna Sripada
Cc: Mika Kahola
Cc: Anusha Srivatsa
Reviewed-by: Gustavo Sousa
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 89
Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to 594000MHz
modes. Add 16 Bit mask operators to support C20 phy programming.
v2: checkpatch fixes
BSPEC: 64568
Cc: Imre Deak
Cc: Mika Kahola
Cc: Radhakrishna Sripada
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Clint Taylor (2
Add the support macros to define/extract bits as 16bits.
v2: checkpatch fixes
Reviewed-by: Gustavo Sousa
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg_defs.h | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
From: "Taylor, Clinton A"
Use BSPEC values for the Audio Keep alive M and N values as included in
the cdclk BSPEC pages for display > 13
BSPEC: 54034, 55409
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Taylor, Clinton A
---
drivers/gpu/drm/i915/display/intel_audio.c | 2
BSPEC has updated the cdclk audio keepalives AUD_TS_CDCLK_M value to 60
for all supported platforms and refclks.
BSPEC: 54034
BSPEC: 55409
BSPEC: 65243
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_audio.c | 6 +-
1
On 06/05/2014 02:26 AM, Daniel Vetter wrote:
On Wed, Jun 04, 2014 at 03:29:41PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Remove OUI read function from the lower half interrupt handler. Upon
closing the eDP panel lid an HPD interrupt is generated. The lower half
handler
On 06/06/2014 02:41 AM, Jani Nikula wrote:
On Thu, 05 Jun 2014, Daniel Vetter wrote:
On Wed, Jun 04, 2014 at 03:29:41PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Remove OUI read function from the lower half interrupt handler. Upon
closing the eDP panel lid an HPD interrupt
On 04/09/2015 01:20 PM, Ville Syrjälä wrote:
On Thu, Apr 09, 2015 at 10:17:05AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Latest version of the "CHV DPIO programming notes" no longer requires writes
to TX DW 11 to fix a +2UI interpair skew issue. The current code
On 12/03/2014 01:01 PM, Ville Syrjälä wrote:
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Added PIPE C register support for CHV audio programming.
nak. The offset between the pipes looks constant so it should work
just fine with _PIPE
On 12/04/2014 12:41 AM, Jani Nikula wrote:
On Wed, 03 Dec 2014, Clint Taylor wrote:
On 12/03/2014 01:01 PM, Ville Syrjälä wrote:
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Added PIPE C register support for CHV audio programming.
nak
On 12/04/2014 11:08 AM, Clint Taylor wrote:
On 12/04/2014 12:41 AM, Jani Nikula wrote:
On Wed, 03 Dec 2014, Clint Taylor wrote:
On 12/03/2014 01:01 PM, Ville Syrjälä wrote:
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com
wrote:
From: Clint Taylor
Added PIPE C register
On 12/05/2014 05:23 AM, Imre Deak wrote:
On Fri, 2014-12-05 at 13:57 +0200, Jani Nikula wrote:
On Fri, 05 Dec 2014, Imre Deak wrote:
On Fri, 2014-12-05 at 10:37 +0200, Jani Nikula wrote:
On Fri, 05 Dec 2014, Clint Taylor wrote:
On 12/04/2014 11:08 AM, Clint Taylor wrote:
On 12/04/2014 12
On 07/02/2014 01:35 AM, Jani Nikula wrote:
From: Clint Taylor
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the conn
On 07/02/2014 07:40 AM, Paulo Zanoni wrote:
2014-07-02 5:35 GMT-03:00 Jani Nikula :
From: Clint Taylor
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timi
On 07/04/2014 05:26 AM, Paulo Zanoni wrote:
2014-07-03 19:07 GMT-03:00 Clint Taylor :
On 07/02/2014 07:40 AM, Paulo Zanoni wrote:
2014-07-02 5:35 GMT-03:00 Jani Nikula :
From: Clint Taylor
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down dur
On 08/11/2014 11:59 PM, Daniel Vetter wrote:
On Tue, Aug 12, 2014 at 07:39:24AM +0100, Chris Wilson wrote:
On Mon, Aug 11, 2014 at 03:33:02PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Intel HDMI does not correctly configure pixel replicated HDMI modes
480i and 576i. Remove
On 08/12/2014 07:11 AM, Jani Nikula wrote:
This series adds support for backlight class sysfs bl_power attribute
for eDP panels, which allows switching the backlight on/off. This is
done using the eDP panel power control as a sub-state of everything else
being enabled. Patch 4 also makes 0 bright
(IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
+IS_VALLEYVIEW(dev_priv))
return 128 * 1024;
else if (INTEL_INFO(dev_priv)->gen >= 4)
return 4 * 1024;
Fairly straight forward now that we know VLV and CHV require th
f this review the else clause is setting PFI_CREDIT
to 15 when the BPSEC states that the default of 8 should be used when
cdclk/czclk < 1. According to the original patch, 15 is the optimal
value as stated by another driver team.
Reviewed-by: Clint Taylor
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Turns out the VLV/CHV system agent doesn't understand memory
latencies, so trying to rely on the PND deadline mechanism is not
going to fly especially when DDR DVFS is enabled. Currently we try to
avoid the problem
On 06/26/2015 12:48 PM, Ville Syrjälä wrote:
On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote:
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Turns out the VLV/CHV system agent doesn't understand memory
latencies, so trying to rely on th
pdate_wm_post;
unsigned disabled_planes;
/* Sleepable operations to perform after commit */
Reviewed-by: Clint Taylor
Tested-by: Clint Taylor
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STPM);
} else {
return;
}
Reviewed-by: Clint Taylor
Tested-by: Clint Taylor
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\n",
+ pipe_name(pipe), wm->pipe[pipe].primary,
wm->pipe[pipe].cursor,
+ wm->pipe[pipe].sprite[0],
wm->pipe[pipe].sprite[1]);
+
+ DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d
c
struct vlv_wm_state *wm_state = &crtc->wm_state;
enum pipe pipe = crtc->pipe;
Reviewed-by: Clint Taylor
Tested-by: Clint Taylor
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_size(intel_crtc);
return;
+ }
if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
@@ -1388,6 +1540,9 @@ static void vlv_update_wm(struct drm_crtc *crtc)
intel_wait_for_vblank(dev, pipe);
else if (IS_VALLEYVIEW(dev))
+ num_levels = 1;
+ else
+ num_levels = ilk_wm_max_level(dev) + 1;
+
if (len >= sizeof(tmp))
return -EINVAL;
Reviewed-by: Clint Taylor
Tested-by: Clint Taylor
].sprite[1],
wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
- if (wm.cxsr && !dev_priv->wm.vlv.cxsr) {
- intel_wait_for_vblank(dev, pipe);
+ if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
intel_set_memory_cxsr(dev_priv, true);
- }
if (w
!= I915_TILING_NONE)
sprctl |= SP_TILED;
- intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
- pixel_size, true,
- src_w != crtc_w || src_h != crtc_h);
-
/* Sizes are 0 based */
src_w--;
.primary >> 8, PLANEA_HI));
}
+ /* zero (unused) WM1 watermarks */
+ I915_WRITE(DSPFW4, 0);
+ I915_WRITE(DSPFW5, 0);
+ I915_WRITE(DSPFW6, 0);
+ I915_WRITE(DSPHOWM1, 0);
+
POSTING_READ(DSPFW1);
}
Reviewed-by: Clint Taylor
Tested-by
On 08/26/2015 12:58 AM, Jani Nikula wrote:
Normally we determine the backlight PWM modulation frequency (which we
also use as backlight max value) from the backlight registers at module
load time, expecting the registers have been initialized by the BIOS. If
this is not the case, we fail.
The VB
);
Simple move of the function with no change in functionality.
Reviewed-by: Clint Taylor
Tested-by: Clint Taylor
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On 08/26/2015 12:58 AM, Jani Nikula wrote:
This is a rebase of [1] and originally [2]. I haven't tried this in a
year and I have no idea if it works on SKL, and it's not implemented for
BXT. However there's renewed interest, so here's the rebase.
Renewed interest as an ODM has been reporting th
n the CPU for clarity.
Cc: Clint Taylor
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_panel.c | 34 +++---
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index e2ab3f6
code.
Cc: Clint Taylor
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h| 2 +
drivers/gpu/drm/i915/i915_reg.h| 3 +
drivers/gpu/drm/i915/intel_panel.c | 187 +++--
3 files changed, 185 insertions(+), 7 deletions(-)
diff --git a
On 09/04/2015 06:55 AM, Jani Nikula wrote:
Fall back to VBT based backlight modulation frequency if it's not
set. Do not hard code.
This could be a problem if there is no VBT.
Cc: Clint Taylor
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_panel.c | 13 -
1
if ((val & FORCE_DDR_HIGH_FREQ) == 0)
+ wm->level = VLV_WM_LEVEL_DDR_DVFS;
+ }
mutex_unlock(&dev_priv->rps.hw_lock);
}
Nice.
Reviewed-by: Clint Taylor
Tested-by: Clint Taylor
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On 09/22/2015 10:27 AM, Ville Syrjälä wrote:
On Tue, Sep 22, 2015 at 10:09:39AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
To reduce eDP T3 time check for digital port connected instead of
msleep. Maintain VBT time if HPD is not asserted on the port.
Current eDP T3 time is
On 12/17/2014 09:04 AM, Paulo Zanoni wrote:
2014-12-10 21:53 GMT-02:00 Todd Previte :
Adds provisions in intel_dp_compute_config() to accommodate compliance
testing. Mostly this invovles circumventing the automatic link configuration
parameters and allowing the compliance code to set those param
On 08/12/2014 07:11 AM, Jani Nikula wrote:
Make it possible to change panel power control backlight state without
touching the PWM. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 39 ++-
1 file changed, 26 insertion
On 08/12/2014 04:07 AM, Ville Syrjälä wrote:
On Tue, Jul 29, 2014 at 02:58:23PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
CEA SD interlaced modes use a horizontal 720 pixels that are pixel replicated
to 1440. The current driver reports 1440 pixel to the OS and does not set
On 08/14/2014 11:48 AM, Ville Syrjälä wrote:
On Thu, Aug 14, 2014 at 11:09:25AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Pixel replicated modes should be 720 horizontal pixel and pixel
replicated by the HW across the HDMI cable at 2X pixel clock. Current
horizontal
On 08/12/2014 07:11 AM, Jani Nikula wrote:
This lets the userspace switch off the backlight using the backlight
class sysfs bl_power file. The switch is done using the power sequencer;
the backlight PWM, and everything else, remains enabled. The display
backlight won't draw power, but for maximum
On 08/18/2014 12:15 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
and flatten the rest of the function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 24
1 file
On 08/12/2014 07:11 AM, Jani Nikula wrote:
Make it possible to change panel power control backlight state without
touching the PWM. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 39 ++-
1 file changed, 26 insertion
On 08/12/2014 07:11 AM, Jani Nikula wrote:
This lets the userspace switch off the backlight using the backlight
class sysfs bl_power file. The switch is done using the power sequencer;
the backlight PWM, and everything else, remains enabled. The display
backlight won't draw power, but for maximum
On 08/13/2014 02:10 AM, Jani Nikula wrote:
Make backlight class sysfs bl_power a sub-state of backlight enabled, if
a backlight power connector callback is defined. It's up to the
connector callback to handle the sub-state, typically in a way that
respects panel power sequencing.
v2: Post the ve
On 08/12/2014 07:11 AM, Jani Nikula wrote:
Make backlight class sysfs brightness 0 value switch off the backlight
for connectors that have the backlight_power callback defined. For eDP,
this has the similar caveats regarding power savings as bl_power as only
the power sequencer backlight control
On 08/20/2014 04:23 AM, Ville Syrjälä wrote:
On Mon, Aug 18, 2014 at 01:48:35PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Backlight on delay uses PWM enable time to seperate PWM to
backlight enable assert. Previous time difference used timing
from VDD enable which occur
i Nikula [mailto:jani.nik...@linux.intel.com]
Sent: Friday, August 22, 2014 6:07 AM
To: Taylor, Clinton A; Ville Syrjälä; Runyan, Arthur J
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL
Enable assert
+Art
On Thu, 21 Aug 2014, Clint Taylor
y work as advertised in the docs?
*shrug* experimental evidence?
commit 01527b3127997ef6370d5ad4fa25d96847fbf12a
Author: Clint Taylor
Date: Mon Jul 7 13:01:46 2014 -0700
drm/i915/vlv: T12 eDP panel timing enforcement during reboot
The panel power sequencer on vlv doesn't ap
On 08/20/2014 03:54 AM, Thomas Wood wrote:
kmstest_edid_add_3d adds an EDID extension block with 3D support to a
copy of the specified EDID.
Signed-off-by: Thomas Wood
---
lib/igt_kms.c | 80 +++
lib/igt_kms.h | 1 +
2 files changed,
On 09/24/2014 01:51 AM, Daniel Vetter wrote:
On Tue, Sep 23, 2014 at 11:06:56AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register
On 09/26/2014 08:58 AM, Ville Syrjälä wrote:
On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
port_clock was being incorrectly computed and WRPLL was incorrectly
programmed for pixel doubled modes using a 27.027MHz pixel clock.
port_clock was set
On 09/26/2014 08:58 AM, Ville Syrjälä wrote:
On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
port_clock was being incorrectly computed and WRPLL was incorrectly
programmed for pixel doubled modes using a 27.027MHz pixel clock.
port_clock was set
On 09/26/2014 09:38 AM, Ville Syrjälä wrote:
On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register
On 09/30/2014 05:46 AM, Ville Syrjälä wrote:
On Fri, Sep 26, 2014 at 09:28:50AM -0700, Clint Taylor wrote:
On 09/26/2014 08:58 AM, Ville Syrjälä wrote:
On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
port_clock was being incorrectly computed
On 10/07/2014 01:52 AM, Ville Syrjälä wrote:
On Mon, Oct 06, 2014 at 03:01:46PM -0700, Clint Taylor wrote:
On 09/26/2014 09:28 AM, Ville Syrjälä wrote:
On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI audio clock config was incorrectly
On 09/26/2014 09:28 AM, Ville Syrjälä wrote:
On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI audio clock config was incorrectly choosing the default for
pixel doubled interlaced modes. The table was missing pixel clock
values 13.500 (27.000
Some devices NAK DPCD writes to the SOURCE OUI (0x300) DPCD registers.
Reduce the log level priority to prevent dmesg noise for these devices.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
Starting with Display 20 the fuse bit to disable Display PM has been
removed.
BSPEC: 69464
Signed-off-by: Clint Taylor
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display_device.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
Starting with Display 13 the fuse bit to disable Display PM has been
removed.
v2: Bit removed starting with Display13 (MattR)
BSPEC: 69464
Cc: Matt Roper
Signed-off-by: Clint Taylor
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display_device.c | 6 --
1 file changed
From: Dnyaneshwar Bhadane
Common display code requires IS_PANTHERLAKE macro.
Define the macro and set 0 as PTL is no longer support for i915.
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915
display version check [Jani]
-change the warn on condition [Jani]
-no need for a different function for edp type c check [Jani]
-dont add register in i915_reg [Jani]
Bspec: 68846
Signed-off-by: Suraj Kandpal
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Arun R Murthy
Acked
From: "Heikkila, Juha-pekka"
Xe3 has no more support for x-tile on display.
v2: Include up to display 29 for X-tiled support. (Gustavo)
Signed-off-by: Heikkila, Juha-pekka
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i9
-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Vinod Govindapillai
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_pmdemand.c | 69 +--
drivers/gpu/drm/i915/display/intel_pmdemand.h | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
This series builds on the previous v2, further enabling new features
for the platform. 1 patch drop at the request of the author.
Clint Taylor (1):
drm/i915/cx0: Remove bus reset after every c10 transaction
Dnyaneshwar Bhadane (3):
drm/i915/ptl: Define IS_PANTHERLAKE macro
drm/i915/cx0
Misc fixes from v3
This series builds on the previous v2, further enabling new features
for the platform. 1 patch drop at the request of the author.
Clint Taylor (1):
drm/i915/cx0: Remove bus reset after every c10 transaction
Dnyaneshwar Bhadane (3):
drm/i915/ptl: Define IS_PANTHERLAKE
C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
transaction. Starting with xe3lpd this is bus reset not necessary
Signed-off-by: Clint Taylor
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 --
1 file changed, 4 insertions(+), 2 deletions
busy bit and command value with 0x1
4. Read mailbox command and wait until run/busy bit is clear
before continuing power request.
Signed-off-by: Mika Kahola
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_tc.c | 40 +
From: Mika Kahola
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when
Starting with display version 13 the fuse bit to disable Display PM has
been removed.
v2: Bit removed starting with display version 13 (MattR)
v3: DG2 still uses this fuse bit (MattR)
BSPEC: 50075, 69464
Cc: Matt Roper
Signed-off-by: Clint Taylor
Signed-off-by: Matt Atwood
---
drivers/gpu
From: Dnyaneshwar Bhadane
When deciding the type of the phy, add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint
C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
transaction. Although not required by BSPEC bus resets were added for
prior platforms as a workaround. Starting with xe3_lpd this bus reset is
not necessary.
Signed-off-by: Clint Taylor
Reviewed-by: Gustavo Sousa
---
drivers/gpu
From: Dnyaneshwar Bhadane
When deciding the type of the phy, add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint
This series has all review comments addressed and review-by's. Basic
enabling is now complete to start testing.
Clint Taylor (1):
drm/i915/cx0: Remove bus reset after every c10 transaction
Dnyaneshwar Bhadane (3):
drm/i915/ptl: Define IS_PANTHERLAKE macro
drm/i915/cx0: Extend C10 che
From: Haridhar Kalvala
At this point we should have enough support landed to turn on and start
basic testing of display functionality.
Signed-off-by: Haridhar Kalvala
Signed-off-by: Clint Taylor
Acked-by: Jani Saarinen
Tested-by: Jani Saarinen
Reviewed-by: Matt Roper
---
drivers/gpu/drm/xe
From: Dnyaneshwar Bhadane
The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD.
Bspec: 69853,69878
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Shekhar Chauhan
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 13
From: Ravi Kumar Vodapalli
>From platforms xe3 Underrun recovery does not exist
v2: improve DISPLAY_VER checking
BSpec: 68849
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Sai Teja Pottumuttu
---
drivers/gpu/drm/i915/disp
From: Ravi Kumar Vodapalli
Spec does not request to disable VRR in the modeset disabling
sequence for DP and HDMI for xe3_lpd.
Bspec: 68848
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +---
1 file changed, 5 insertion
splay_ver check, use INTEL_NUM_PIPES
v4: add a conditional for number of pipes macro vs using 3.
v5: reverse conditional order of v4.
Bspec: 68883, 69125
Signed-off-by: Matt Roper
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_pmdemand.c | 68
From: Dnyaneshwar Bhadane
When deciding the type of the phy, add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint
From: Suraj Kandpal
Read PICA register to see if edp over type C is possible and then
add the appropriate tables for it.
--v2
-remove bool from intel_encoder have it in runtime_info [Jani]
-initialize the bool in runtime_info init [Jani]
-dont abbreviate the bool [Jani]
Bspec: 68846
Signed-off-
From: Mika Kahola
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when
From: Mitul Golani
In progress to make VRR timing generator as the default timing generator,
rest other timings will be derived based on vrr.vmin and vrr.vmax. Call
intel_vrr_get_config before intel_get_transcoder_timings to accommodate
values getting pre-filled.
Signed-off-by: Mitul Golani
Sig
This series builds on the previous one, further enabling new features
for the platform. 3 patches from the previous series have been brought
forward to this series.
Clint Taylor (1):
drm/i915/cx0: Remove bus reset after every c10 transaction
Dnyaneshwar Bhadane (3):
drm/i915/ptl: Define
From: Dnyaneshwar Bhadane
The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD.
Bspec: 69853,69878
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 13 +
.../gpu/drm/i915
From: Dnyaneshwar Bhadane
Common display code requires IS_PANTHERLAKE macro.
Define the macro and set 0 as PTL is no longer support for i915.
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 ins
From: Ravi Kumar Vodapalli
>From platforms xe3 Underrun recovery does not exist
v2: improve DISPLAY_VER checking
BSpec: 68849
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed
From: Suraj Kandpal
We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI
encoder.
v2: add additional definition instead of function, commit message typo
fix and update.
v3: restore lost conditional from v2.
v4: subject line and subject message updated, fix the if ladder order,
C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
transaction. Starting with xe3lpd this is bus reset not necessary
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
101 - 200 of 232 matches
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