On 12/03/2014 01:01 PM, Ville Syrjälä wrote:
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>

Added PIPE C register support for CHV audio programming.

nak. The offset between the pipes looks constant so it should work
just fine with _PIPE().

Correct. Now I just need to figure out why AUD_CONFIG_C is cleared after ChromeOS boot.

-Clint



Signed-off-by: Clint Taylor <clinton.a.tay...@intel.com>
---
  drivers/gpu/drm/i915/i915_reg.h |   18 ++++++++++++------
  1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc03fac..3d5813a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6189,14 +6189,18 @@ enum punit_power_well {

  #define _VLV_HDMIW_HDMIEDID_A         (VLV_DISPLAY_BASE + 0x62050)
  #define _VLV_HDMIW_HDMIEDID_B         (VLV_DISPLAY_BASE + 0x62150)
-#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+#define _CHV_HDMIW_HDMIEDID_C          (VLV_DISPLAY_BASE + 0x62250)
+#define VLV_HDMIW_HDMIEDID(pipe) _PIPE3(pipe, \
                                        _VLV_HDMIW_HDMIEDID_A, \
-                                       _VLV_HDMIW_HDMIEDID_B)
+                                       _VLV_HDMIW_HDMIEDID_B, \
+                                       _CHV_HDMIW_HDMIEDID_C)
  #define _VLV_AUD_CNTL_ST_A            (VLV_DISPLAY_BASE + 0x620B4)
  #define _VLV_AUD_CNTL_ST_B            (VLV_DISPLAY_BASE + 0x621B4)
-#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+#define _CHV_AUD_CNTL_ST_C             (VLV_DISPLAY_BASE + 0x622B4)
+#define VLV_AUD_CNTL_ST(pipe) _PIPE3(pipe, \
                                        _VLV_AUD_CNTL_ST_A, \
-                                       _VLV_AUD_CNTL_ST_B)
+                                       _VLV_AUD_CNTL_ST_B, \
+                                       _CHV_AUD_CNTL_ST_C)
  #define VLV_AUD_CNTL_ST2              (VLV_DISPLAY_BASE + 0x620C0)

  /* These are the 4 32-bit write offset registers for each stream
@@ -6217,9 +6221,11 @@ enum punit_power_well {
                                        _CPT_AUD_CONFIG_B)
  #define _VLV_AUD_CONFIG_A             (VLV_DISPLAY_BASE + 0x62000)
  #define _VLV_AUD_CONFIG_B             (VLV_DISPLAY_BASE + 0x62100)
-#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
+#define _CHV_AUD_CONFIG_C              (VLV_DISPLAY_BASE + 0x62200)
+#define VLV_AUD_CFG(pipe) _PIPE3(pipe, \
                                        _VLV_AUD_CONFIG_A, \
-                                       _VLV_AUD_CONFIG_B)
+                                       _VLV_AUD_CONFIG_B, \
+                                       _CHV_AUD_CONFIG_C)

  #define   AUD_CONFIG_N_VALUE_INDEX            (1 << 29)
  #define   AUD_CONFIG_N_PROG_ENABLE            (1 << 28)
--
1.7.9.5

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