For 50-58, with Jani's coding style fix:
Reviewed-by: Antti Koskipää
--
- Antti
On 04/09/2014 01:28 PM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/d
On 06/02/2014 11:49 AM, Daniel Vetter wrote:
> On Fri, May 30, 2014 at 04:35:26PM +0300, Chris Wilson wrote:
>> It is possible for userspace to create a big object large enough for a
>> 256x256, and then switch over to using it as a 64x64 cursor. This
>> requires the cursor update routines to check
| 70
> +++-
> drivers/gpu/drm/i915/intel_tv.c | 1 +
> 11 files changed, 110 insertions(+), 12 deletions(-)
>
> Signed-off-by: Imre Deak
Reviewed-by: Antti Koskipää
--
- Antti
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
ivers/gpu/drm/i915/i915_reg.h | 10 +++--
> drivers/gpu/drm/i915/intel_pm.c | 47
> ++---
> 2 files changed, 47 insertions(+), 10 deletions(-)
For everything except 4/7, which was reviewed by Ken:
Reviewed-by: Antti Koskipää
--
- Antti
__
| 1 +
> drivers/gpu/drm/i915/intel_pm.c | 4
> 5 files changed, 30 insertions(+), 12 deletions(-)
For the whole series,
Reviewed-by: Antti Koskipää
--
- Antti
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 04/02/2014 02:21 PM, Ville Syrjälä wrote:
> On Wed, Apr 02, 2014 at 02:06:28PM +0300, Antti Koskipaa wrote:
>
>> @@ -184,9 +192,6 @@ static void test_crc_offscreen(test_data_t *test_data)
>> do_test(test_data, left - (cursor_w+512), right + (cursor_w+512), top
>> , bottom
On 01/22/14 08:50, Barbalho, Rafael wrote:
> BCLRPAT is in the transcoder, not the pipe.
> PIPERSRC is in the transcoder not in the pipe.
> PIPECONF is in the pipe not the transcoder.
> Missing from that patch is also all the DSP* registers (DSPCNTR,DSPADDR,
> etc...) those should use the new
On 01/24/14 14:52, Ville Syrjälä wrote:
> On Fri, Jan 24, 2014 at 02:13:14PM +0200, Antti Koskipaa wrote:
>> +#define PIPE_A_OFFSET 0x7
>> +#define PIPE_B_OFFSET 0x71000
>> +#define PIPE_C_OFFSET 0x72000
>
> I'd like a comment here to explain what PIPE_EDP_OFFSET
> actually m
Sorry, sent the wrong file. Ignore this one.
--
- Antti
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 01/27/14 13:21, Chris Wilson wrote:
> On Mon, Jan 27, 2014 at 01:17:25PM +0200, Antti Koskipaa wrote:
>> RFCv2: Reorganize array indexing so that full offsets can be used as
>> is. It makes grepping for registers in i915_reg.h much easier. Also
>> move offset arrays to intel_device_info.
>>
>> P
On 01/27/14 15:31, Ville Syrjälä wrote:
> On Mon, Jan 27, 2014 at 03:09:34PM +0200, Antti Koskipaa wrote:
>> +.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
>> +.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
>> +.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET
On 10/31/13 09:32, Jani Nikula wrote:
> On Wed, 30 Oct 2013, Antti Koskipaa wrote:
>> Upcoming hardware will not have the various display pipe register
>> ranges evenly spaced in memory. Change register address calculations
>> into array lookups.
>>
>> Tested on SandyBridge.
>>
>> I left the UMS c
Both patches look ok.
Reviewed-by: Antti Koskipaa
On 08/21/12 02:15, Ben Widawsky wrote:
> ERR_INT can generate interrupts. However since most of the conditions seem
> quite fatal the patch opts to simply report it in error state instead of
> adding more complexity to the interrupt handler for l
Hi,
On 08/22/12 12:17, Vijay Purushothaman wrote:
> This is already fixed for ILK and SNB in the below commit but somehow
> IVB is missed.
>
> commit ab2f9df10dd955f1fc0a8650e377588c98f1c029
> Author: Jesse Barnes
> Date: Mon Feb 27 12:40:10 2012 -0800
>
> drm/i915: fix color order for BG
Hi,
On 10/25/12 22:15, Jesse Barnes wrote:
> This allows us to get the right vblank interrupt frequency.
>
> v2: pull in register definition
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/i915_reg.h |2 ++
> drivers/gpu/drm/i915/intel_pm.c |7 +++
> 2 files changed, 9
On 11/01/12 16:50, Jesse Barnes wrote:
> No, it's in the gunit spec. I'm still working on getting that one
> opened up.
In that case, for the whole lot:
Reviewed-by: Antti Koskipää
--
- Antti
___
Intel-gfx mailin
On 11/20/12 20:24, Роман Мельник wrote:
> Good day!
>
> I've sent already mail, but got no response, so trying again.
> Please advise how to disable dpst on linux? The module is i915. As I
> see, windows driver has such checkbox for this. Can I do the same on linux?
The linux driver does not supp
On 11/22/12 16:36, РоманМельник wrote:
> Antti Koskipää linux.intel.com> writes:
>
>>
>> On 11/20/12 20:24, Роман Мельник wrote:
>>> Good day!
>>>
>>> I've sent already mail, but got no response, so trying again.
>>> Please advise
Another bug team week gone...
Antti:
Went through bugzilla, checking that work is still being done, general
stuff.
Mika:
Fixed https://bugs.freedesktop.org/show_bug.cgi?id=58230
Tried to verify a fix (drm/i915: disable shrinker lock
stealing for create_mmap_offset) for a problem i reported
but
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau
>
> v2: Switch to info->ring_mask and add VEBOX support.
> v3: Fold in update from Damien.
> v4: Add GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS
> v5: set no-LLC (imre)
>
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Sumit Singh
>
> The caching options for page table entries have remained the same as
> Cherryview. This patch fixes it so the right code path is taken on BXT.
>
> v2: Fix up commit message (Mike)
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau
>
> v2: Rebase on top of the early-quirks rework from Ville.
>
> Signed-off-by: Damien Lespiau (v1)
> Signed-off-by: Daniel Vetter
> ---
> arch/x86/kernel/early-quirks.c |
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau
>
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau
>
> Pipe A and b have 4 planes.
>
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau
>
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Damien Lespiau
>
> v2: Rebase on top of the for_each_pipe() change adding dev_priv as first
> argument.
>
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_dma.c | 6 +++
Reviewed-by: Antti Koskipää
On 03/27/2015 01:07 PM, Imre Deak wrote:
> On Broxton per specification the GTT has to be mapped as uncached.
> This was caught by the PTE write readback warning, which showed a
> corrupted PTE value with using the current write-combine mapping.
>
&
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Daisy Sun
>
> Enable FBC feature on Broxton
>
> Issue: VIZ-3784
> Signed-off-by: Daisy Sun
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> 1 file cha
Reviewed-by: Antti Koskipää
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Daisy Sun
>
> Enable FBC feature on Broxton
>
> Issue: VIZ-3784
> Signed-off-by: Daisy Sun
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> 1 file cha
Reviewed-by: Antti Koskipää
On 03/26/2015 05:35 PM, Imre Deak wrote:
> Starting from GEN5 the FBC base register is the same on all platforms.
> GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
> things work on BXT as well.
>
> Motivated by Rodrigo'
Just FYI, this patch depends on David Weinehall's Buffer translation
improvements patch from earlier today.
--
- Antti
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Looks fine to me.
Reviewed-by: Antti Koskipää
On 06/25/2015 11:11 AM, David Weinehall wrote:
> This patch adds support for 0.85V VccIO on Skylake Y,
> separate buffer translation tables for Skylake U,
> and support for I_boost for the entries that needs this.
>
> Changes in v2:
On 07/03/2015 06:09 PM, Paulo Zanoni wrote:
> 2015-07-03 8:28 GMT-03:00 Antti Koskipaa :
>> An OEM may request increased I_boost beyond the recommended values
>> by specifying an I_boost value to be applied to all swing entries for
>> a port. These override values are specified in VBT.
>>
>> v2: re
On 05/26/2015 02:37 PM, Jani Nikula wrote:
> On Sat, 23 May 2015, Antti Koskipaa wrote:
>> This is a basic sanity test of the backlight sysfs interface.
>>
>> Issue: VIZ-3377
>> Signed-off-by: Antti Koskipaa
>> ---
>> tests/.gitignore | 1 +
>> tests/Makefile.sources | 1 +
>> tests/pm
Reviewed-by: Antti Koskipaa
--
- Antti
On 08/18/2014 10:16 PM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> VLV/CHV have a per-pipe panel power sequencer which locks onto the
> port once used. We need to keep track wich power sequencers are
> locked to which ports.
>
> Sign
35 matches
Mail list logo
