== Series Details ==
Series: series starting with [1/2] drm/i915: Enable/disable shared dplls just
the once for joined pipes
URL : https://patchwork.freedesktop.org/series/146097/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16258 -> Patchwork_146097v1
==
On 2/28/2025 8:55 PM, Suraj Kandpal wrote:
Some DSI panel vendors end up hardcoding PPS params because of which
it does not listen to the params sent from the source. We use the
default config tables for DSI panels when using DSC 1.1 rather than
calculate our own rc parameters.
--v2
-Use intel
On Mon, 10 Mar 2025, Gustavo Sousa wrote:
> Quoting Ville Syrjälä (2025-03-10 13:47:57-03:00)
>>On Fri, Mar 07, 2025 at 04:25:11PM -0300, Gustavo Sousa wrote:
>>> Update intel_bw.c internally use intel_display. Conversion of the public
>>> interface will come as a follow-up.
>>>
>>> Cc: Ville Syr
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, March 7, 2025 7:36 PM
> To: Kandpal, Suraj
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Nautiyal,
> Ankit K ; Shankar, Uma
> ; Kahola, Mika
> Subject: Re: [PATCH 07/11] drm/i915/dpll: Change argument
To move away from legacy timing generator and always use VRR timing
generator, some refactoring is required in existing VRR code.
This series is a spinoff from the original series [1], tackling only VRR
refactoring patches from the main series.
[1] https://patchwork.freedesktop.org/series/141152/
The comment about fixed average vtotal is incorrect.
Remove it.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/
Reorder the macros HAS_AS_SDP and HAS_CMRR as per alphabetical order.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_device.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/d
On Mon, 10 Mar 2025, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On ILK-IVB only PCH outputs use shared dplls. Move the relevant
> intel_disable_shared_dpll() into ilk_pch_post_disable() to make
> that clear (and if we extend the dpll mgr to cover all plls we need
> different enable/disable po
On Mon, 10 Mar 2025, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we loop over all joined pipes and enable/disable the
> shared dplls for each. We don't really have to do that since
> all joined pipes will be using the same dpll. So let's just do
> the enable/disable once for the whol
Hello Chris Wilson,
Commit 52c0fdb25c7c ("drm/i915: Replace global breadcrumbs with
per-context interrupt tracking") from Jan 29, 2019 (linux-next),
leads to the following Smatch static checker warning:
drivers/gpu/drm/i915/selftests/i915_request.c:385
__igt_breadcrumbs_smoketest()
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add the register bits related to filter lut values
and populate the table.
Lets have some more details about the LUT values and the fact that they
are only needed to be loaded once.
With that fixed this looks good to me.
Reviewed-by: Ankit Nautiyal
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add the macro for casf HAS_CASF.
A bit explanation about the macro and why is this introduced will be good.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/dr
Convert i915 runtime PM interfaces to display runtime PM interfaces all
over the place in display code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/hsw_ips.c | 8
.../drm/i915/display/intel_display_debugfs.c| 17 +++--
.../gpu/drm/i915/display/i
Convert all with_intel_runtime_pm() uses to with_intel_display_rpm().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_backlight.c | 5 ++---
drivers/gpu/drm/i915/display/intel_bios.c | 6 +++---
drivers/gpu/drm/i915/display/intel_hdcp.c | 5 ++---
drivers/gpu/drm/i915
Finish the conversions to display specific runtime PM interfaces in the
power code.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_power.c| 63 ---
.../i915/display/intel_display_power_well.c | 4 +-
2 files changed, 30 insertions(+), 37 deletions(-)
di
Add an abstracted display runtime PM interface to hide i915 and xe
specific details, and remove the xe compat intel_runtime_pm.h. We can
reduce direct i915 accesses from display all over the place.
Text size remains roughly the same for both i915 and xe; here's the
bloat-o-meter results for i915.k
Add display specific wrappers around the i915 and xe dedicated runtime
PM interfaces. There are no conversions here, just the wrappers.
Implement with_intel_display_rpm() without needing to provide a local
variable, which neatly narrows the scope and hides the type of the
wakeref cookie.
Signed-o
Convert intel_atomic_commit() and intel_atomic_commit_tail() to use
display runtime PM interfaces. Also convert the wakeref member type to
struct ref_tracker *, which is the same as intel_wakeref_t, but without
the typedef.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_displa
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
As only second scaler can be used for sharpness check if it
is available and also check if panel fitting is also not enabled,
then set the sharpness. Panel fitting will have the preference
over sharpness property.
v2: Add the panel fitting check before e
== Series Details ==
Series: drm/i915/selftests: Refactor RC6 power measurement and error handling
(rev2)
URL : https://patchwork.freedesktop.org/series/145766/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16237 -> Patchwork_145766v2
=
On Mon, Mar 10, 2025 at 03:57:58PM -0300, Gustavo Sousa wrote:
> Update intel_bw.c internally use intel_display. Conversion of the public
> interface will come as a follow-up.
>
> v2:
> - Prefer intel_uncore_read() for MCHBAR registers. (Ville)
>
> Cc: Ville Syrjälä
> Signed-off-by: Gustavo So
Quoting Ville Syrjälä (2025-03-11 13:46:25-03:00)
>On Mon, Mar 10, 2025 at 03:57:58PM -0300, Gustavo Sousa wrote:
>> Update intel_bw.c internally use intel_display. Conversion of the public
>> interface will come as a follow-up.
>>
>> v2:
>> - Prefer intel_uncore_read() for MCHBAR registers. (Vi
On 3/10/2025 11:42 PM, Ville Syrjälä wrote:
On Mon, Mar 10, 2025 at 05:46:14PM +0530, Ankit Nautiyal wrote:
Currently VRR timing generator is used only when VRR is enabled by
userspace for sinks that support VRR. From MTL+ gradually move away from
the older timing generator and use VRR timing
== Series Details ==
Series: i915/gt/selftests: Disable lrc_timestamp test
URL : https://patchwork.freedesktop.org/series/146125/
State : warning
== Summary ==
Error: dim checkpatch failed
95199fb5c6f5 i915/gt/selftests: Disable lrc_timestamp test
-:12: WARNING:COMMIT_LOG_USE_LINK: Unknown lin
Hi,
[...]
> If that's the case, then the patch is alright. I was mostly worried
> about messing with userspace memory of a random process.
>
> > If we put on our paranoia hats, the biggest problem with borrowing
> > userspace's mm is that it gives them temporary insight into whatever
> > we plac
On Fri, Mar 07, 2025 at 08:18:18PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/dp_mst: Fix locking when skipping CSN before topology probing
> URL : https://patchwork.freedesktop.org/series/146019/
> State : success
Thanks for the reviews, patch is pushed to drm-misc-fixes.
Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing
generator is used with variable timings.
Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable
when vmax == vmin == flipline (fixed refresh rate timing).
v2: Use intel_vrr_vmin_flipline() to account f
Currently we always compute the timings as if vrr is enabled.
With this approach the state checker becomes complicated when we
introduce fixed refresh rate mode with vrr timing generator.
To avoid the complications, instead of always computing vrr timings, we
compute vrr timings based on uapi.vrr_
MSA Ignore Timing PAR enable is set in the DP sink when we enable variable
refresh rate.
Currently for link training we depend on flipline to decide whether we
want to ignore the msa timings. With fixed refresh rate we will still
fill the flipline in all cases whether panel supports VRR or not.
C
Make helpers to compute vmin and vmax.
v2: Make the adjusted mode const (Ville)
Use reverse xmas tree order of declarations. (Ville)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c | 38 +++-
1 file changed, 30 insertion
Separate out functions for computing cmrr and vrr timings.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c | 45 +++-
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.
Switching between variable and fixed timings is possible as for that we
just need to flip between VRR timings. However for CMRR along with the
timings, few other bits also need to be changed on the fly, which might
cause issues. So disable CMRR for now, till we have variable and fixed
timings sorte
To have fixed refresh rate with VRR timing generator the
guardband/pipeline full can't be programmed on the fly. So we need to
ensure that the values satisfy both the fixed and variable refresh
rates.
Since we compute these value based on vmin, lets set the vmin to
crtc_vtotal for both fixed and v
> -Original Message-
> From: Kandpal, Suraj
> Sent: Tuesday, 11 March 2025 10.16
> To: Ville Syrjälä
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> Nautiyal, Ankit
> K ; Shankar, Uma ;
> Kahola, Mika
> Subject: RE: [PATCH 07/11] drm/i915/dpll: Change argument
== Series Details ==
Series: i915/gt/selftests: Disable lrc_timestamp test
URL : https://patchwork.freedesktop.org/series/146125/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16262 -> Patchwork_146125v1
Summary
---
Quoting Jani Nikula (2025-03-11 06:26:32-03:00)
>On Mon, 10 Mar 2025, Gustavo Sousa wrote:
>> Quoting Ville Syrjälä (2025-03-10 13:47:57-03:00)
>>>On Fri, Mar 07, 2025 at 04:25:11PM -0300, Gustavo Sousa wrote:
Update intel_bw.c internally use intel_display. Conversion of the public
inter
On 3/10/2025 11:37 PM, Ville Syrjälä wrote:
On Mon, Mar 10, 2025 at 05:46:09PM +0530, Ankit Nautiyal wrote:
During modeset enable sequence, program the fixed timings, and turn on the
VRR Timing Generator (VRR TG) for platforms that always use VRR TG.
For this intel_vrr_set_transcoder now alwa
== Series Details ==
Series: VRR Refactor
URL : https://patchwork.freedesktop.org/series/146126/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced sy
On 07-03-2025 00:41, sk.anir...@intel.com wrote:
From: Sk Anirban
Refactor power measurement logic to store and compare energy values.
Introduce a threshold check to ensure the GPU enters RC6 properly.
v2:
- Improved commit message (Badal)
v3:
- Reorder threshold check (Badal)
Signed-
Hi Mikolaj,
> This test was designed to isolate a bug in tigerlake and dg2 hardware.
> The bug was found and fixed in newer generations.
> Since we won't support any new hardware with this driver, the test
> should now be turned off in the CI to not pollute it with random failures
> on previous ha
This change is to avoid over-specification of the TEOT timing
parameter, which is derived from software in current design.
Supposed that THS-TRAIL and THS-EXIT have the minimum values,
i.e., 60 and 100 in ns. If SW is overriding the HW default,
the TEOT value becomes 150 ns, approximately calculat
> -Original Message-
> From: Kahola, Mika
> Sent: Friday, March 7, 2025 7:24 PM
> To: Ville Syrjälä
> Cc: Kandpal, Suraj ; Jani Nikula
> ; intel...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; Syrjala, Ville ;
> Nautiyal,
> Ankit K ; Shankar, Uma
> Subject: RE: [PATCH 0
== Series Details ==
Series: VRR Refactor
URL : https://patchwork.freedesktop.org/series/146126/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16262 -> Patchwork_146126v1
Summary
---
**FAILURE**
Serious unknown ch
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Once the casf_compute config is called then the
strength and win_size bit of sharpness ctl register
will be set. Read back the bits in get_config.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c| 11 +++
drivers/gpu/d
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add a check for enabling/disabling the casf
and enable the sharpness bit. Also load the
filter lut value which is needed one time.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c| 18 +++
drivers/gpu/drm/i915/disp
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Expose the drm crtc sharpness property
which will ultimately enable the sharpness.
The drm crtc property is sharpness strength.
So lets have the subject and commit message in line with that.
Regards,
Ankit
Signed-off-by: Nemesa Garg
---
driver
This test was designed to isolate a bug in tigerlake and dg2 hardware.
The bug was found and fixed in newer generations.
Since we won't support any new hardware with this driver, the test
should now be turned off in the CI to not pollute it with random failures
on previous hardware.
Fixes: https:/
Since the vrr.guardband can now change for platforms that always use the
VRR Timing Generator, and it is unsafe to reprogram the guardband on the
fly, move the guardband and pipeline_full checks from the pure !fastboot
path and add a check for intel_vrr_always_use_vrr_tg().
For older platforms the
Even though the VRR timing generator (TG) is primarily used for
variable refresh rates, it can be used for fixed refresh rates as
well. For a fixed refresh rate the Flip Line and Vmax must be equal
(TRANS_VRR_FLIPLINE = TRANS_VRR_VMAX). Beyond that, there are some
dependencies between the VRR timin
From: Ville Syrjälä
Hoist the bw stuff into a separate function from
intel_crtc_disable_noatomic_complete() so that the details
are better hidden inside intel_bw.c.
We can also skip the whole thing on pre-skl since the dbuf state
isn't actually used on those platforms.
Reviewed-by: Vinod Govind
On Mon, Mar 10, 2025 at 05:46:14PM +0530, Ankit Nautiyal wrote:
> Currently VRR timing generator is used only when VRR is enabled by
> userspace for sinks that support VRR. From MTL+ gradually move away from
> the older timing generator and use VRR timing generator for both variable
> and fixed tim
Bandwidth parameters for Xe3_LPD have been updated with respect to
previous display releases. Encode them into xe3lpd_sa_info and use that
new struct.
Since we are touching intel_bw.c, also take the opportunity convert it
to intel_display.
Changes in v2:
- Fix typo in patch #2.
Changes in v3:
From: Ville Syrjälä
Currently we loop over all joined pipes and enable/disable the
shared dplls for each. We don't really have to do that since
all joined pipes will be using the same dpll. So let's just do
the enable/disable once for the whole set of joined pipes.
We can still keep tracking the
On Mon, Mar 10, 2025 at 05:46:12PM +0530, Ankit Nautiyal wrote:
> Since the vrr.guardband can now change for platforms that always use the
> VRR Timing Generator, and it is unsafe to reprogram the guardband on the
> fly, move the guardband and pipeline_full checks from the pure !fastboot
> path and
== Series Details ==
Series: drm/i915/display: add display specific runtime PM interface
URL : https://patchwork.freedesktop.org/series/146134/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16263 -> Patchwork_146134v1
Summa
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Compute the values for second scaler for sharpness.
Fill the register bits corresponding to the scaler.
v1: Rename the title of patch [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 3 ++
drivers/gpu/drm/i915/disp
Bandwidth parameters for Xe3_LPD have been updated with respect to
previous display releases. Encode them into xe3lpd_sa_info and use that
new struct.
Since we are touching intel_bw.c, also take the opportunity convert it
to intel_display.
Changes in v2:
- Fix typo in patch #2.
Changes in v3:
Update intel_bw.c internally use intel_display. Conversion of the public
interface will come as a follow-up.
v2:
- Prefer intel_uncore_read() for MCHBAR registers. (Ville)
v3:
- Remove the unnecessary inclusion of intel_de.h after changes from
v2. (Ville)
Reviewed-by: Ville Syrjälä
Signe
We already have internal interface for intel_bw.c converted to use
intel_display. Now convert the external interface as well.
Reviewed-by: Ville Syrjälä
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c| 25 +-
drivers/gpu/drm/i915/display/
Bandwidth parameters for Xe3_LPD have been updated with respect to
previous display releases. Encode them into xe3lpd_sa_info and use that
new struct.
Bspec: 68859
Reviewed-by: Matt Roper
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c | 11 ++-
1 file changed,
From: Lucas De Marchi
Add some additional tests in lib/test_bits.c to cover the
expected/non-expected values of the fixed-type GENMASK_U*() macros.
Also check that the result value matches the expected type. Since
those are known at build time, use static_assert() instead of normal
kunit tests.
== Series Details ==
Series: bits: Fixed-type GENMASK_U*() and BIT_U*()
URL : https://patchwork.freedesktop.org/series/146088/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/146088/revisions/1/mbox/ not
applied
Applying: bits: split the definition
We have a local display variable, use it directly.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 33b8d5229db
Get to the struct intel_display pointer, not struct drm_i915_private.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 21 ++--
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu
As the first step towards making struct intel_display an opaque pointer
in i915 and xe drivers, convert the struct drm_i915_private and struct
xe_device display members into pointers.
Initially, add temporary struct intel_display __display members, and
point display at it to avoid dynamic allocati
On Mon, Mar 10, 2025 at 06:27:53PM -0300, André Almeida wrote:
> Em 01/03/2025 02:53, Raag Jadav escreveu:
> > On Fri, Feb 28, 2025 at 06:54:12PM -0300, André Almeida wrote:
> > > Hi Raag,
> > >
> > > On 2/28/25 11:20, Raag Jadav wrote:
> > > > Cc: Lucas
> > > >
> > > > On Fri, Feb 28, 2025 at 09
During modeset enable sequence, program the fixed timings, and turn on the
VRR Timing Generator (VRR TG) for platforms that always use VRR TG.
For this intel_vrr_set_transcoder now always programs fixed timings.
Later if vrr timings are required, vrr_enable() will switch
to the real VRR timings.
A rough idea what making struct intel_display opaque towards i915 and xe
core code looks like.
This is by no means ready, and patch 4 is still way too big. We need to
do more regular struct drm_i915_private to struct intel_display
conversions before this is feasible.
But we're getting closer.
BR
On Mon, Mar 10, 2025 at 06:03:27PM -0400, Alex Deucher wrote:
> On Mon, Mar 10, 2025 at 5:54 PM André Almeida wrote:
> >
> > Em 01/03/2025 03:04, Raag Jadav escreveu:
> > > On Fri, Feb 28, 2025 at 06:49:43PM -0300, André Almeida wrote:
> > >> Hi Raag,
> > >>
> > >> On 2/28/25 11:58, Raag Jadav wro
On Wed, Mar 05, 2025 at 09:11:07PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dp: Fix link training interrupted by HPD pulse (rev3)
> URL : https://patchwork.freedesktop.org/series/145782/
> State : failure
Thanks for the reviews, patchset is pushed to drm-intel-next.
== Series Details ==
Series: drm/i915/dsi: let HW maintain the HS-TRAIL timing (rev4)
URL : https://patchwork.freedesktop.org/series/96750/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16262 -> Patchwork_96750v4
Summary
--
On 11-03-2025 16:47, Nilawar, Badal wrote:
On 07-03-2025 00:41, sk.anir...@intel.com wrote:
From: Sk Anirban
Refactor power measurement logic to store and compare energy values.
Introduce a threshold check to ensure the GPU enters RC6 properly.
v2:
- Improved commit message (Badal)
v3
== Series Details ==
Series: drm/i915/display: add display specific runtime PM interface
URL : https://patchwork.freedesktop.org/series/146134/
State : warning
== Summary ==
Error: dim checkpatch failed
92c803c467d2 drm/i915/display: add display specific runtime PM wrappers
-:28: WARNING:FILE_
== Series Details ==
Series: drm/i915/xe3lpd: Update bandwidth parameters (rev5)
URL : https://patchwork.freedesktop.org/series/11/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16263 -> Patchwork_11v5
Summary
-
Make i915->display opaque.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 +
drivers/gpu/drm/i915/display/i9xx_wm.c | 1 +
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_bios.c
A quick hack to allocate struct intel_display dynamically. No error
handling yet.
For xe, xe->display may be NULL for DRM_XE_DISPLAY=n or
xe.probe_display=n. This needs to be handled gracefully.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_driver.c | 4 ++--
drivers/gpu/drm/i91
Make xe->display opaque.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/display/xe_display.c | 1 +
drivers/gpu/drm/xe/display/xe_fb_pin.c| 1 +
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 1 +
drivers/gpu/drm/xe/display/xe_plane_initial.c | 1 +
drivers/gpu/drm/xe/display/x
We already have internal interface for intel_bw.c converted to use
intel_display. Now convert the external interface as well.
Reviewed-by: Ville Syrjälä
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c| 25 +-
drivers/gpu/drm/i915/display/
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add new registers and related bits. Compute the strength
value and tap value based on display mode.
Lets have some more details about what is strength and win size and why
is this required for sharpness.
In this what is missing is the readback part whi
On 2025/3/7 21:54, Matthew Wilcox (Oracle) wrote:
Call swap_writeout() and shmem_writeout() from pageout() instead.
Signed-off-by: Matthew Wilcox (Oracle)
I tested shmem swap-out and swap-in with your patch set, and works well.
So feel free to add:
Reviewed-by: Baolin Wang
Tested-by: Ba
== Series Details ==
Series: VRR Refactor (rev2)
URL : https://patchwork.freedesktop.org/series/146126/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unrepl
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev13)
URL : https://patchwork.freedesktop.org/series/134383/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16254 -> Patchwork_134383v13
Su
On Fri, Mar 07, 2025 at 04:25:11PM -0300, Gustavo Sousa wrote:
> Update intel_bw.c internally use intel_display. Conversion of the public
> interface will come as a follow-up.
>
> Cc: Ville Syrjälä
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 416
> +
Bandwidth parameters for Xe3_LPD have been updated with respect to
previous display releases. Encode them into xe3lpd_sa_info and use that
new struct.
Bspec: 68859
Reviewed-by: Matt Roper
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c | 11 ++-
1 file changed,
From: Ville Syrjälä
Hoist the bw stuff into a separate function from
intel_modeset_readout_hw_state() so that the details
are better hidden inside intel_bw.c.
We can also skip the whole thing on pre-skl since the dbuf state
isn't actually used on those platforms.
Reviewed-by: Vinod Govindapilla
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev13)
URL : https://patchwork.freedesktop.org/series/134383/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/i
== Series Details ==
Series: VRR Refactor (rev2)
URL : https://patchwork.freedesktop.org/series/146126/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16263 -> Patchwork_146126v2
Summary
---
**FAILURE**
Serious unk
== Series Details ==
Series: drm/i915/display: Maintain alphabetical order for HAS_AS_SDP and
HAS_CMRR
URL : https://patchwork.freedesktop.org/series/146143/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Separate out functions for computing cmrr and vrr timings.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c | 45 +++-
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.
On Mon, Mar 10, 2025 at 03:12:43PM +0200, Jani Nikula wrote:
> On Fri, 07 Mar 2025, Gustavo Sousa wrote:
> > Bandwidth parameters for Xe3_LPD have been updated with respect to
> > previous display releases. Encode them into xe3lpd_sa_info and use that
> > new struct.
> >
> > Since we are touching
On Mon, Mar 10, 2025 at 01:01:25PM +, Lin, Wayne wrote:
> [Public]
>
> > -Original Message-
> > From: Imre Deak
> > Sent: Monday, March 10, 2025 7:00 PM
> > To: Lin, Wayne
> > Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org; dri-
> > de...@lists.freedesktop.org; L
From: Ville Syrjälä
Reuse intel_plane_set_invisible() in intel_plane_disable_noatomic()
instead of hand rolling the same stuff.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 1 insertion(+), 5 deletion
Hello Li,
Hope you are doing well. I am Chaitanya from the linux graphics team in Intel.
This mail is regarding a regression we are seeing in our CI runs[1] on
linux-next repository.
Since the version next-20250304 [2], we are seeing the following regression
```
== Series Details ==
Series: drm/i915: make i915->display opaque pointer
URL : https://patchwork.freedesktop.org/series/146155/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16263 -> Patchwork_146155v1
Summary
---
**
== Series Details ==
Series: drm/i915: make i915->display opaque pointer
URL : https://patchwork.freedesktop.org/series/146155/
State : warning
== Summary ==
Error: dim checkpatch failed
86f3f992d5c6 drm/i915/hdmi: remove inline to_i915()
5ce6ca11f746 drm/i915/hotplug: use container_of() to ge
== Series Details ==
Series: drm/i915: make i915->display opaque pointer
URL : https://patchwork.freedesktop.org/series/146155/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Tue, Mar 11, 2025 at 08:00:34PM +0200, Jani Nikula wrote:
> Primarily convert all hotplug and irq code to struct intel_display, and
> then some.
>
> Jani Nikula (9):
> drm/i915/color: prefer display->platform. checks
> drm/i915/connector: convert intel_connector.c to struct intel_display
>
On Tue, Mar 11, 2025 at 08:00:41PM +0200, Jani Nikula wrote:
> Going forward, struct intel_display is the main display device data
> pointer. Convert the external interfaces of intel_display_irq.[ch] to
> struct intel_display.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/i
Quoting Ville Syrjälä (2025-03-10 13:37:15-03:00)
>On Mon, Mar 10, 2025 at 03:12:43PM +0200, Jani Nikula wrote:
>> On Fri, 07 Mar 2025, Gustavo Sousa wrote:
>> > Bandwidth parameters for Xe3_LPD have been updated with respect to
>> > previous display releases. Encode them into xe3lpd_sa_info and u
Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_display_irq.[ch] to struct
intel_display.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_irq.c | 527 --
1 file changed, 247 insertions(+), 28
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