On 2025-03-07 at 12:31:25 GMT, Chris Wilson wrote:
> Quoting Mikolaj Wasiak (2025-03-07 08:44:29)
> > Hi Krzysztof,
> >
> > On 2025-03-05 at 17:31:49 +0100, Krzysztof Niemiec wrote:
> > > Don't we run into the same issue as in V1, meaning we use an unknown
> > > current->active_mm (since we run in
== Series Details ==
Series: bits: Fixed-type GENMASK()/BIT() (rev2)
URL : https://patchwork.freedesktop.org/series/145997/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16245 -> Patchwork_145997v2
Summary
---
**SUCC
From: Ville Syrjälä
Move the bw_state->pipe_sagv_reject computation into intel_bw.c
where it belongs.
Previously we had a complicated dance between watermarks and
sagv which required this to be computed earlier, but that was
changed in commit 5e8146251f7b ("extract intel_bw_check_sagv_mask()")
w
On Fri, Mar 07, 2025 at 12:18:02PM -0500, Yury Norov wrote:
> No rush, please allow your reviewers a week or two before submitting
> a new iteration unless you want to disregard the previous version for
> some reason, of course. This will not get into the upcoming merge
> window, anyways.
>
> So,
== Series Details ==
Series: drm/dp_mst: Fix locking when skipping CSN before topology probing
URL : https://patchwork.freedesktop.org/series/146019/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16246 -> Patchwork_146019v1
== Series Details ==
Series: drm/i915: sagv/bw cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/146014/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16246 -> Patchwork_146014v2
Summary
---
**SUCCESS**
On 3/6/2025 10:08 PM, José Roberto de Souza wrote:
> Commit 255fc1703e42 ("drm/i915/gem: Calculate object page offset for partial
> memory mapping")
> was the last patch of several patches fixing multiple partial mmaps.
> But without a bump in I915_PARAM_MMAP_GTT_VERSION there is no clean
> way
On Sat, Mar 08, 2025 at 01:48:48AM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Vincent Mailhol
>
> In an upcoming change, GENMASK() and its friends will indirectly
> depend on sizeof() which is not available in asm.
>
> Instead of adding further complexity to __GENMASK() to make it work
>
From: Ville Syrjälä
Rename the intel_crtc_bw struct to intel_dbuf_bw to better
reflect what it does.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
From: Ville Syrjälä
The only thing between the current intel_bw_check_sagv_mask() call
site and intel_bw_atomic_check() is skl_wm_add_affected_planes()
which no longer depends on the sagv mask, so we can make life
a lot less confusing by calling intel_bw_check_sagv_mask() from
intel_bw_atomic_che
Bandwidth parameters for Xe3_LPD have been updated with respect to
previous display releases. Encode them into xe3lpd_sa_info and use that
new struct.
Bspec: 68859
Reviewed-by: Matt Roper
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c | 11 ++-
1 file changed,
== Series Details ==
Series: drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate
support for partial mmaps (rev4)
URL : https://patchwork.freedesktop.org/series/145945/
State : warning
== Summary ==
Error: dim checkpatch failed
e4a5570cfc5d drm/i915: Increase I915_PARAM_MMAP_GT
== Series Details ==
Series: drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate
support for partial mmaps (rev4)
URL : https://patchwork.freedesktop.org/series/145945/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16246 -> Patchwork_145945v4
==
Quoting Juha-Pekka Heikkila (2025-02-14 16:57:11)
> Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12, this
> is performance optimization.
>
> Bspec: 46132
>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411
> Signed-off-by: Juha-Pekka Heikkila
> ---
> drivers/gpu/
On Wed, 05 Mar 2025, Imre Deak wrote:
> Add support for blocking the IRQ handling on the HPD pin of a given
> encoder, handling IRQs that arrived while in the blocked state after
> unblocking the IRQ handling. This will be used by a follow-up change,
> which blocks/unblocks the IRQ handling around
On Tue, 04 Mar 2025, Imre Deak wrote:
> intel_hpd_disable/enable() have the same purpose as
> intel_hpd_block/unblock(), except that disable/enable will drop any HPD
> IRQs which were triggered while the HPD was disabled, while
> block/unblock will handle such IRQs after the IRQ handling is unbloc
== Series Details ==
Series: drm/i915/selftests: Re-enable power gating after live_selftest (rev3)
URL : https://patchwork.freedesktop.org/series/145144/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16245 -> Patchwork_145144v3
=
On Fri, Mar 07, 2025 at 07:11:42PM +0900, Vincent Mailhol wrote:
> On 07/03/2025 at 02:55, Andy Shevchenko wrote:
> > On Fri, Mar 07, 2025 at 01:08:15AM +0900, Vincent Mailhol wrote:
> >> On 06/03/2025 at 22:11, Andy Shevchenko wrote:
> >>> On Thu, Mar 06, 2025 at 08:29:58PM +0900, Vincent Mailhol
== Series Details ==
Series: bits: Fixed-type GENMASK()/BIT() (rev2)
URL : https://patchwork.freedesktop.org/series/145997/
State : warning
== Summary ==
Error: dim checkpatch failed
f96fba907aff bits: fix typo 'unsigned __init128' -> 'unsigned __int128'
fdc85516eb83 bits: split the definition
== Series Details ==
Series: bits: Fixed-type GENMASK()/BIT() (rev2)
URL : https://patchwork.freedesktop.org/series/145997/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR as described in workaround
for underrun on idle PSR HW issue (Wa_16025596647).
Bspec: 74151
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/d
This patchset is implementing workaround for underrun on idle PSR HW bug.
It is adding notification mechanisms toward PSR for pipe
enable/disable, vblank enable/disable and enabling disabling
DC5/DC6. These notifications are used to apply/remove the workaround.
Current mechanism to block DC state
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register
definitions.
Bspec: 67576
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 6 ++
1 file changed, 6 insertions(+)
di
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to have current configured DC state available. Add new interface
for this purpose.
Signed-off-by: Jouni Högander
---
.../drm/i915/display/intel_display_power.c| 29 +++
.../drm/i915/display/int
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This
patch implements mechanism to notify PSR about pipe enable/disable and
applies/removes the workaround using this notification.
Bspec: 74151
Signed-off-b
To implement Wa_16025596647 we need to get notification of vblank interrupt
enable/disable. Add new interface to PSR code for this notification.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 40
drivers/gpu/drm/i915/display/intel_psr.h | 2
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to know enabled. Figure out which non-PSR pipes we will have active
and store it into intel_crtc_state->active_non_psr_pipes. This is currently
assuming only one eDP on a time. I.e. possible secondary eDP with PSR
ca
We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for
underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW
register definitions.
Bspec: 71265
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 8
1 file changed, 8 inse
We have extended using vblank DC workaround mechanism for
Wa_16025596647. Rename related functions and variables:
vblank_wa_num_pipes -> vblank_enable_count
vblank_dc_work -> vblank_notify_work
intel_display_vblank_dc_work -> intel_display_vblank_notify_work
Signed-off-by: Jouni Högander
---
dr
On Thu, 06 Mar 2025, "Garg, Nemesa" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> @@ -0,0 +1,15 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/* Copyright © 2025 Intel Corporation */
>> +
>> +#ifndef __I915_GEM_OBJECT_H__
>> +#define __i915_GEM_OBJECT_H__
Quoting Mikolaj Wasiak (2025-03-07 08:44:29)
> Hi Krzysztof,
>
> On 2025-03-05 at 17:31:49 +0100, Krzysztof Niemiec wrote:
> > Don't we run into the same issue as in V1, meaning we use an unknown
> > current->active_mm (since we run in a kthread, and cannot control it) to
> > use as the current->m
== Series Details ==
Series: i915/gt/selftest_lrc: Disable timestamp test
URL : https://patchwork.freedesktop.org/series/145991/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16245 -> Patchwork_145991v1
Summary
---
*
On Fri, Mar 07, 2025 at 05:33:46PM +0530, Nautiyal, Ankit K wrote:
>
> On 3/6/2025 10:16 PM, Ville Syrjälä wrote:
> > On Thu, Mar 06, 2025 at 06:40:54PM +0530, Ankit Nautiyal wrote:
> >> During modeset enable sequence, program the fixed timings, and turn on the
> >> VRR Timing Generator (VRR TG) f
== Series Details ==
Series: drm/display: dp: add new DPCD access functions
URL : https://patchwork.freedesktop.org/series/145998/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Fri, Mar 07, 2025 at 02:02:15AM -0600, Lucas De Marchi wrote:
Hi Dave and Sima,
Last drm-xe-next pull request for 6.15. It comes with some big features
that we have been working on for some time: EU stall sampling and SVM.
The latter also touches other subsystems and provides the common parts
This patch is applying workaround for underrun on idle PSR HW issue
(Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable
status, DC5/6 enabled disabled and enabled pipes count information made
available.
This patch is also adding calls to dc5/dc6, vblank enable/disable and p
We need to ensure transcoder is supporting Selective Update in case of
Panel Replay as well.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/d
== Series Details ==
Series: Underrun on idle PSR workaround
URL : https://patchwork.freedesktop.org/series/145986/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16243 -> Patchwork_145986v1
Summary
---
**FAILURE**
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, 3 March 2025 14.52
> To: Kandpal, Suraj
> Cc: Jani Nikula ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
> Nautiyal,
> Ankit K ; Shankar, Uma ;
> Kahola, Mika
> Subject: Re: [PATCH 05/11] d
On 3/6/2025 10:16 PM, Ville Syrjälä wrote:
On Thu, Mar 06, 2025 at 06:40:54PM +0530, Ankit Nautiyal wrote:
During modeset enable sequence, program the fixed timings, and turn on the
VRR Timing Generator (VRR TG) for platforms that always use VRR TG.
For this intel_vrr_set_transcoder now alway
This test was supposed to show bug in tigerlake and dg2 hardware.
The bug was found and fixed in newer generations.
Since we won't support any new hardware with this driver, the test
should now be turned off in the CI to not polute it with random failures
on previous hardware.
Signed-off-by: Mikol
On Mon, 2025-03-03 at 14:05 +0530, Animesh Manna wrote:
> For every commit the dependent condition for LOBF is checked
> and accordingly update has_lobf flag which will be used
> to update the ALPM_CTL register during commit.
>
> v1: Initial version.
> v2: Avoid reading h/w register without has_lo
On Fri, Mar 07, 2025 at 06:34:42AM +0200, Dmitry Baryshkov wrote:
> Existing DPCD access functions return an error code or the number of
> bytes being read / write in case of partial access. However a lot of
> drivers either (incorrectly) ignore partial access or mishandle error
> codes. In other c
On Mon, 2025-03-03 at 14:05 +0530, Animesh Manna wrote:
> Add an interface in debugfs which will help in debugging LOBF
> feature.
>
> v1: Initial version.
> v2:
> - Remove FORCE_EN flag. [Jouni]
> - Change prefix from I915 to INTEL. [Jani]
> - Use u8 instead of bool for lobf-debug flag. [Jani]
>
== Series Details ==
Series: Remove aops->writepage
URL : https://patchwork.freedesktop.org/series/145995/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/145995/revisions/1/mbox/ not
applied
Applying: f2fs: Remove check for ->writepage
Applying: f
On 07/03/2025 at 22:27, David Laight wrote:
> On Fri, 7 Mar 2025 18:58:08 +0900
> Vincent Mailhol wrote:
>
>> On 07/03/2025 at 04:23, David Laight wrote:
>>> On Thu, 06 Mar 2025 20:29:52 +0900
>>> Vincent Mailhol via B4 Relay
>>> wrote:
>>>
From: Vincent Mailhol
(...)
+#define G
Mappings which implement writepages should not implement writepage
as it can only harm writeback patterns.
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/f2fs/data.c | 24
1 file changed, 24 deletions(-)
diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c
index a80d5ef9acbb..cd
On Mon, 2025-03-03 at 14:05 +0530, Animesh Manna wrote:
> Disable LOBF/ALPM for any erroneous condition from sink side.
>
> v1: Initial version.
> v2: Add centralized alpm error handling. [Jouni]
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 25
> +
On 06/03/2025 à 22:08, Andy Shevchenko wrote:
> On Thu, Mar 06, 2025 at 08:29:53PM +0900, Vincent Mailhol via B4 Relay wrote:
>> From: Yury Norov
>>
>> Add GENMASK_TYPE() which generalizes __GENMASK() to support different
>> types, and implement fixed-types versions of GENMASK() based on it.
>> Th
From: Dmitry Baryshkov
Switch drm_dp_helper.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_helper.c | 296 +---
1 file changed, 116 insertions(+), 180
From: Lucas De Marchi
Add some additional tests in lib/test_bits.c to cover the
expected/non-expected values of the fixed-type genmasks.
Also check that the result value matches the expected type. Since
those are known at build time, use static_assert() instead of normal
kunit tests.
Signed-off
On 05/03/2025 at 23:33, Andy Shevchenko wrote:
> On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol via B4 Relay wrote:
>> From: Lucas De Marchi
>>
>> Implement fixed-type BIT to help drivers add stricter checks, like was
>
> Here and in the Subject I would use BIT_Uxx().
>
>> done for GE
Hi Vincent!
On Wed, Mar 05, 2025 at 10:00:13PM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Vincent Mailhol
>
> "int" was misspelled as "init" in GENMASK_U128() comments. Fix the typo.
>
> Signed-off-by: Vincent Mailhol
Thanks for respinning the series. I'll take this fix in bitmap-for-
On Tue, Feb 25, 2025 at 01:39:23PM +0530, Suraj Kandpal wrote:
> Change the arguments for enable hook in intel_global_dpll_funcs to only
> accept crtc_state. This is because we really don't need those extra
> arguments everything can be derived from crtc_state and we need
> intel_encoder for PLL en
From: Vincent Mailhol
"int" was misspelled as "init" in GENMASK_U128() comments. Fix the typo.
Signed-off-by: Vincent Mailhol
---
include/linux/bits.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/bits.h b/include/linux/bits.h
index
61a75d3f294bfa96267383b5
== Series Details ==
Series: drm/i915/psr: Check transcoder Selective Update support for PR as well
URL : https://patchwork.freedesktop.org/series/145989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16245 -> Patchwork_145989v1
On 2025-03-07 at 12:31:25 +0100, Chris Wilson wrote:
> Quoting Mikolaj Wasiak (2025-03-07 08:44:29)
> > Hi Krzysztof,
> >
> > On 2025-03-05 at 17:31:49 +0100, Krzysztof Niemiec wrote:
> > > Don't we run into the same issue as in V1, meaning we use an unknown
> > > current->active_mm (since we run
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when DC5/6 is enabled/disabled. This patch implements
mechanism to notify PSR about DC5/6 enable/disable and applies/removes the
workaround using this notification.
Bspec: 74115
Signed-off-by: Jouni Högander
--
Scope of intel_psr_needs_block_dc_vblank has changed now. Rename it as
intel_psr_needs_vblank_notification. Also rename
intel_crtc::block_dc_for_vblank as intel_crtc:vblank_psr_notify
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++--
drivers/gpu/drm/i
This will be the replacement for shmem_writepage().
Signed-off-by: Matthew Wilcox (Oracle)
---
include/linux/shmem_fs.h | 7 ---
mm/shmem.c | 20 ++--
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/include/linux/shmem_fs.h b/include/linux/shmem
We're almost able to remove a_ops->writepage. This check is unnecessary
as we'll never call into __f2fs_write_data_pages() for character
devices.
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/f2fs/data.c | 4
1 file changed, 4 deletions(-)
diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c
inde
ed here, but some of the documentation was so out of date it
was hard to tell what was worth preserving.
Anyway, let's see what the bots make of this. This is against
next-20250307.
Matthew Wilcox (Oracle) (11):
f2fs: Remove check for ->writepage
f2fs: Remove f2fs_writ
The ->writepage operation is going away. Remove this alternative to
calling ->writepages.
Signed-off-by: Matthew Wilcox (Oracle)
---
mm/page-writeback.c | 28 ++--
1 file changed, 2 insertions(+), 26 deletions(-)
diff --git a/mm/page-writeback.c b/mm/page-writeback.c
in
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, 7 March 2025 15.07
> To: Kahola, Mika
> Cc: Kandpal, Suraj ; Jani Nikula
> ; intel...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; Syrjala, Ville ;
> Nautiyal, Ankit
> K ; Shankar, Uma
> Subject: Re: [PATCH 05/11]
If we add a migrate_folio operation, we can convert the writepage
operation to writepages. Further, this lets us optimise by using
the same write handle for multiple folios. The large folio support here
is illusory; we would need to kmap each page in turn for proper support.
But we do remove a fe
Mappings which implement writepages should not implement writepage
as it can only harm writeback patterns.
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/f2fs/node.c | 8
1 file changed, 8 deletions(-)
diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c
index 36614a1c2590..b78c1f95bc04 100644
The writepage callback is going away; filesystems must implement
migrate_folio or else dirty folios will not be migratable.
Signed-off-by: Matthew Wilcox (Oracle)
---
mm/migrate.c | 57
1 file changed, 4 insertions(+), 53 deletions(-)
diff --
Call swap_writeout() and shmem_writeout() from pageout() instead.
Signed-off-by: Matthew Wilcox (Oracle)
---
block/blk-wbt.c | 2 +-
mm/page_io.c| 3 +--
mm/shmem.c | 23 +--
mm/swap.h | 4 ++--
mm/swap_state.c | 1 -
mm/swapfile.c | 2 +-
mm/vmscan.c
Convert from an inefficient loop to the standard writeback iterator.
Signed-off-by: Matthew Wilcox (Oracle)
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 32 ++-
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/driv
Mappings which implement writepages should not implement writepage
as it can only harm writeback patterns.
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/f2fs/checkpoint.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c
index a35595f8d3f5..412
+ Anshuman Khandual
Anshuman,
I merged your GENMASK_U128() because you said it's important for your
projects, and that it will get used in the kernel soon.
Now it's in the kernel for more than 6 month, but no users were added.
Can you clarify if you still need it, and if so why it's not used?
From: Yury Norov
Add __GENMASK_t() which generalizes __GENMASK() to support different
types, and implement fixed-types versions of GENMASK() based on it.
The fixed-type version allows more strict checks to the min/max values
accepted, which is useful for defining registers like implemented by
i91
From: Vincent Mailhol
The definitions of GENMASK() and GENMASK_ULL() do not depend any more
on __GENMASK() and __GENMASK_ULL(). Duplicate the existing unit tests
so that __GENMASK{,ULL}() is still covered.
Signed-off-by: Vincent Mailhol
---
lib/test_bits.c | 18 ++
1 file chang
On 07/03/2025 at 02:55, Andy Shevchenko wrote:
> On Fri, Mar 07, 2025 at 01:08:15AM +0900, Vincent Mailhol wrote:
>> On 06/03/2025 at 22:11, Andy Shevchenko wrote:
>>> On Thu, Mar 06, 2025 at 08:29:58PM +0900, Vincent Mailhol via B4 Relay
>>> wrote:
From: Vincent Mailhol
Add some a
Introduce some fixed width variant of the GENMASK() and the BIT()
macros in bits.h. Note that the main goal is not to get the correct
type, but rather to enforce more checks at compile time. For example:
GENMASK_U16(16, 0)
will raise a build bug.
This series is a continuation of:
https://l
On 06/03/2025 at 04:45, Andy Shevchenko wrote:
>>> But GENMASK_U128() becomes a special case now.
>>> The 128-bit GENMASK is unsued, but it's exported in uapi. Is there any
>>> simple way to end up with a common implementation for all fixed-type
>>> GENMASKs?
>>
>> What bothers me is that the 128 b
Introduce some fixed width variant of the GENMASK() and the BIT()
macros in bits.h. Note that the main goal is not to get the correct
type, but rather to enforce more checks at compile time. For example:
GENMASK_U16(16, 0)
will raise a build bug.
This series is a continuation of:
https://l
From: Dmitry Baryshkov
Switch drm_dp_cec.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_cec.c | 37 ++--
1 file changed, 18 insertions(+), 19 delet
From: Dmitry Baryshkov
Switch drm_dp_aux_dev.c to use new set of DPCD read / write helpers.
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_aux_dev.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/displ
From: Vincent Mailhol
The definitions of GENMASK() and GENMASK_ULL() do not depend any more
on __GENMASK() and __GENMASK_ULL(). Duplicate the existing unit tests
so that __GENMASK{,ULL}() is still covered.
Signed-off-by: Vincent Mailhol
---
lib/test_bits.c | 18 ++
1 file chang
From: Yury Norov
Add GENMASK_TYPE() which generalizes __GENMASK() to support different
types, and implement fixed-types versions of GENMASK() based on it.
The fixed-type version allows more strict checks to the min/max values
accepted, which is useful for defining registers like implemented by
i9
From: Vincent Mailhol
Add some additional tests in lib/test_bits.c to cover the expected
results of the fixed type BIT_U*() macros.
Signed-off-by: Vincent Mailhol
---
Changelog
v4 -> v5:
- BIT_U8()/BIT_U16() are now back to u8/u16.
v3 -> v4:
- New patch.
---
lib/test_bits.c | 1
From: Dmitry Baryshkov
Switch drm_dp_tunnel.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_tunnel.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
d
On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Yury Norov
>
> Add __GENMASK_t() which generalizes __GENMASK() to support different
> types, and implement fixed-types versions of GENMASK() based on it.
> The fixed-type version allows more strict checks to the
On 06/03/2025 at 00:48, Andy Shevchenko wrote:
> On Wed, Mar 05, 2025 at 11:48:10PM +0900, Vincent Mailhol wrote:
>> On 05/03/2025 at 23:33, Andy Shevchenko wrote:
>>> On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol via B4 Relay
>>> wrote:
>
> ...
>
+#define BIT_U8(b) (BIT_INPUT_C
On 07/03/2025 at 04:23, David Laight wrote:
> On Thu, 06 Mar 2025 20:29:52 +0900
> Vincent Mailhol via B4 Relay
> wrote:
>
>> From: Vincent Mailhol
>>
>> In an upcoming change, GENMASK() and its friends will indirectly
>> depend on sizeof() which is not available in asm.
>>
>> Instead of adding
On 05/03/2025 at 23:30, Andy Shevchenko wrote:
> On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote:
>> From: Yury Norov
>>
>> Add __GENMASK_t() which generalizes __GENMASK() to support different
>
> Is it with double underscore? I do not see it.
This is my mistake. In
From: Dmitry Baryshkov
Existing DPCD access functions return an error code or the number of
bytes being read / write in case of partial access. However a lot of
drivers either (incorrectly) ignore partial access or mishandle error
codes. In other cases this results in a boilerplate code which com
From: Lucas De Marchi
Implement fixed-type BIT_U*() to help drivers add stricter checks,
like was done for GENMASK_U*().
Signed-off-by: Lucas De Marchi
Acked-by: Jani Nikula
Co-developed-by: Vincent Mailhol
Signed-off-by: Vincent Mailhol
---
Changelog:
v4 -> v5:
- Rename GENMASK_t()
On 06/03/2025 at 00:47, Yury Norov wrote:
> On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote:
>> From: Yury Norov
>>
>> Add __GENMASK_t() which generalizes __GENMASK() to support different
>> types, and implement fixed-types versions of GENMASK() based on it.
>> The fix
From: Vincent Mailhol
In an upcoming change, GENMASK() and its friends will indirectly
depend on sizeof() which is not available in asm.
Instead of adding further complexity to __GENMASK() to make it work
for both asm and non asm, just split the definition of the two
variants.
Signed-off-by: Vi
On 06/03/2025 at 23:34, Lucas De Marchi wrote:
> On Thu, Mar 06, 2025 at 08:29:52PM +0900, Vincent Mailhol via B4 Relay
> wrote:
(...)
> it seems we now have 1 inconsistency that we comment why
> GENMASK_U128() is not available in asm, but we don't comment why
> GENMASK_INPUT_CHECK() is not avail
On Thu, Mar 06, 2025 at 12:42:07PM +0200, Jani Nikula wrote:
> Side note, I often pipe messages from my MUA (notmuch-emacs) to b4, as
> it nicely parses the mails and picks up the message-id from
> there. Overall it works great. However, b4 seems to err on the side of
> writing color codes to pipes
From: Dmitry Baryshkov
Switch drm_dp_mst_topology.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 105 +-
1 file changed, 51 insertions(+),
From: Lucas De Marchi
Implement fixed-type BIT to help drivers add stricter checks, like was
done for GENMASK().
Signed-off-by: Lucas De Marchi
Acked-by: Jani Nikula
Signed-off-by: Vincent Mailhol
---
Changelog:
v3 -> v4:
- Use const_true() to simplify BIT_INPUT_CHECK().
- Make B
On Wed, 2025-03-05 at 19:52 +0200, Jani Nikula wrote:
> On Wed, 05 Mar 2025, "Knop, Ryszard" wrote:
> > Hey everyone,
> >
> > Patchwork has been having lots of issues recently, dropping patches,
> > being unusably slow and generally starting to become more of a pain
> > than help. Over on the CI
From: Lucas De Marchi
Now that include/linux/bits.h implements fixed-width GENMASK_U*(), use
them to implement the i915/xe specific macros. Converting each driver
to use the generic macros are left for later, when/if other
driver-specific macros are also generalized.
Signed-off-by: Lucas De Marc
On Wed, 5 Mar 2025 17:48:05 +0200
Andy Shevchenko wrote:
> On Wed, Mar 05, 2025 at 11:48:10PM +0900, Vincent Mailhol wrote:
> > On 05/03/2025 at 23:33, Andy Shevchenko wrote:
> > > On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol via B4 Relay
> > > wrote:
>
> ...
>
> > >> +#define
From: Lucas De Marchi
Add some additional tests in lib/test_bits.c to cover the
expected/non-expected values of the fixed-type GENMASK_U*() macros.
Also check that the result value matches the expected type. Since
those are known at build time, use static_assert() instead of normal
kunit tests.
On 06/03/2025 at 22:11, Andy Shevchenko wrote:
> On Thu, Mar 06, 2025 at 08:29:58PM +0900, Vincent Mailhol via B4 Relay wrote:
>> From: Vincent Mailhol
>>
>> Add some additional tests in lib/test_bits.c to cover the expected
>> results of the fixed type BIT_U*() macros.
>
> Still would be good to
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