On Tue, Jan 21, 2025 at 03:58:03PM -0800, Umesh Nerlige Ramappa wrote:
> On Tue, Jan 21, 2025 at 06:10:34PM -0500, Rodrigo Vivi wrote:
> > On Tue, Jan 21, 2025 at 02:25:57PM -0800, Umesh Nerlige Ramappa wrote:
> >
> > drm/i915/pmu as tag please...
>
> will do
>
> >
> > > When running igt@gem_ex
== Series Details ==
Series: i915/pmu: Fix zero delta busyness issue (rev2)
URL : https://patchwork.freedesktop.org/series/143815/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15999 -> Patchwork_143815v2
Summary
---
On 12/13/2024 11:01 PM, Ville Syrjälä wrote:
On Mon, Nov 11, 2024 at 02:41:58PM +0530, Ankit Nautiyal wrote:
Even though the VRR timing generator (TG) is primarily used for
variable refresh rates, it can be used for fixed refresh rates as
well. For a fixed refresh rate the Flip Line and Vmax m
On Wed, 22 Jan 2025, Vinod Govindapillai wrote:
> Dirty rectangle feature allows FBC to recompress a subsection
> of a frame. When this feature is enabled, display will read
> the scan lines between dirty rectangle start line and dirty
> rectangle end line in subsequent frames.
>
> v2: Move dirty
Start the xe-i915-display reconciliation by using the same
shutdown sequences.
v2: include the stubs for !CONFIG_DRM_XE_DISPLAY (Kunit)
Reviewed-by: Jonathan Cavitt
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/xe/display/xe_display.c | 48 +++--
drivers/gpu/drm/xe/displa
Move display related shutdown sequences from i915_driver to
intel_display_driver.
No functional change. Just taking the right ownership and
start some reconciliation of them between i915 and Xe.
v2: - Add missing _nogem caller (Imre)
- Fix comment style (Jonathan)
v3: rebase
v4: amend build f
This aligns with the current i915 display sequence.
Cc: Maarten Lankhort
Reviewed-by: Jonathan Cavitt
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/xe/display/xe_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/driv
On Wed, 22 Jan 2025, Vinod Govindapillai wrote:
> To avoid programming garbage to dirty rectangle registers,
> introduce a state variable to track the validity of the
> dirty rectangle update scenarios. Program the dirty rectangle
> coordinate only if this state variable is valid.
>
> Signed-off-b
Ensure drm headers build, are self-contained, have header guards, and
have no kernel-doc warnings, when CONFIG_DRM_HEADER_TEST=y.
The mechanism follows similar patters used in i915, xe, and usr/include.
To cover include/drm, we need to recurse there using the top level
Kbuild and the new include/
drm_client_event.h uses bool without types.h, include it.
Fixes: bf17766f1083 ("drm/client: Move suspend/resume into DRM client
callbacks")
Cc: Thomas Zimmermann
Signed-off-by: Jani Nikula
---
include/drm/drm_client_event.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_
Add CONFIG_DRM_HEADER_TEST to ensure drm headers are self-contained and
pass kernel-doc. And for starters, fix one header that this catches.
Jani Nikula (2):
drm/client: include types.h to make drm_client_event.h self-contained
drm: ensure drm headers are self-contained and pass kernel-doc
K
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Move shutdown sequences
under display driver
URL : https://patchwork.freedesktop.org/series/143844/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be chec
Hi Ingyu,
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index d60a6ca0cae5..8d22d8f2243d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -311,7 +311,7 @@ static struct intel_context *gen8_ggtt_b
On 1/22/2025 6:38 PM, Ville Syrjälä wrote:
On Wed, Jan 22, 2025 at 04:08:07PM +0530, Nautiyal, Ankit K wrote:
On 12/13/2024 11:01 PM, Ville Syrjälä wrote:
On Mon, Nov 11, 2024 at 02:41:58PM +0530, Ankit Nautiyal wrote:
Even though the VRR timing generator (TG) is primarily used for
variable
== Series Details ==
Series: drm/i915: Improve the display VT-d workarounds
URL : https://patchwork.freedesktop.org/series/143857/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16001 -> Patchwork_143857v1
Summary
---
On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> The DMC wakelock code needs to keep track of register offsets that need
> the wakelock for proper access. If one of the necessary offsets are
> missed, then the failure in asserting the wakelock is very likely to
> cause problems down the ro
On Wed, 22 Jan 2025, Vinod Govindapillai wrote:
> Programming of the dirty rectangle coordinates should happen
> within the scope of DSB prepare and finish calls. So call the
> compute and programming of dirty rectangle related routines
> early within the DSB programming window. Some of the FBC st
On Wed, 22 Jan 2025, Krzysztof Karas wrote:
> Hi Ingyu,
>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index d60a6ca0cae5..8d22d8f2243d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -31
On Wed, 2025-01-22 at 12:47 +0200, Jani Nikula wrote:
> On Wed, 22 Jan 2025, Vinod Govindapillai
> wrote:
> > Programming of the dirty rectangle coordinates should happen
> > within the scope of DSB prepare and finish calls. So call the
> > compute and programming of dirty rectangle related routi
== Series Details ==
Series: drm/i915/lspcon: do not hardcode settle timeout (rev4)
URL : https://patchwork.freedesktop.org/series/140116/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16001 -> Patchwork_140116v4
Summary
--
Set look ok to me and those missing ci results seem to never arrive..
Reviewed-by: Juha-Pekka Heikkila
On Wed, Dec 18, 2024 at 7:48 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Get rid of the 64bpp YUV formats on ICL+ SDR planes due to
> some weird underruns they're causing on TGL, and
On 1/22/2025 4:15 AM, Almahallawy, Khaled wrote:
Thank You for the series.
Tested a modeline that is not pre-computed and able to see pixel clock
calculation done correctly and the analyzer turns on:
adjusted mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443
1453 1474 0x48 0x9
crtc ti
Programming of the dirty rectangle coordinates should happen
within the scope of DSB prepare and finish calls. So call the
compute and programming of dirty rectangle related routines
early within the DSB programming window. Some of the FBC state
handling is done later as part of pre-plane or post-p
Dirty rect support for FBC in xe3 onwards based on the comments after the
initial RFC series.
v2: Dirty rect related compute and storage moved to fbc state (Ville)
V3: Dont call fbc activate if FBC is already active
v4: Dirty rect compute and programming moved within DSB scope
New changes ar
It is not recommended to have both FBC and PSR2 selective fetch
be enabled at the same time in a plane. If PSR2 selective fetch
or panel replay is on, mark FBC as not possible in that plane.
v2: fix the condition to disable FBC if PSR2 enabled (Jani)
Bspec: 68881
Signed-off-by: Vinod Govindapilla
Dirty rectangle feature allows FBC to recompress a subsection
of a frame. When this feature is enabled, display will read
the scan lines between dirty rectangle start line and dirty
rectangle end line in subsequent frames.
v2: Move dirty rect handling to fbc state (Ville)
Bspec: 71675, 73424
Sign
If FBC is already active, we don't need to call FBC activate
routine again during the post plane update. As this will
explicitly call the nuke and also rewrite the FBC ctl registers.
Xe doesn't support legacy fences. Hence fence programming also
not required as part of this fbc_haw_activate.
"inte
Register definitions for FBC dirty rect support
Bspec: 71675, 73424
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
b/drivers/gpu/drm/i915/display/inte
On Mon, 20 Jan 2025, Ankit Nautiyal wrote:
> Add C10 register bits to be used for computing HDMI PLLs with
> algorithm.
>
> v2: Add bspec reference. (Suraj)
>
> Bspec: 74166
> Signed-off-by: Ankit Nautiyal
> Reviewed-by: Suraj Kandpal
> ---
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 +
On Wed, Jan 22, 2025 at 04:08:07PM +0530, Nautiyal, Ankit K wrote:
>
> On 12/13/2024 11:01 PM, Ville Syrjälä wrote:
> > On Mon, Nov 11, 2024 at 02:41:58PM +0530, Ankit Nautiyal wrote:
> >> Even though the VRR timing generator (TG) is primarily used for
> >> variable refresh rates, it can be used f
== Series Details ==
Series: drm/i915: Improve the display VT-d workarounds
URL : https://patchwork.freedesktop.org/series/143857/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Tue, Jan 21, 2025 at 02:40:16PM +0100, Alexander Gordeev wrote:
> On Fri, Jan 10, 2025 at 03:16:08PM +0100, Joel Granados wrote:
>
> Hi Joel,
>
> > Add the const qualifier to all the ctl_tables in the tree except for
> > watchdog_hardlockup_sysctl, memory_allocation_profiling_sysctls,
> > load
== Series Details ==
Series: drm: add header tests
URL : https://patchwork.freedesktop.org/series/143853/
State : warning
== Summary ==
Error: dim checkpatch failed
282b1c214450 drm/client: include types.h to make drm_client_event.h
self-contained
6cafae5be8dc drm: ensure drm headers are self
== Series Details ==
Series: drm: add header tests
URL : https://patchwork.freedesktop.org/series/143853/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./arch/x86/include/asm/bitops.h:116:1: warning: un
== Series Details ==
Series: drm: add header tests
URL : https://patchwork.freedesktop.org/series/143853/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16001 -> Patchwork_143853v1
Summary
---
**FAILURE**
Serious u
== Series Details ==
Series: drm/i915/xe3: FBC Dirty rect feature support (rev5)
URL : https://patchwork.freedesktop.org/series/141527/
State : warning
== Summary ==
Error: dim checkpatch failed
35c76b1e5939 drm/i915/xe3: avoid calling fbc activate if fbc is active
ed4125786d32 drm/i915/xe3: a
== Series Details ==
Series: drm/i915/xe3: FBC Dirty rect feature support (rev5)
URL : https://patchwork.freedesktop.org/series/141527/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
> On Wed, Jan 08, 2025 at 11:09:00AM +0530, Arun R Murthy wrote:
> > Expose drm plane function to create formats/modifiers blob. This
> > function can be used to expose list of supported formats/modifiers for
> > sync/async flips.
> >
> > Signed-off-by: Arun R Murthy
> > ---
> > drivers/gpu/drm/d
From: Ville Syrjälä
Currently we don't account for the VT-d alignment w/a in
plane->min_alignment() which means that panning inside a larger
framebuffer can still cause the plane SURF to be misaligned.
Fix the issue by moving the VT-d alignment w/a into
plane->min_alignment() itself (for the affe
From: Ville Syrjälä
Currently i915_gem_object_pin_to_display_plane() uses
i915_gem_object_get_tile_row_size() to calculate the tile row
size for the VT-d guard w/a. That's not really proper since
i915_gem_object_get_tile_row_size() only works for fenced BOs,
nor does it take rotation into account
From: Ville Syrjälä
Depending on the platform and/or plane type we can get away
with a bit less alignment in the VT-d w/a. Reduce the numbers
accordingly.
Note that it's not actually clear in VLV/CHV need this w/a,
and if they do we don't actually know what kind of alignment
is sufficient. Leave
From: Ville Syrjälä
Bspec lists different VT-d guard numbers (the number of dummy
padding PTEs) for different platforms and plane types. Use those
instead of just assuming the max glk+ number for everything.
This could avoid a bit of overhead on older platforms due to
reduced padding, and it make
From: Ville Syrjälä
Grab the GTT view for the fbdev fb pinning from
fb->normal_view.gtt instead of having and extra one on
the stack. Seems safer in case we ever put any new
information into normal GTT views.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 5 +
From: Ville Syrjälä
Try to make the display VT-d workarounds more robust.
Ville Syrjälä (5):
drm/i915: Move VT-d alignment into plane->min_alignment()
drm/i915: Use more optimal VTd alignment for planes
drm/i915: Calculate the VT-d guard size in the display code
drm/i915: Use per-plane V
== Series Details ==
Series: drm/i915/xe3: FBC Dirty rect feature support (rev5)
URL : https://patchwork.freedesktop.org/series/141527/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15999 -> Patchwork_141527v5
Summary
-
On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> We already have a way of finding the set of untracked offsets for which
> there has been one or more MMIO operations via the
> "intel_dmc_wl/untracked" debugfs interface.
>
> However, in order to try adding one or more of those registers to
To avoid programming garbage to dirty rectangle registers,
introduce a state variable to track the validity of the
dirty rectangle update scenarios. Program the dirty rectangle
coordinate only if this state variable is valid.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/in
== Series Details ==
Series: drm/i915/selftests: Correct frequency handling in RPS power measurement
(rev4)
URL : https://patchwork.freedesktop.org/series/143213/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15984 -> Patchwork_143213v4
===
On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> We use a spinlock to protect DMC wakelock debugfs data, since it is also
> accessed by the core DMC wakelock logic. Taking the spinlock when the
> debugfs is not in use introduces a small but unnecessary penalty.
>
> Since the debugfs funct
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Move shutdown sequences
under display driver
URL : https://patchwork.freedesktop.org/series/143844/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15999 -> Patchwork_143844v1
Add C10 register bits to be used for computing HDMI PLLs with
algorithm.
v2: Add bspec reference. (Suraj)
v3: Use REG_BIT8 like other reg bits/masks. (Jani)
Bspec: 74166
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24
The CMTG is a timing generator that runs in parallel with transcoders
timing generators and can be used as a reference for synchronization.
We have observed that we are inheriting from GOP a display configuration
with the CMTG enabled. Because our driver doesn't currently implement
any CMTG sequen
On Wed, 2025-01-22 at 20:13 +0200, Ville Syrjälä wrote:
> On Wed, Jan 22, 2025 at 11:30:01AM +0200, Vinod Govindapillai wrote:
> > If FBC is already active, we don't need to call FBC activate
> > routine again during the post plane update. As this will
> > explicitly call the nuke and also rewrite
On Wed, Jan 22, 2025 at 11:30:01AM +0200, Vinod Govindapillai wrote:
> If FBC is already active, we don't need to call FBC activate
> routine again during the post plane update. As this will
> explicitly call the nuke and also rewrite the FBC ctl registers.
> Xe doesn't support legacy fences. Hence
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Move shutdown sequences
under display driver (rev2)
URL : https://patchwork.freedesktop.org/series/143844/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't
On Wed, Jan 22, 2025 at 11:30:04AM +0200, Vinod Govindapillai wrote:
> Dirty rectangle feature allows FBC to recompress a subsection
> of a frame. When this feature is enabled, display will read
> the scan lines between dirty rectangle start line and dirty
> rectangle end line in subsequent frames.
On Wed, Jan 22, 2025 at 11:03:57AM +0530, Suraj Kandpal wrote:
> Extended wake timeout request helps to give additional
> time by reading the DPCD register through which sink requests the
> minimal amount of time required to wake the sink up.
> Source device shall keep retying the AUX tansaction t
== Series Details ==
Series: Add HDMI PLL Algorithm for SNPS/C10PHY (rev5)
URL : https://patchwork.freedesktop.org/series/135397/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16001 -> Patchwork_135397v5
Summary
---
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Move shutdown sequences
under display driver (rev2)
URL : https://patchwork.freedesktop.org/series/143844/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16002 -> Patchwork_143844v2
=
== Series Details ==
Series: drm/i915/cmtg: Disable the CMTG (rev8)
URL : https://patchwork.freedesktop.org/series/142947/
State : warning
== Summary ==
Error: dim checkpatch failed
c66a6e106e08 drm/i915/cmtg: Disable the CMTG
-:83: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), d
== Series Details ==
Series: drm/i915/cmtg: Disable the CMTG (rev8)
URL : https://patchwork.freedesktop.org/series/142947/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/cmtg: Disable the CMTG (rev8)
URL : https://patchwork.freedesktop.org/series/142947/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16002 -> Patchwork_142947v8
Summary
---
**FAILU
On Wed, 22 Jan 2025, "Nautiyal, Ankit K" wrote:
> On 1/22/2025 4:15 AM, Almahallawy, Khaled wrote:
>> Thank You for the series.
>> Tested a modeline that is not pre-computed and able to see pixel clock
>> calculation done correctly and the analyzer turns on:
>>
>> adjusted mode: "3440x1440": 50 26
Hi all,
On Wed, 8 Jan 2025 12:16:50 +1100 Stephen Rothwell
wrote:
>
> On Mon, 6 Jan 2025 13:03:48 +1100 Stephen Rothwell
> wrote:
> >
> > Today's linux-next merge of the drm-intel tree got a conflict in:
> >
> > drivers/gpu/drm/i915/display/intel_display_driver.c
> >
> > between commit:
>
== Series Details ==
Series: Add HDMI PLL Algorithm for SNPS/C10PHY (rev5)
URL : https://patchwork.freedesktop.org/series/135397/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitop
== Series Details ==
Series: Add HDMI PLL Algorithm for SNPS/C10PHY (rev5)
URL : https://patchwork.freedesktop.org/series/135397/
State : warning
== Summary ==
Error: dim checkpatch failed
3e4ddea43f88 drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for
DG2
-:48: WARNING:FILE_PA
Quoting Patchwork (2025-01-22 18:00:52-03:00)
>== Series Details ==
>
>Series: drm/i915/cmtg: Disable the CMTG (rev8)
>URL : https://patchwork.freedesktop.org/series/142947/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_16002 -> Patchwork_142947v8
>
Hello Brian, Many thanks for the fix. I am adding my tested-by.
Tested-by: Vidya Srinivas
> -Original Message-
> From: Brian Geffon
> Sent: 16 January 2025 21:24
> To: intel-gfx@lists.freedesktop.org
> Cc: Wilson, Chris P ; Saarinen, Jani
> ; Mistat, Tomasz ;
> Srinivas, Vidya ; ville.s
Hi,
The below failure is not related to the patch series.
The test was passing in previous revision v4:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v4/bat-adlp-9/igt@i915_selft...@live.html
The v5 is just a minor change in macro in patch#2, sent in-reply-to it,
so both versions
On 1/22/2025 10:22 PM, Jani Nikula wrote:
On Wed, 22 Jan 2025, "Nautiyal, Ankit K" wrote:
On 1/22/2025 4:15 AM, Almahallawy, Khaled wrote:
Thank You for the series.
Tested a modeline that is not pre-computed and able to see pixel clock
calculation done correctly and the analyzer turns on:
a
== Series Details ==
Series: drm/i915/pmu: Drop custom hotplug code (rev2)
URL : https://patchwork.freedesktop.org/series/143636/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16004 -> Patchwork_143636v2
Summary
---
== Series Details ==
Series: drm/i915/cmtg: Disable the CMTG (rev8)
URL : https://patchwork.freedesktop.org/series/142947/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16002 -> Patchwork_142947v8
Summary
---
**SUCCE
== Series Details ==
Series: drm/i915/pmu: Drop custom hotplug code (rev2)
URL : https://patchwork.freedesktop.org/series/143636/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
> > On Wed, Jan 08, 2025 at 11:09:00AM +0530, Arun R Murthy wrote:
> > > Expose drm plane function to create formats/modifiers blob. This
> > > function can be used to expose list of supported formats/modifiers
> > > for sync/async flips.
> > >
> > > Signed-off-by: Arun R Murthy
> > > ---
> > > d
== Series Details ==
Series: drm/i915/dp: Guarantee a minimum HBlank time (rev10)
URL : https://patchwork.freedesktop.org/series/139267/
State : warning
== Summary ==
Error: dim checkpatch failed
e4465fa2630c drm/i915/dp: Guarantee a minimum HBlank time
-:159: WARNING:LONG_LINE: line length of
== Series Details ==
Series: drm/i915/dp: Guarantee a minimum HBlank time (rev10)
URL : https://patchwork.freedesktop.org/series/139267/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15998 -> Patchwork_139267v10
Summary
---
On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> We will add another function that checks the offset in an upcoming
> change. Instead of passing the reg variable to only extract the offset
> later, let's extract the offset before so that we do not need to repeat
> ourselves.
>
> Signed-of
On 13-01-2025 15:29, Sk Anirban wrote:
Previously, the RPS function was being used, which utilizes
raw frequency to calculate measured power. This commit introduces
a dedicated function specifically for measuring power in SLPC,
ensuring more accurate and reliable power measurements.
Signed-off
On 13-01-2025 15:29, Sk Anirban wrote:
Fix the frequency calculation by ensuring it uses the raw frequency only.
Update live_rps_power test to use the correct frequency values for logging
and comparison.
Signed-off-by: Sk Anirban
---
drivers/gpu/drm/i915/gt/selftest_rps.c | 2 +-
1 file ch
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