== Series Details ==
Series: drm/i915/dp: Add FEC Enable Retry mechanism (rev3)
URL : https://patchwork.freedesktop.org/series/138963/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15573 -> Patchwork_138963v3
Summary
--
== Series Details ==
Series: drm/i915/display: platform identification with
display->platform. (rev2)
URL : https://patchwork.freedesktop.org/series/139302/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/display: platform identification with
display->platform. (rev2)
URL : https://patchwork.freedesktop.org/series/139302/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15573 -> Patchwork_139302v2
=
== Series Details ==
Series: Add support for 3 VDSC engines 12 slices (rev4)
URL : https://patchwork.freedesktop.org/series/139934/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15571_full -> Patchwork_139934v4_full
Summary
== Series Details ==
Series: drm/i915/psr: vbt.psr.enable is only for eDP panels
URL : https://patchwork.freedesktop.org/series/140233/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15569 -> Patchwork_140233v1
Summary
-
> -Original Message-
> From: Intel-gfx On Behalf Of
> Gustavo Sousa
> Sent: Friday, October 18, 2024 2:23 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: [PATCH] drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to
> include tx_misc
>
> There has been
We will be using more than one range table in
intel_dmc_wl_check_range(). As such, move the logic to a new function
and name it intel_dmc_wl_addr_in_range().
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 22 ++---
1 file changed, 11 insertions(+),
Allow simpler syntax for defining entries for single registers in range
tables. That makes them easier to type as well as to read, allowing one
to quickly tell whether a range actually refers to a single register or
a "true range".
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/in
We are currently using ARRAY_SIZE() to iterate address ranges in
intel_dmc_wl_check_range(). In upcoming changes, we will be using more
than a single table and will extract the range checking logic into a
dedicated function that takes a range table as argument. As we will not
able to use ARRAY_SIZE
There are extra registers that require the DMC wakelock when specific
dynamic DC states are in place. Add the table ranges for them and use
the correct table depending on the allowed DC states.
Bspec: 71583
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 112 ++
It is possible that there are active wakelock references at the time we
are disabling the DMC wakelock mechanism. We need to deal with that in
two ways:
(A) Implement the missing step from Bspec:
The Bspec instructs us to clear any existing wakelock request bit
after disabling the mechani
In order to be able to use the DMC wakelock, we also need to know that
the display hardware has support for DMC, which is a runtime info.
Define HAS_DMC_WAKELOCK(), which checks for both DMC availability and IP
version, and use it in place of directly checking the display version.
Since we depend
Although Bspec doesn't explicitly mentions that, as of Xe3_LPD, using
DMC wakelock is the officially recommended way of accessing registers
that would be off during DC5/DC6 and the legacy method (where the DMC
intercepts MMIO to wake up the hardware) is to be avoided.
As such, update the driver to
Bspec says that disabling dynamic DC states require taking the DMC
wakelock to cause an DC exit before writing to DC_STATE_EN. Implement
that.
In fact, testing on PTL revealed we end up failing to exit DC5/6 without
this step.
Bspec: 71583
Signed-off-by: Gustavo Sousa
---
.../drm/i915/display/i
When the DMC wakelock refcount reaches zero, we know that there are no
users and that we can do the actual release operation on the hardware,
which is queued with a delayed work. The idea of the delayed work is to
avoid performing the release if a new lock user appears (i.e. refcount
gets increment
Some display MMIO transactions for offsets in the range that requires
the DMC wakelock happen in atomic context (this has been confirmed
during tests on PTL). That means that we need to use a non-sleeping
variant of MMIO waiting function.
Implement __intel_de_wait_for_register_atomic_nowl() and us
Enabling and disabling the DMC wakelock should be done as part of
enabling and disabling of dynamic DC states, respectively. We should not
enable or disable DMC wakelock independently of DC states, otherwise we
would risk ending up with an inconsistent state where dynamic DC states
are enabled and
Instead of checking for HAS_DMC_WAKELOCK() multiple times, let's use it
to sanitize the enable_dmc_wl parameter and use that variable when
necessary.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 21 ++---
1 file changed, 14 insertions(+), 7 delet
In upcoming display changes, we will modify the DMC wakelock MMIO
waiting code to choose a non-sleeping variant implementation, because
the wakelock is also taking in atomic context.
While xe provides an explicit parameter (namely "atomic") to prevent
xe_mmio_wait32() from sleeping, i915 does not
Using the DMC wakelock is the official recommendation for Xe3_LPD. This
series apply fixes to the current DMC wakelock implementation and
enables it by default for Xe3_LPD. The series has been tested with a PTL
machine.
Gustavo Sousa (13):
drm/xe: Mimic i915 behavior for non-sleeping MMIO wait
During GuC reset prepare, interrupt disabled before hardware reset,
although interrupt disabled, the ct is still enabled, the host-GuC
communication is still active.
Move the destroy part to the end of reset preparation to avoid the
situation of host processing G2H messages about an context, but th
During GuC reset prepare, interrupt disabled before hardware reset,
although interrupt disabled, the ct is still enabled, the host-GuC
communication is still active.
Move the destroy part to the end of reset preparation to avoid the
situation of host processing G2H messages about an context, but th
== Series Details ==
Series: drm/i915/dmc_wl: Fixes and enablement for Xe3_LPD
URL : https://patchwork.freedesktop.org/series/140282/
State : warning
== Summary ==
Error: dim checkpatch failed
22a0e1dad66b drm/xe: Mimic i915 behavior for non-sleeping MMIO wait
21b66390096d drm/i915/dmc_wl: Use
== Series Details ==
Series: drm/i915/dmc_wl: Fixes and enablement for Xe3_LPD
URL : https://patchwork.freedesktop.org/series/140282/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hi Jouni,
On 10/21/2024 1:03 PM, Jouni Högander wrote:
We don't want to check vbt.psr.enable on DP Panel Replay as it is targeted
for eDP panel usage only.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
dif
We don't want to check vbt.psr.enable on DP Panel Replay as it is targeted
for eDP panel usage only.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drive
Quoting Matt Atwood (2024-10-18 17:49:32-03:00)
>From: Dnyaneshwar Bhadane
>
>When deciding the type of the phy, Add PTL support to make
s/Add/add/
>sure the correct path is taken for selection of C10 PHY.
>Only port A is connected C10 PHY for Pantherlake.
>
>Bspec: 72571
>Signed-off-by: Dnyane
On Fri, 18 Oct 2024, Matt Atwood wrote:
> From: Mika Kahola
>
> There is a HW issue that arises when there are race conditions
> between TCSS entering/exiting TC7 or TC10 states while the
> driver is asserting/deasserting TCSS power request. As a
> workaround, Display driver will implement a mail
== Series Details ==
Series: Add AS_SDP to fastset (rev2)
URL : https://patchwork.freedesktop.org/series/137035/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warnin
== Series Details ==
Series: Add AS_SDP to fastset (rev2)
URL : https://patchwork.freedesktop.org/series/137035/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15571 -> Patchwork_137035v2
Summary
---
**FAILURE**
Se
On Mon, 21 Oct 2024, Gustavo Sousa wrote:
> Quoting Matt Atwood (2024-10-18 17:49:32-03:00)
>>From: Dnyaneshwar Bhadane
>>
>>When deciding the type of the phy, Add PTL support to make
>
> s/Add/add/
>
>>sure the correct path is taken for selection of C10 PHY.
>>Only port A is connected C10 PHY fo
Hi Suraj,
Thanks for the review and comments.
I agree with most of the comments on the series and will send new
version with those addressed.
Please find my explanation inline for your query:
On 10/18/2024 7:47 AM, Kandpal, Suraj wrote:
-Original Message-
From: Nautiyal, Ankit K
== Series Details ==
Series: Add support for 3 VDSC engines 12 slices (rev4)
URL : https://patchwork.freedesktop.org/series/139934/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15571 -> Patchwork_139934v4
Summary
---
On Mon, 21 Oct 2024, Chaitanya Kumar Borah
wrote:
> Currently, even though there is a bit to control FEC enable/disable
> individually, the FEC Decode Enable sequence is sent by the SOC only
> once TRANS_CONF enable is set. This ties the FEC enabling too tightly
> to modeset and therefore cannot
Quoting Saarinen, Jani (2024-10-18 03:00:58-03:00)
>Hi,
>
>> -Original Message-
>> From: Intel-gfx On Behalf Of
>> Patchwork
>> Sent: Friday, 18 October 2024 2.01
>> To: Sousa, Gustavo
>> Cc: intel-gfx@lists.freedesktop.org
>> Subject: ✗ Fi.CI.BAT: failure for drm/i915/xe2lpd: Update C20
On Mon, 21 Oct 2024, Ankit Nautiyal wrote:
> Add macro for Pixel replication support with DSC.
Add blank line here.
> Bspec: 49259, 68912.
>
Remove blank line here.
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++
> 1 file changed, 3 insert
Currently, even though there is a bit to control FEC enable/disable
individually, the FEC Decode Enable sequence is sent by the SOC only
once TRANS_CONF enable is set. This ties the FEC enabling too tightly
to modeset and therefore cannot be re-issued (in case of failure)
without a modeset.
>From
Quoting Matt Atwood (2024-10-18 17:03:06-03:00)
>From: Radhakrishna Sripada
>
>Xe3_LPD has new max cdclk of 691200 which requires reusing the lnl table
>and modify/add higher frequencies. Updating the max cdclk supported by
>the platform and voltage_level determination is also updated.
>
>There ar
On Mon, 21 Oct 2024, Ankit Nautiyal wrote:
> At the moment dsc_split represents that dsc splitter is used or not.
> With 3 DSC engines, the splitter can split into two streams or three
> streams. Make the member dsc_split as int and set that to 2 when dsc
> splitter splits to 2 stream.
Maybe also
Quoting Jani Nikula (2024-10-21 09:29:30-03:00)
>On Thu, 17 Oct 2024, Gustavo Sousa wrote:
>> There has been an update to the Bspec in which we need to set
>> tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for
>> Xe2_LPD and newer. That field is mapped to the bits 7:0 of
>> SRAM_GE
> -Original Message-
> From: Sousa, Gustavo
> Sent: Monday, 21 October 2024 15.31
> To: Atwood, Matthew S ; intel-
> g...@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Kahola, Mika ; Atwood, Matthew S
>
> Subject: Re: [PATCH 12/12] drm/i915/xe3lpd: Power request
> asserting/
== Series Details ==
Series: Add support for 3 VDSC engines 12 slices (rev4)
URL : https://patchwork.freedesktop.org/series/139934/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add support for 3 VDSC engines 12 slices (rev4)
URL : https://patchwork.freedesktop.org/series/139934/
State : warning
== Summary ==
Error: dim checkpatch failed
321ae3da8cc9 drm/i915/dp: Update Comment for Valid DSC Slices per Line
ad2c11146440 drm/i915/display: P
vrr enable disable should happen with fastset, where
adptive sync SDP should not block it to full modeset.
Mitul Golani (3):
drm/i915/vrr: Update vrr.vsync_{start,end} computation
drm/i915/dp: Set FAVT mode in DP SDP with fixed refresh rate
drm/i915/dp: Compute as_sdp based on if vrr possibl
While running with fixed refresh rate and VRR timing generator set FAVT
mode (Fixed Vtotal) in DP Adaptive Sync SDP to intimate the panel
about Fixed refresh rate.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 ins
vrr.vsync_{start,end} computation should not depend on
crtc_state->vrr.enable. Also add them to state dump.
--v1:
- Explain commit message more clearly [Jani]
- Instead of tweaking to fastset use vrr.flipline while computing AS_SDP.
--v2:
- Correct computation of vrr.vsync_start/end should not
Adaptive sync sdp param computation, specifically minimum vtotal is
blocking vrr enable and disable fastset requirements in certain scenario
i.e. during null modeset, this minimum vtotal we can configure during
full modeset as well when sink is having vrr support, where it doesn't
need dependency o
On Mon, 21 Oct 2024, Gustavo Sousa wrote:
> Quoting Jani Nikula (2024-10-21 09:29:30-03:00)
>>On Thu, 17 Oct 2024, Gustavo Sousa wrote:
>>> There has been an update to the Bspec in which we need to set
>>> tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for
>>> Xe2_LPD and newer. T
On Mon, 30 Sep 2024 15:02:58 +0200, Thomas Zimmermann wrote:
> DRM's aperture helpers are merely wrappers around the respective
> helpers in drivers/video/. The DRM interface existed first, but was
> later generalized for use with fbdev and a few other graphics-related
> places in the kernel. It
On Fri, 18 Oct 2024, Matt Atwood wrote:
> From: Suraj Kandpal
>
> Read PICA register to see if edp over type C is possible and then
> add the appropriate tables for it.
>
> --v2
> -remove bool from intel_encoder have it in runtime_info [Jani]
> -initialize the bool in runtime_info init [Jani]
> -
Quoting Matt Atwood (2024-10-18 17:49:35-03:00)
>From: "Heikkila, Juha-pekka"
>
>Xe3 has no more support for x-tile on display.
>
>Signed-off-by: Heikkila, Juha-pekka
>Signed-off-by: Matt Atwood
>---
> drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Thu, 17 Oct 2024, Gustavo Sousa wrote:
> There has been an update to the Bspec in which we need to set
> tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for
> Xe2_LPD and newer. That field is mapped to the bits 7:0 of
> SRAM_GENERIC__TX_CNTX_CFG_1, which in turn translates to tx[
Quoting Matt Atwood (2024-10-18 17:49:41-03:00)
>From: Mika Kahola
>
>There is a HW issue that arises when there are race conditions
>between TCSS entering/exiting TC7 or TC10 states while the
>driver is asserting/deasserting TCSS power request. As a
>workaround, Display driver will implement a ma
Hi Rodrigo,
On Fri, Oct 11, 2024 at 05:41:10PM -0400, Rodrigo Vivi wrote:
> Also update the function names in the documentation.
>
> Reported-by: Stephen Rothwell
> Closes:
> https://lore.kernel.org/intel-gfx/20241001134331.7b4d4...@canb.auug.org.au/
> Fixes: 3de5774cb8c0 ("drm/i915/irq: Rename
Enhance the `intel_splitter_adjust_pipe_width` helper to account for
both pixel replication and odd pixels. When the display width is
divided among multiple pipes, extra pixels can make the pipe source
width odd. Since hardware expects an even width, an extra pixel is
added to each pipe to ensure e
Add the extra pixels to the hactive while computing overhead with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +--
drivers/gpu/drm/i915/display/intel_vdsc.c | 23 +
d
With 3 DSC engines we can support 12 slices. With ultra joiner
usecase while dividing the width into 12 slices, we might
end up having odd number of pixels per pipe.
As per Bspec, pipe src size should be even, so an extra pixel is added
in each pipe. For Pipe A and C the odd pixel is added at the
Allow DSC slice count that do not divide the hactive evenly by adding
extra pixels (replicated pixels).
Check if the pixel replication is supported and store the no. of
replicated pixel count in crtc_state.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++
Check if Odd pixel is required during DSC compute config and update
the crtc_state to track the presence of odd pixels.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_d
Add macro for Pixel replication support with DSC.
Bspec: 49259, 68912.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/
According to the DSC spec, the slice width should be chosen such that
the picture width (hactive) is evenly divisible by the slice width.
If not, extra pixels (padding) must be added to the last slice to
ensure all slices have the same width.
Currently, we do not support handling these extra pixel
Certain resolutions require 12 DSC slices support along with ultrajoiner.
For such cases, the third DSC Engine per Pipe is enabled. Each DSC
Engine processes 1 Slice, resulting in a total of 12 VDSC slices
(4 Pipes * 3 DSC Instances per Pipe).
Add support for 12 DSC slices and 3 DSC engines for suc
With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS
registers for the 3rd DSC engine
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +---
drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 6 ++
2 files c
With 3 VDSC engines and Ultrajoiner, we may encounter a situation where
hactive is not a multiple of slice count. In this case we need to add
extra pixels to the last slice to distribute pixels evenly across
slices.
Add member to store DSC pixel replication when hactive is not divisible
by slice c
For BMG 3 VDSC engines are supported and each pipe can then support
3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require
ultrajoiner and 3 x 4= 12 slices.
Add support for 3 VDSC engines and 12 DSC slices. Along with this
Pixel replication and Odd pixel considerartions are also requi
At the moment dsc_split represents that dsc splitter is used or not.
With 3 DSC engines, the splitter can split into two streams or three
streams. Make the member dsc_split as int and set that to 2 when dsc
splitter splits to 2 stream.
v2: Avoid new enum for dsc split. (Suraj)
Signed-off-by: Anki
Include the extra pixels added while computing bandwidth with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915
With DSC pixel replication, extra pixels are added in the last slice
of the last pipe. Due to this the total hactive gets increased by few
pixels. Adjust the computation for pipe source width to account for
pixel replication.
These extra pixels will be take care by the Splitter logic in
hardware.
Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead.
While at it, use REG_BIT macro for the bits.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 8
drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 4 ++--
2 files
For some platforms, the maximum slices per DSC engine is 4, while for
others it is 2. Update the comment to reflect this and clarify that
the 'valid_dsc_slicecount' list represents the valid number of slices
per pipe.
Currently, we are working with 1, and 2 slices per DSC engine,
which works for a
Introduce the register bits to enable the 3rd DSC engine VDSC2.
Add support to read/write these bits.
v2: Only introduce bits that are used and update the subject and commit
message. (Suraj)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 20 +++
Quoting Matt Atwood (2024-10-18 17:03:05-03:00)
>From: Matt Roper
>
>There are some minor changes to pmdemand handling on Xe3:
> - Active scalers are no longer tracked. We can simply skip the readout
> and programming of this field.
> - Active dbuf slices are no longer tracked. We should skip
v4 of https://lore.kernel.org/r/cover.1727699233.git.jani.nik...@intel.com
Jani Nikula (15):
drm/i915/display: reindent subplatform initialization
drm/i915/display: use a macro to initialize subplatforms
drm/i915/display: use a macro to define platform enumerations
drm/i915/display: join t
Make it easier to change the underlying structures by using a macro
similar to PLATFORM() for initialization.
The subplatform names in debug logs change slightly as they now reflect
the enum rather than manually entered names. For example, RAPTORLAKE_S
rather than RPL-S.
Reviewed-by: Rodrigo Vivi
We'll be needing a macro based list of platforms for more things in the
future. Start by defining the platform enumerations with it.
v3: Rebase for PTL
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.h | 119 +-
1 file change
We'll want to use the subplatforms similar to platforms. Join the
subplatforms next to their corresponding platforms. Update the comment
while at it.
v2: Put the subplatforms next to the platforms
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_devic
Make the subplatform initialization less cramped, and follow the coding
style more closely. Initialize .pciidlist using designated initializers.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 116 +-
1 file changed, 88 in
Add a structure with a bitfield member for each platform and
subplatform, and initialize them in platform and subplatform descs.
The structure also contains a bitmap in a union for easier manipulation
of the bits. This, in turn, requires a bit of trickery with
INTEL_DISPLAY_PLATFORMS() to count th
Facilitate using display->platform.haswell and
display->platform.haswell_ult etc. for identifying platforms and
subplatforms.
Merge the platform and subplatform bitmaps together, and check that
there's no overlap.
v4:
- Lower case, s/is/platform/
v3:
- Fix sanity check on display->is after mergi
Add support for defining aliases for platform groups, such as g4x that
covers both g45 and gm45.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_device.c | 9 +
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
2 files changed, 10 insertions(+)
diff --
Add support for defining aliases for subplatform groups, such as HSW/BDW
ULT that covers both ULT and ULX.
ULT is a special case, because we slightly abuse the ULT subplatform
both as a subplatform and group, but with the way this is defined, it
should be fairly clear.
This follows i915 core and
This will be helpful for follow-up, where the names here become struct
member names.
This does impact debug logs as well, making everything lower case.
v2: Rebase to adapt to PTL
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 122 +
The display platform enums are not really needed for anything. Remove.
Without the enum, PLATFORM_UNINITIALIZED is also no longer needed for
keeping the first enum 0.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_device.c | 12 +++-
drivers/gpu/drm/i915/displ
Switch to using the new display->platform. members for
platform identification in display code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 40 +--
1 file changed, 15 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/inte
Switch to using the new display->platform. members for
platform identification in display code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pps.c | 47 ++--
1 file changed, 20 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/inte
Switch to using the new display->platform. members for
platform identification in display code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vga.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c
b/drivers/gpu/d
Switch to using the new display->platform. members for
platform identification in display code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vblank.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
Switch to using the new display->platform. members for
platform identification in display code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_tv.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c
b/drivers
== Series Details ==
Series: drm/i915/gt: Retry RING_HEAD reset until it get sticks (rev2)
URL : https://patchwork.freedesktop.org/series/14/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15573 -> Patchwork_14v2
Sum
== Series Details ==
Series: drm/i915/dmc_wl: Fixes and enablement for Xe3_LPD
URL : https://patchwork.freedesktop.org/series/140282/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15574 -> Patchwork_140282v1
Summary
---
== Series Details ==
Series: FOR-CI: drm/i915/guc: Move destroy context at end of reset prepare
URL : https://patchwork.freedesktop.org/series/140284/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15574 -> Patchwork_140284v1
On 10/21/2024 6:16 PM, Jani Nikula wrote:
On Mon, 21 Oct 2024, Ankit Nautiyal wrote:
At the moment dsc_split represents that dsc splitter is used or not.
With 3 DSC engines, the splitter can split into two streams or three
streams. Make the member dsc_split as int and set that to 2 when dsc
s
On 10/21/2024 6:19 PM, Jani Nikula wrote:
On Mon, 21 Oct 2024, Ankit Nautiyal wrote:
Add macro for Pixel replication support with DSC.
Add blank line here.
Bspec: 49259, 68912.
Remove blank line here.
Noted will have Bspec as first line of the trailer.
Regards,
Ankit
Signed-off-b
On 22-10-2024 11:26, Suraj Kandpal wrote:
Add check to remove HDCP2 compatibility from BMG as it does not
have GSC which ends up causing warning when we try to get reference
of GSC FW.
Add fixes.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 3 ++-
d
On 10/22/2024 11:26 AM, Suraj Kandpal wrote:
Add check to remove HDCP2 compatibility from BMG as it does not
have GSC which ends up causing warning when we try to get reference
of GSC FW.
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_h
Add check to remove HDCP2 compatibility from BMG as it does not
have GSC which ends up causing warning when we try to get reference
of GSC FW.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 3 ++-
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 3 ++-
2 files ch
== Series Details ==
Series: drm/i915/gt: Retry RING_HEAD reset until it get sticks (rev3)
URL : https://patchwork.freedesktop.org/series/14/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15574 -> Patchwork_14v3
Sum
> -Original Message-
> From: Roper, Matthew D
> Sent: 19 October 2024 05:14
> To: Atwood, Matthew S
> Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org; Golani,
> Mitulkumar Ajitkumar ; Nautiyal,
> Ankit K
> Subject: Re: [PATCH 01/12] drm/i915/display/ptl: Fill VRR c
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Monday, October 21, 2024 6:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj
>
> Subject: [PATCH 01/16] drm/i915/dp: Update Comment for Valid DSC Slices
> per Line
>
> For some platfo
On 10/22/2024 9:23 AM, Nautiyal, Ankit K wrote:
On 10/21/2024 6:16 PM, Jani Nikula wrote:
On Mon, 21 Oct 2024, Ankit Nautiyal wrote:
At the moment dsc_split represents that dsc splitter is used or not.
With 3 DSC engines, the splitter can split into two streams or three
streams. Make the me
1 - 100 of 103 matches
Mail list logo
