[PATCH 04/16] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2

[Ankit Nautiyal]

Introduce the register bits to enable the 3rd DSC engine VDSC2.
Add support to read/write these bits.

v2: Only introduce bits that are used and update the subject and commit
message. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 20 +++++++++++++++----
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  2 ++
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c 
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 198446738662..70b75de921de 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -380,6 +380,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum 
transcoder cpu_transcoder)
 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state 
*crtc_state)
 {
        switch (crtc_state->dsc.dsc_split) {
+       case 3:
+               return 3;
        case 2:
                return 2;
        case 0:
@@ -782,6 +784,12 @@ void intel_dsc_enable(const struct intel_crtc_state 
*crtc_state)
                dss_ctl2_val |= VDSC1_ENABLE;
                dss_ctl1_val |= JOINER_ENABLE;
        }
+
+       if (vdsc_instances_per_pipe > 2) {
+               dss_ctl2_val |= VDSC2_ENABLE;
+               dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES;
+       }
+
        if (crtc_state->joiner_pipes) {
                if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
                        dss_ctl1_val |= ULTRA_JOINER_ENABLE;
@@ -983,11 +991,15 @@ void intel_dsc_get_config(struct intel_crtc_state 
*crtc_state)
        if (!crtc_state->dsc.compression_enable)
                goto out;
 
-       if ((dss_ctl1 & JOINER_ENABLE) &&
-           (dss_ctl2 & VDSC1_ENABLE))
-               crtc_state->dsc.dsc_split = 2;
-       else
+       if (dss_ctl1 & JOINER_ENABLE) {
+               if (dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES))
+                       crtc_state->dsc.dsc_split = 3;
+
+               else if (dss_ctl2 & VDSC1_ENABLE)
+                       crtc_state->dsc.dsc_split = 2;
+       } else {
                crtc_state->dsc.dsc_split = 0;
+       }
 
        intel_dsc_get_pps_config(crtc_state);
 out:
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h 
b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index d7a72b95ee7e..474a7f9f3881 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -22,6 +22,8 @@
 
 #define DSS_CTL2                               _MMIO(0x67404)
 #define  VDSC0_ENABLE                          REG_BIT(31)
+#define  VDSC2_ENABLE                          REG_BIT(30)
+#define  SMALL_JOINER_CONFIG_3_ENGINES         REG_BIT(23)
 #define  VDSC1_ENABLE                          REG_BIT(15)
 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK                (0xfff << 0)
 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)     ((pixels) << 0)
-- 
2.45.2