On 2024-04-05 16:18:18 [+0200], To intel-gfx@lists.freedesktop.org wrote:
Hi,
> The following patches are from the PREEMPT_RT queue. It is mostly about
> disabling interrupts/preemption which leads to problems. Unfortunately
…
Could I please get some feedback? I didn't receive anything but
autom
Jouni, Animesh, there are some PSR commits with Fixes: pointing at
commits in v6.9 or v6.10-rc1.
This does not apply cleanly to -rc1:
d07a578703db ("drm/i915/display: Do not print "psr: enabled" for on Panel
Replay")
This applies but does not build:
45b5853114ad ("drm/i915/psr: Get Early Trans
On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
> We'll want to use fsb frequency for deriving GT clock and rawclk
> frequencies in the future. Increase the accuracy by converting to
> kHz. Do the same for mem freq to be aligned.
mem_freq is used in:
- gen5_rps_init() -> needs to be a
On Wed, 2024-06-05 at 13:06 +0300, Jani Nikula wrote:
>
> Jouni, Animesh, there are some PSR commits with Fixes: pointing at
> commits in v6.9 or v6.10-rc1.
>
> This does not apply cleanly to -rc1:
> d07a578703db ("drm/i915/display: Do not print "psr: enabled" for on
> Panel Replay")
>
> This ap
On Tue, Jun 04, 2024 at 02:46:18PM +0300, Jani Nikula wrote:
> On Thu, 30 May 2024, Jani Nikula wrote:
> > On Wed, 29 May 2024, Matt Roper wrote:
> >> On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
> >>> Initialize fsb frequency for more platforms to be able to use it for GT
> >>> c
On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
> Initialize fsb frequency for more platforms to be able to use it for GT
> clock and rawclk frequency initialization.
>
> Note: There's a discrepancy between existing pnv_fsb_freq() and
> i9xx_hrawclk() regarding CLKCFG interpretation.
This patch set is implementing eDP1.5 Panel Replay for Intel hw. Patch
to disable Region Early Transport by default is reverted as it is
needed by eDP Panel Replay.
Patches 1 - 14 are fixes and clean-ups for DP2.0 Panel Replay found while
testing with eDP1.5 panel. Patches 15 - 26 are implementin
Currently AUX Less Wake lines are not written into ALPM_CTL. Fix this.
Fixes: 1ccbf135862b ("drm/i915/psr: Enable ALPM on source side for eDP Panel
replay")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Currently intel_dp_vsc_sdp_unpack is not taking into account Panel Replay
vsc sdp. Fix this by adding vsc sdp revision 0x6 and length 0x10 into
intel_dp_vsc_sdp_unpack
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 -
1 file changed, 4 insertions(+), 1 deletion
We want to have own variables for fast wake lines and aux less wake
time. It might be needed to choose if we can enable Panel Replay Selective
Update or PSR2.
Also currently aux less wake time is overwritten by calculated fast wake
time.
v2:use less wake time in intel_alpm_lobf_compute_config
Fi
Panel Replay is not enabled if there are no active planes. Do not compare
it on pipe comparison. Otherwise we get pipe mismatch.
Fixes: ac9ef327327b ("drm/i915/psr: Panel replay has to be enabled before link
training")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display
Add missing Panel Replay Enable SU Region ET bit defined in DP2.1
specification.
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index f246fa03a3cb..173548c6473a 100644
Current intel_psr_enable_sink is a mess due to partly reusing PSR bit
definitions for Panel Replay. Even thought PSR and Panel Replay enable
registers do have common bits they still have also different bits and same
bits with different meaning. For sake of clarity split enabling sink to PSR
and Pan
We want to use intel_alpm_aux_wake_supported and
intel_alpm_aux_less_wake_supported in intel_psr.c. Convert them as
non-static.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4 ++--
drivers/gpu/drm/i915/display/intel_alpm.h | 2 ++
2 files changed, 4 insertions(+)
We have now intel_alpm_aux_wake_supported. Use that instead of local
variable.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/dr
Early Transport is possible and in our HW mandatory on eDP Panel
Replay. Add parameter to intel_psr2_config_et_valid to differentiate
validity check for Panel Replay.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 15 ---
1 file changed, 8 insertions(+),
Currently Panel Replay status printout is printing frame lock status. It
should print Panel Replay status instead. Panel Replay status register
field follows PSR status register field. Use existing PSR code for that.
Fixes: ef75c25e8fed ("drm/i915/panelreplay: Debugfs support for panel replay")
Si
SU SDP scanline indication should be taken into account when checking
vblank length. In Bspec we have:
PSR2_CTL[ SU SDP scanline indication ] = 0: (TRANS_VBLANK Vertical Blank End-
TRANS_VBLANK Vertical Blank Start) > PSR2_CTL Block Count Number value in lines
PSR2_CTL[ SU SDP scanline indication
We are about to add more complexity to vblank length check. It makes sense
to move it to separate function for sake of clarity.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drive
As Lunarlake doesn't have block count configuration vblank should be
checked against IO buffer wake time.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display
When checking vblank length used wake time is aux less wake time for eDP
Panel Replay (vblank length is not checked for DP2.0 Panel Replay).
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/driv
Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check
panel support for this and prevent eDP panel replay if it doesn't exits.
Bspec: 68920
v2: use intel_alpm_aux_less_wake_supported
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
1 fil
Display version >= 20 support eDP 1.5. Inform Panel Replay source support
on eDP for display version >= 20.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
eDP1.5 allows Panel Replay on eDP as well. Take this into account when
enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register
accordingly.
v3:
- set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2
- PANEL_REPLAY_CONFIG2 is available in DP2.1 as well
v2: do not config
Our HW doesn't support panel replay without Early Transport on eDP.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/
We are about to add more checks for Panel Replay. Due to that it makes
sense to add now Panel Replay compute config helper.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i
There are couple of bits in PSR2_CTL which needs to be written in case of
eDP Panel Replay
Bspec: 68920
v2: use boolean instead of assuming eDP Panel Replay mean Early Transport
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 13 +
1 file changed, 13 in
This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d.
We want to notice possible issues faced with PSR2 Region Early Transport as
early as possible -> let's revert patch disabling Region Early Transport by
default. Also eDP 1.5 Panel Replay requires Early Transport.
Signed-off-by: Jouni H
Take into account in Panel Replay compute config that HW will not allow PR
on eDP when HDCP enabled.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/in
Move Early Transport validity check to be performed for Panel Replay as
well and use Early Transport for eDP Panel Replay always.
v2:set crtc_state->enable_psr2_su_region_et directly (not in if block)
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
1 file
eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM
related things for Panel Replay as well.
Bspec: 68920
v3: move vblank check as well
v2: do not move Vblank >= PSR2_CTL Block Count Number maximum line count
check
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/dis
Take into account that 128b/132b Panel Replay is not supported on eDP.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/driver
Currently there is no way to disable Panel Replay without disabling
PSR. Add new debug bit to be used with i915_edp_psr_debug debugfs
interface.
v2: ensure that fastset is performed when the bit changes
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
On Tue, May 28, 2024 at 05:24:58PM +0300, Jani Nikula wrote:
> Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
> figure out rawclk_freq where applicable.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++
> 1 file ch
From: Ville Syrjälä
Clean up the bdw+ pipe interrupt bits, and enable some new fault
interrupts on tgl+ and mtl+.
Ville Syrjälä (7):
drm/i915: Use REG_BIT() for bdw+ pipe interrupts
drm/i915: Document bdw+ pipe interrupt bits
drm/i915: Sort bdw+ pipe interrupt bits
drm/i915: Extend GEN9_
From: Ville Syrjälä
Replace the hand rolled (1<
---
drivers/gpu/drm/i915/i915_reg.h | 54 -
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0569a23b83b2..6b77de060e33 100644
--
From: Ville Syrjälä
Sprinkle some notes indicating which platforms have which
pipe interrupt bits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 42 -
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_
From: Ville Syrjälä
It's really hard to figure out which bdw+ pipe interrupt bits
we've defined and which we have not. Sort the defines to make
that a bit easier (still not super easy since the bits have
been shuffled a bit over the years).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915
From: Ville Syrjälä
GEN9_PIPE_PLANE_FLIP_DONE() only works for planes 1-4. Extend
it handle planes 5-7 as well. Somewhat annoyingly the bits are
spread around into two distinct clumps.
Currently this doesn't achieve anything, but if we ever extend
async flip support to more than just the first p
From: Ville Syrjälä
GEN8_DE_PIPE_IRQ_FAULT_ERRORS & co. don't really achieve anything.
Get rid of them and just declare all the bits directly in
gen8_de_pipe_fault_mask().
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_display_irq.c | 26 ---
drivers/gpu/drm/i
From: Ville Syrjälä
PipeDMC has its own fault interrupt. Enable that so that
we can know if things are failing.
While at it, define the other pipeDMC interrupt as well, even
though we're not currently using it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_irq.c
From: Ville Syrjälä
MTL has some new IOMMU thing that has a few new fault interrupts.
Enable those so we can know if things are going poorly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h | 2
From: Ville Syrjälä
No idea why the DDI clock gating print is done with drm_notice().
Just use drm_dbg_kms() since no one is going to be interested in
this under normal circumstances.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
1 file changed, 3 insert
On Wed, 05 Jun 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No idea why the DDI clock gating print is done with drm_notice().
> Just use drm_dbg_kms() since no one is going to be interested in
> this under normal circumstances.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enab
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame dro
From: Ville Syrjälä
It's probably a good idea to start protecting all macro arguments
to avoid any cargo-cult mistakes when people go looking for examples
of how to define these things.
Signed-off-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-8-ville
From: Ville Syrjälä
---
integration-manifest | 28
1 file changed, 28 insertions(+)
create mode 100644 integration-manifest
diff --git a/integration-manifest b/integration-manifest
new file mode 100644
index ..d840964a2208
--- /dev/null
+++ b/integratio
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++
drivers/gpu/drm/i915/i915_reg.h | 101 ---
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based o
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enab
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1 file
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/inte
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enab
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enab
On Wed, 05 Jun 2024, Ville Syrjälä wrote:
> On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
>> We'll want to use fsb frequency for deriving GT clock and rawclk
>> frequencies in the future. Increase the accuracy by converting to
>> kHz. Do the same for mem freq to be aligned.
>
> mem_
Hi,
I made a mistake while creating patch and this was sent by mistake. Please
ignore this patch. I will rebase my patch series and send the correct version.
Sorry for inconvenience.
Regards,
Mitul
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Wednesday, J
Hi,
Similar to Patch #1 this was sent by mistake. Please ignore this patch. I will
rebase my patch series and send the correct version.
Sorry for inconvenience.
Regards,
Mitul
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Wednesday, June 5, 2024 5:58 PM
>
On Sun, Jun 02, 2024 at 06:57:12PM +0300, Andy Shevchenko wrote:
> Make two APIs look similar. Hence convert match_string() to be
> a 2-argument macro. In order to avoid unneeded churn, convert
> all users as well. There is no functional change intended.
>
> Signed-off-by: Andy Shevchenko
> ---
>
Il 02/06/24 17:57, Andy Shevchenko ha scritto:
Make two APIs look similar. Hence convert match_string() to be
a 2-argument macro. In order to avoid unneeded churn, convert
all users as well. There is no functional change intended.
Signed-off-by: Andy Shevchenko
For MediaTek
Reviewed-by: Ange
On Tue, 04 Jun 2024 10:45:37 +0300
Jani Nikula wrote:
> On Sun, 02 Jun 2024, Andy Shevchenko
> wrote:
> > Make two APIs look similar. Hence convert match_string() to be
> > a 2-argument macro. In order to avoid unneeded churn, convert
> > all users as well. There is no functional change intende
On Tue, 4 Jun 2024 at 11:25, Rodrigo Vivi wrote:
>
> (I believe that the new _match_string(str1, size, str2) deserves a better
> name,
> but since I'm bad with naming stuff, I don't have any good suggestion)
I hated the enormous cc list, so I didn't reply to all. But clearly
everybody else is ju
On Sun, Jun 02, 2024 at 06:57:12PM +0300, Andy Shevchenko wrote:
> Make two APIs look similar. Hence convert match_string() to be
> a 2-argument macro. In order to avoid unneeded churn, convert
> all users as well. There is no functional change intended.
> diff --git a/drivers/cpufreq/amd-pstate.
== Series Details ==
Series: Panel Replay eDP support (rev7)
URL : https://patchwork.freedesktop.org/series/133684/
State : warning
== Summary ==
Error: dim checkpatch failed
58d77df5a406 drm/i915/alpm: Do not use fast_wake_lines for aux less wake time
c88c51ffc880 drm/i915/alpm: Write also AU
== Series Details ==
Series: Panel Replay eDP support (rev7)
URL : https://patchwork.freedesktop.org/series/133684/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Ville Syrjälä
The VBT spec does a very poor job of defining how the chromaticity
coordinates in block 46 are laid out. After double checking the
Windows implementation it turns out these more or less match the
EDID definition, where the 10bit values are split into 2bit + 8bit
chunks. Adjust
From: Ville Syrjälä
Since BDB version 211 block 46 has included more luminance and
gamma related information. Define it fully. The data is semi-based
on DisplayID v2.0 apparently.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12
1 file changed,
== Series Details ==
Series: Panel Replay eDP support (rev7)
URL : https://patchwork.freedesktop.org/series/133684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14881 -> Patchwork_133684v7
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: bdw+ pipe interrupt stuff
URL : https://patchwork.freedesktop.org/series/134497/
State : warning
== Summary ==
Error: dim checkpatch failed
1e0bd32b8a29 drm/i915: Use REG_BIT() for bdw+ pipe interrupts
8711ec9d6af6 drm/i915: Document bdw+ pipe interrupt b
== Series Details ==
Series: drm/i915: bdw+ pipe interrupt stuff
URL : https://patchwork.freedesktop.org/series/134497/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14881 -> Patchwork_134497v1
Summary
---
**SUCCESS*
== Series Details ==
Series: Implement CMRR Support (rev12)
URL : https://patchwork.freedesktop.org/series/126443/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/126443/revisions/12/mbox/ not
applied
Applying: drm/i915: Protect CRC reg macro argum
== Series Details ==
Series: drm/i915: Reduce DDI clock gating printk level from NOTICE to DEBUG
URL : https://patchwork.freedesktop.org/series/134499/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14881 -> Patchwork_134499v1
===
== Series Details ==
Series: series starting with [1/2] drm/i915/bios: Define block 46 chromaticity
coordinates properly
URL : https://patchwork.freedesktop.org/series/134505/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14881 -> Patchwork_134505v1
==
On Mon, Jun 03, 2024 at 02:25:49PM +0300, Stanislav Lisovskiy wrote:
> Lets unify both bigjoiner and ultrajoiner under simple "joiner" name,
> because in future we might have multiple configurations, involving
> multiple bigjoiners, ultrajoiner, however it is possible to use
> same api for handling
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 234cb065ad82915ff8d06ce01e01c3e640b674d2 Add linux-next specific
files for 20240605
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202406051521.mroqvr5l-...@intel.com
https
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame dro
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++
drivers/gpu/drm/i915/i915_reg.h | 101 ---
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based o
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/inte
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1 file
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
with VRR timing generator or not. Make CMRR as s
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enab
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
--v3:
- vrr.enable and cmrr.enable check together is not required as both
will be true at the same point in time. (Ankit)
-
== Series Details ==
Series: Panel Replay eDP support (rev7)
URL : https://patchwork.freedesktop.org/series/133684/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14881_full -> Patchwork_133684v7_full
Summary
---
**FA
== Series Details ==
Series: Implement CMRR Support (rev13)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Implement CMRR Support (rev13)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
71b880e0125f gpu/drm/i915: Update indentation for VRR registers and bits
00df34d55970 drm/i915: Separate VRR related reg
== Series Details ==
Series: Implement CMRR Support (rev13)
URL : https://patchwork.freedesktop.org/series/126443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14881 -> Patchwork_126443v13
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: bdw+ pipe interrupt stuff
URL : https://patchwork.freedesktop.org/series/134497/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14881_full -> Patchwork_134497v1_full
Summary
---
The ce->guc_state.lock was made to protect guc_prio, which
indicates the GuC priority level.
But at the begnning of the function we perform some sanity check
of guc_prio outside its protected section. Move them within the
locked region.
Use this occasion to expand the if statement to make it clea
== Series Details ==
Series: drm/i915/gt/uc: Evaluate GuC priority within locks
URL : https://patchwork.freedesktop.org/series/134525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14881 -> Patchwork_134525v1
Summary
--
Hi Krzysztof,
On Mon, Jun 03, 2024 at 06:20:22PM +0200, Niemiec, Krzysztof wrote:
> The test is trying to push the heartbeat frequency to the limit, which
> might sometimes fail. Such a failure does not provide valuable
> information, because it does not indicate that there is something
> necessar
Hi Janusz,
On Tue, Jun 04, 2024 at 05:27:24PM +0200, Janusz Krzysztofik wrote:
> On Tuesday, 4 June 2024 02:48:43 GMT+2 Andi Shyti wrote:
> > On Mon, Jun 03, 2024 at 09:54:45PM +0200, Janusz Krzysztofik wrote:
> > > CI has been sporadically reporting the following issue triggered by
> > > igt@i915
On Thu, Jun 06, 2024 at 02:17:02AM +0200, Andi Shyti wrote:
> The ce->guc_state.lock was made to protect guc_prio, which
> indicates the GuC priority level.
>
> But at the begnning of the function we perform some sanity check
> of guc_prio outside its protected section. Move them within the
> lock
== Series Details ==
Series: drm/i915/gt/uc: Evaluate GuC priority within locks (rev2)
URL : https://patchwork.freedesktop.org/series/134525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14883 -> Patchwork_134525v2
Summary
== Series Details ==
Series: drm/i915/gt: Fix potential UAF by revoke of fence registers (rev2)
URL : https://patchwork.freedesktop.org/series/134411/
State : warning
== Summary ==
Error: dim checkpatch failed
68a3074a63dc drm/i915/gt: Fix potential UAF by revoke of fence registers
-:9: WARNIN
== Series Details ==
Series: drm/i915/gt: Fix potential UAF by revoke of fence registers (rev2)
URL : https://patchwork.freedesktop.org/series/134411/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14883 -> Patchwork_134411v2
100 matches
Mail list logo
