== Series Details ==
Series: drm/i915/rpl: Update pci ids for RPL P/U (rev2)
URL : https://patchwork.freedesktop.org/series/122712/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13558 -> Patchwork_122712v2
Summary
---
== Series Details ==
Series: drm/i915/rpl: Update pci ids for RPL P/U (rev3)
URL : https://patchwork.freedesktop.org/series/122712/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: drm/i915/rpl: Update pci ids for RPL P/U (rev3)
URL : https://patchwork.freedesktop.org/series/122712/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: drm/i915/rpl: Update pci ids for RPL P/U (rev3)
URL : https://patchwork.freedesktop.org/series/122712/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13558 -> Patchwork_122712v3
Summary
---
On Fri, 2023-08-18 at 20:50 -0700, Lucas De Marchi wrote:
> On Wed, Aug 16, 2023 at 09:08:44AM +, Coelho, Luciano wrote:
> > On Wed, 2023-08-16 at 08:13 +, Kandpal, Suraj wrote:
> > > > This function doesn't really return the pin assignment mask, but
> > > > the max lane
> > > > count deriv
On Mon, 2023-08-21 at 17:27 +, Kandpal, Suraj wrote:
> 0/4] drm/i915/tc: some clean-ups in max
> > lane count handling code
> >
> > On Fri, Jul 21, 2023 at 02:11:17PM +0300, Luca Coelho wrote:
> > > Hi,
> > >
> > > Here are four patches with some clean-ups in the code that handles the
> > > m
This is v2 of [1], with the following changes:
- Add helpers to convert between fractional and integer bpp values
instead of open coding these. (Jani)
- Increase back pipe B's link bpp after it was reduced due to a BW
limit on FDI wrt. pipe C and then pipe C gets disabled. (Patch 8)
- Fix vari
Factor out helpers that DP / DP_MST encoders can use to compute the link
rate/lane count and bpp limits. A follow-up patch will call these to
recalculate the limits if DSC compression is required.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 61 +
Computing the non-DSC mode link config is redundant once it's determined
that DSC will be needed, so skip computing it. In a follow-up patch this
simplifies setting the link limits which are dependent on the DSC vs.
non-DSC mode.
While at it sanitize the debug print about the MST DSC fallback path
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
range, while in DSC mode it can be set in 1/16 bpp steps to any value
up to the maximum pipe bpp. Update the limits accordingly in both modes
to prepare for a follow-up patch which may need to reduce the max link
bpp value and
Limit the output link bpp in DSC mode to the link_config_limits
link.min_bpp_x16 .. max_bpp_x16 range the same way it's done in non-DSC
mode. Atm this doesn't make a difference, the link bpp range being
0 .. max pipe bpp, but a follow-up patch will need a way to reduce max
link bpp below its curre
Factor out intel_atomic_check_config() to check and compute all the CRTC
states. This will be used by a follow up patch to recompute/check the
state until required by BW limitations between CRTCs.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 78
At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
link bpp in this case, until pipe B uses only up to 2 FDI lanes.
For this instead of the encoder compute config retry loop - which
reduced link bpp only for t
A follow-up patch will need to limit the output link bpp both in the
non-DSC and DSC configuration, so track the pipe and link bpp limits
separately in the link_config_limits struct.
Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
in DSC mode and for now keep this limit ma
On 8b/10b MST links the PBN value for DSC streams must be calculated
accounting for the FEC overhead. The same applies to 8b/10b non-DSC
streams if there is another DSC stream on the same link. Fix up the PBN
calculation accordingly.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/inte
Add intel_modeset_pipes_in_mask() to modeset a provided set of pipes,
used in a follow-up patch.
While at it add DocBook descriptions for the exported functions.
v2:
- Add a flag controlling if active planes are force updated as well.
- Add DockBook descriptions.
Signed-off-by: Imre Deak
---
d
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c
Atm the DSC PPS SDP is programmed only if the first stream is compressed
and then it's programmed only for the first stream. This left all other
compressed streams blank. Program the SDP for all streams.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c| 12 +++-
Atm the DSC PPS SDP will stay enabled after enabling and disabling DSC.
This leaves an output blank after switching off DSC on it. Make sure the
SDP is disabled for an uncompressed output.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 6 ++
1 file changed, 6 insert
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port an
Add the missing DSC compression disabling step for MST streams,
similarly to how this is done for SST outputs.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu
Atm the driver supports DSC on MST links only by enabling it globally in
the first branch device UFP's physical DPCD (vs. enabling it per-stream
in the virtual DPCD right upstream the DPRX). This means the branch
device will decompress any compressed stream (which it recognizes via
MSA / SDP compre
If an MST stream is modeset, its state must be checked along all the
other streams on the same MST link, for instance to resolve a BW
overallocation of a non-sink MST port or to make sure that the FEC is
enabled/disabled the same way for all these streams.
To prepare for that this patch adds all t
Atm DSC decompression is enabled in the sink only if the first stream is
compressed. This left compressed streams blank if the first stream was
uncompressed.
Enable decompression whenever FEC is enabled, which will be true for all
streams if any stream is compressed. Enabling FEC correctly in all
After the previous patch the BW limits on the whole MST topology will be
checked after computing the state for all the streams in the topology.
Accordingly remove the check during the stream's encoder compute config
step, to prevent failing an atomic commit due to a BW limit, if this can
be resolve
For fractional bpp values passed to the function in a .4 fixed point
format, the fractional part is currently ignored due to scaling bpp too
early. Fix this by scaling the overhead factor instead and to avoid an
overflow multiplying bpp with the overhead factor instead of the clock
rate.
While at
At the moment modesetting a stream CRTC will fail if the stream's BW
along with the current BW of all the other streams on the same MST link
is above the total BW of the MST link. Make the BW sharing more dynamic
by trying to reduce the link bpp of one or more streams on the MST link
in this case.
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signe
Add a way for drivers to calculate the MST PBN values with FEC overhead.
This is required by 8b/10b links both for DSC and non-DSC (the latter
needed if there are both DSC and non-DSC streams on the same MST link).
Also add kunit test cases for PBN values calculated with FEC overhead.
Cc: Lyude P
Hi Manasi,
> -Original Message-
> From: Intel-gfx On Behalf Of
> Manasi Navare
> Sent: 24 August 2023 05:22
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH] drm/i915/display/vrr: Compute VRR min/max
> based on highest clock mode for DRRS panel
>
>
On Wed, 23 Aug 2023, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan
>>
>> Add Lunar Lake platform definitions for i915 display. The support for
>> LNL will be added to the xe driver, with i915 only driving the display
>> s
On Wed, 23 Aug 2023, Lucas De Marchi wrote:
> From: Clint Taylor
>
> Display Ver 20 moved the D2D Enable bit to DDI_BUF_CTL(DDI_CTL_DE)
> register. We used multiple variables for HDMI and DisplayPort copies of
> this register. Consolidate the various locations to use
> intel_digital_port saved_po
On Wed, 23 Aug 2023, Lucas De Marchi wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index cb5d1be2ba19..4b5b9a97142d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/displ
Hi,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2023-08-24:
A samsung-dsim initialization fix, a devfreq fix for panfrost, a DP DSC
define fix, a recursive lock fix for dma-buf, a shader validation fix
and a reference counting fix for vmwgfx
The following changes since commit 50b6f2
Add newly added PCI-IDs for RPL
BSpec: 55376
Signed-off-by: Chaitanya Kumar Borah
---
include/drm/i915_pciids.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 1661f9e552d2..1256770d3827 100644
--- a/include
Just noticed that Dnyaneshwar has already sent patches for this change.
https://patchwork.freedesktop.org/patch/554112/?series=122712&rev=3
We can perhaps ignore this.
Regards
Chaitanya
> -Original Message-
> From: Borah, Chaitanya Kumar
> Sent: Thursday, August 24, 2023 2:09 PM
> To:
On Thu, 24 Aug 2023, Chaitanya Kumar Borah
wrote:
> Add newly added PCI-IDs for RPL
Please review [1] instead.
BR,
Jani.
[1]
https://patchwork.freedesktop.org/patch/msgid/20230824062840.2372872-1-dnyaneshwar.bhad...@intel.com
>
> BSpec: 55376
>
> Signed-off-by: Chaitanya Kumar Borah
> ---
On Wed, Aug 23, 2023 at 05:24:25PM +0530, Ankit Nautiyal wrote:
> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
> limits while computing the input bpp for DSC.
>
> Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
That is kind of funny, I can see this pa
On Thu, Aug 24, 2023 at 11:05:13AM +0300, Imre Deak wrote:
> Atm DSC decompression is enabled in the sink only if the first stream is
> compressed. This left compressed streams blank if the first stream was
> uncompressed.
>
> Enable decompression whenever FEC is enabled, which will be true for al
On Wed, 23 Aug 2023, Ankit Nautiyal wrote:
> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
> limits while computing the input bpp for DSC.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 d
On Thu, Aug 24, 2023 at 11:05:14AM +0300, Imre Deak wrote:
> Add the missing DSC compression disabling step for MST streams,
> similarly to how this is done for SST outputs.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
> 1 file changed, 2 insertions(+)
On Thu, 24 Aug 2023, Ankit Nautiyal wrote:
> As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
> Apparently some panels that do support DSC, are not setting the bit for
> 8bpc.
>
> So always assume 8bpc support by DSC decoder, when DSC is claimed to be
> supported.
>
> v2: Use h
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev2)
URL : https://patchwork.freedesktop.org/series/122589/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file o
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev2)
URL : https://patchwork.freedesktop.org/series/122589/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, 24 Aug 2023, Gil Dekel wrote:
> Next version of https://patchwork.freedesktop.org/series/122643/
>
> Reorganize into:
> 1) Add for final failure state for SST and MST link training fallback.
> 2) Add a DRM helper for setting downstream MST ports' link-status state.
> 3) Make handling SST a
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev2)
URL : https://patchwork.freedesktop.org/series/122589/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13559 -> Patchwork_122589v2
Su
Reviewed-by: Arun R Murthy
Thanks and Regards,
Arun R Murthy
---
From: Kandpal, Suraj
Sent: Wednesday, August 23, 2023 11:28 AM
To: intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K ; uma.sha...@intel.com
; Murthy, Arun R ; Kandpal,
Suraj
On Mon, 2023-08-21 at 06:33 +, Hogander, Jouni wrote:
> On Mon, 2023-08-14 at 19:34 +0300, Juha-Pekka Heikkila wrote:
> > Add missing spin_lock/unlock
> >
> > Signed-off-by: Juha-Pekka Heikkila
>
> Reviewed-by: Jouni Högander
Thank you for the patch. This is now merged.
BR,
Jouni Högande
On Thu, Aug 24, 2023 at 11:34:59AM +0300, Jani Nikula wrote:
On Wed, 23 Aug 2023, Lucas De Marchi wrote:
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index cb5d1be2ba19..4b5b9a97142d 100644
--- a/drivers/gpu/drm/i915/display
On Thu, Aug 24, 2023 at 12:44:16PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Aug 24, 2023 at 11:05:14AM +0300, Imre Deak wrote:
> > Add the missing DSC compression disabling step for MST streams,
> > similarly to how this is done for SST outputs.
> >
> > Signed-off-by: Imre Deak
> > ---
> > d
== Series Details ==
Series: drm/i915/display/vrr: Compute VRR min/max based on highest clock mode
for DRRS panel
URL : https://patchwork.freedesktop.org/series/122812/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13558_full -> Patchwork_122812v1_full
===
== Series Details ==
Series: drm/i915/rpl: Add new RPL PCI-IDs
URL : https://patchwork.freedesktop.org/series/122831/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13559 -> Patchwork_122831v1
Summary
---
**SUCCESS**
On Wed, 2023-08-16 at 08:54 +, Kandpal, Suraj wrote:
> > This makes the code a bit more symmetric and readable, especially
> > when we
> > start adding more display version-specific alternatives.
> >
> > Signed-off-by: Luca Coelho
> > ---
> > drivers/gpu/drm/i915/display/intel_tc.c | 32
On Thu, 2023-08-24 at 05:43 +, Kandpal, Suraj wrote:
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Lucas
> > De Marchi
> > Sent: Wednesday, August 23, 2023 10:37 PM
> > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Coelho, Luciano
> > Subject
> On Wed, 2023-08-16 at 08:54 +, Kandpal, Suraj wrote:
> > > This makes the code a bit more symmetric and readable, especially
> > > when we start adding more display version-specific alternatives.
> > >
> > > Signed-off-by: Luca Coelho
> > > ---
> > > drivers/gpu/drm/i915/display/intel_tc.c
> On Wed, 2023-08-16 at 08:54 +, Kandpal, Suraj wrote:
> > > This makes the code a bit more symmetric and readable, especially
> > > when we start adding more display version-specific alternatives.
> > >
> > > Signed-off-by: Luca Coelho
> > > ---
> > > drivers/gpu/drm/i915/display/intel_tc.c
On Thu, 2023-08-24 at 11:12 +, Kandpal, Suraj wrote:
> > On Wed, 2023-08-16 at 08:54 +, Kandpal, Suraj wrote:
> > > > This makes the code a bit more symmetric and readable,
> > > > especially
> > > > when we start adding more display version-specific
> > > > alternatives.
> > > >
> > > > S
On Thu, 2023-08-24 at 09:39 +0530, Animesh Manna wrote:
> Platforms having Display 13 and above will support panel
> replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY()
> macro to check for panel replay capability.
>
> v1: Initial version.
> v2: DISPLAY_VER() removed as HAS_DP20() is havi
On Thu, 2023-08-24 at 09:39 +0530, Animesh Manna wrote:
> TRANS_DP2_CTL register is programmed to enable panel replay from
> source
> and sink is enabled through panel replay dpcd configuration address.
>
> Bspec: 1407940617
>
> v1: Initial version.
> v2:
> - Use pr_* flags instead psr_* flags. [
On Fri, 18 Aug 2023, Manasi Navare wrote:
> Dual refresh rate (DRR) fastset seamlessly lets refresh rate
> throttle without needing a full modeset.
> However with the recent VRR fastset patches that got merged this
> logic was broken. This is broken because now with VRR fastset
> VRR parameters ar
On Thu, 24 Aug 2023, Animesh Manna wrote:
> DPCD register definition added to check and enable panel replay
> capability of the sink.
>
> Cc: Jouni Högander
> Signed-off-by: Animesh Manna
> ---
> include/drm/display/drm_dp.h | 11 +++
If it touches drm, need to Cc: dri-devel. This is no
On Wed, 2023-08-23 at 13:28 -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:25AM -0700, Lucas De Marchi wrote:
> > From: Luca Coelho
> >
> > Starting from display version 20, we need to read the pin assignment
> > from the IOM TCSS_DDI_STATUS register instead of reading it from the
> > F
Thanks Stan for the review.
Regards,
Ankit
On 8/24/2023 2:59 PM, Lisovskiy, Stanislav wrote:
On Wed, Aug 23, 2023 at 05:24:25PM +0530, Ankit Nautiyal wrote:
Edid specific BPC constraints are stored in limits->max_bpp. Honor these
limits while computing the input bpp for DSC.
Signed-off-by: A
On Wed, 2023-08-23 at 10:07 -0700, Lucas De Marchi wrote:
> From: Luca Coelho
>
> Starting from display version 20, we need to read the pin assignment
> from the IOM TCSS_DDI_STATUS register instead of reading it from the
> FIA.
>
> We use the pin assignment to decide the maximum lane count. So
On Thu, 24 Aug 2023, Animesh Manna wrote:
> Modify existing PSR implementation to enable panel replay feature of DP 2.0
> which is similar to PSR feature of EDP panel. There is different DPCD
> address to check panel capability compare to PSR and vsc sdp header
> is different.
>
> v1: Initial vers
> -Original Message-
> From: Intel-gfx On Behalf Of Tvrtko
> Ursulin
> Sent: Friday, July 7, 2023 6:32 PM
> To: Intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Implement fdinfo memory stats
> printing
>
> From: Tvrtko Ursuli
== Series Details ==
Series: eDP DSC fixes (rev2)
URL : https://patchwork.freedesktop.org/series/122792/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13558_full -> Patchwork_122792v2_full
Summary
---
**FAILURE**
On 8/24/2023 3:14 PM, Jani Nikula wrote:
On Wed, 23 Aug 2023, Ankit Nautiyal wrote:
Edid specific BPC constraints are stored in limits->max_bpp. Honor these
limits while computing the input bpp for DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
1
On Thu, Aug 24, 2023 at 02:27:49PM +0300, Jani Nikula wrote:
> On Fri, 18 Aug 2023, Manasi Navare wrote:
> > Dual refresh rate (DRR) fastset seamlessly lets refresh rate
> > throttle without needing a full modeset.
> > However with the recent VRR fastset patches that got merged this
> > logic was
Thanks Jani for the corrections and suggestions.
I agree to them and will fix them in next version.
Now that I see the commit subject line also should have been "Assume 8
bpc support when DSC is supported", will change that too.
Regards,
Ankit
On 8/24/2023 3:15 PM, Jani Nikula wrote:
On Th
On Wed, Aug 23, 2023 at 11:51:59PM +, Manasi Navare wrote:
> In case of a DRRS panel, there is a preferred panel mode and there is
> a downclock mode with lower pixel clock. But the Vtotal for both remains
> the same. This means even in downclocking mode the VRR Vtotal min/max
> should remain t
== Series Details ==
Series: Panel replay phase1 implementation (rev6)
URL : https://patchwork.freedesktop.org/series/94470/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13558_full -> Patchwork_94470v6_full
Summary
---
Hi Dave and Daniel,
Here goes our next-fixes targeting 6.6-rc1.
Please notice that we have 2 drm level patches there,
one to fix the display HPD polling and one dependency
introducing a helper to reschedule the poll work.
drm-intel-next-fixes-2023-08-24:
- Fix TLB invalidation (Alan)
- Fix Disp
Hi Dave and Daniel,
And this is our fixes targeting 6.5 (rc8?).
I'm again covering for Tvrtko at this round.
Please also notice that here we also have the drm
patches fixing the HPD polling that I had mentioned
in our next-fixes.
One is the fix itself and the other is a dependency
to add the hel
== Series Details ==
Series: drm/i915/vma: constify unbind_fence_ops (rev2)
URL : https://patchwork.freedesktop.org/series/122627/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
Assume 8bpc is supported if Sink claims DSC support.
Also consider bpc constraint coming from EDID while computing
input BPC for DSC.
Rev2: Fix check for dsc support.
Rev3: Minor styling and typos fix.
Ankit Nautiyal (2):
drm/display/dp: Assume 8 bpc support when DSC is supported
drivers/drm/
As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
Apparently some panels that do support DSC, are not setting the bit for
8bpc.
So always assume 8bpc support by DSC decoder, when DSC is claimed to be
supported.
v2: Use helper to get check dsc support. (Ankit)
v3: Fix styling an
Edid specific BPC constraints are stored in limits->max_bpp. Honor these
limits while computing the input bpp for DSC.
v2: Use int instead of u8 for computations. (Jani)
Add closes tag. (Ankit)
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9161
Signed-off-by: Ankit Nautiyal
Reviewed-
== Series Details ==
Series: drm/i915/vma: constify unbind_fence_ops (rev2)
URL : https://patchwork.freedesktop.org/series/122627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13560 -> Patchwork_122627v2
Summary
---
Reduce the use of struct edid and drm_edid_raw().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 11 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 -
drivers/gpu/drm/i915/display/intel_sdvo.c | 7 ++-
3 files changed, 10 insertions(+), 17 del
Avoid accessing the raw edid directly. Pre-parse the source physical
address during normal EDID parsing and use that for CEC.
Jani Nikula (6):
drm/edid: add drm_edid_is_digital()
drm/i915/display: use drm_edid_is_digital()
drm/edid: parse source physical address
drm/cec: add drm_dp_cec_att
Checking edid->input & DRM_EDID_INPUT_DIGITAL is common enough to
deserve a helper that also lets us abstract the raw EDID a bit better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 17 +++--
include/drm/drm_edid.h | 1 +
2 files changed, 16 insertions(+), 2 delet
Connectors have source physical address available in display
info. There's no need to parse the EDID again for this. Add
drm_dp_cec_attach() to do this.
Seems like the set_edid/unset_edid naming is a bit specific now that
there's no need to pass the EDID at all, so aim for attach/detach going
forw
== Series Details ==
Series: HDCP MST aux issue fix (rev4)
URL : https://patchwork.freedesktop.org/series/122267/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/122267/revisions/4/mbox/ not
applied
Applying: drm/i915/hdcp: Use intel_connector argu
In the drm subsystem, the source physical address is, in most cases,
available without having to parse the EDID again. Add notes about
preferring to use the pre-parsed address instead.
Cc: Hans Verkuil
Cc: linux-me...@vger.kernel.org
Signed-off-by: Jani Nikula
---
drivers/media/cec/core/cec-ada
Avoid parsing the EDID again for source physical address. Also gets rids
of a few remaining raw EDID usages.
Cc: Hans Verkuil
Cc: linux-me...@vger.kernel.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 ++---
CEC needs the source physical address. Parsing it is trivial with the
existing EDID CEA DB infrastructure.
Default to CEC_PHYS_ADDR_INVALID (0x) instead of 0 to cater for
easier CEC usage.
Cc: Hans Verkuil
Cc: linux-me...@vger.kernel.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_e
On Thu, 2023-08-17 at 18:53 +0300, Jani Nikula wrote:
> Split out register macros to a separate file, and move more color
> register access to intel_color.c.
Reviewed-by: Jouni Högander
for the whole set.
>
> Jani Nikula (6):
> drm/i915/regs: split out intel_color_regs.h
> drm/i915/color:
== Series Details ==
Series: eDP DSC fixes (rev3)
URL : https://patchwork.freedesktop.org/series/122792/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: eDP DSC fixes (rev3)
URL : https://patchwork.freedesktop.org/series/122792/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unrep
== Series Details ==
Series: eDP DSC fixes (rev3)
URL : https://patchwork.freedesktop.org/series/122792/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13561 -> Patchwork_122792v3
Summary
---
**SUCCESS**
No regress
Hi Jonathan,
few little things...
On Wed, Aug 23, 2023 at 11:51:03AM -0700, Jonathan Cavitt wrote:
> From: Nirmoy Das
>
> Apply WABB blit for Wa_16018031267 / Wa_16018063123.
> Additionally, update the lrc selftest to exercise the new
> WABB changes.
>
> Signed-off-by: Jonathan Cavitt
> Co-de
Hi Jonathan,
> + /* Wa_16018031267, Wa_16018063123 */
> + if (engine->class == COPY_ENGINE_CLASS &&
> + NEEDS_FASTCOLOR_BLT_WABB(i915))
maybe we should have something like
gt_needs_wa_XXX(struct intel_gt *gt)
engine_needs_wa_XXX(struct intel_engine_ce *engine)
Ju
-Original Message-
From: Andi Shyti
Sent: Thursday, August 24, 2023 7:54 AM
To: Cavitt, Jonathan
Cc: intel-gfx@lists.freedesktop.org; Mistat, Tomasz ;
Vivi, Rodrigo ; Germano, Gregory F
; Roper, Matthew D ;
Das, Nirmoy
Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Add WABB blit f
== Series Details ==
Series: drm/i915/rpl: Update pci ids for RPL P/U (rev3)
URL : https://patchwork.freedesktop.org/series/122712/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13558_full -> Patchwork_122712v3_full
Summary
On Thu, Aug 24, 2023 at 11:34:22AM +, Coelho, Luciano wrote:
On Wed, 2023-08-23 at 10:07 -0700, Lucas De Marchi wrote:
From: Luca Coelho
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use th
Hi Suraj,
On Thu, Aug 24, 2023 at 05:43:15AM +, Kandpal, Suraj wrote:
-Original Message-
From: Intel-gfx On Behalf Of Lucas
De Marchi
Sent: Wednesday, August 23, 2023 10:37 PM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Coelho, Luciano
Subject: [Intel
Next version of https://patchwork.freedesktop.org/series/122643/
v3:
Still learning the ropes of upstream workflow. Apologies for mucking up v2.
This is just a re-upload.
v2:
Reorganize into:
1) Add for final failure state for SST and MST link training fallback.
2) Add a DRM helper for
Instead of silently giving up when all link-training fallback values are
exhausted, this patch modifies the fallback's failure branch to reduces
both max_link_lane_count and max_link_rate to zero (0) and continues to
emit uevents until userspace stops attempting to modeset.
By doing so, we ensure
Currently, MST link training has no fallback. This means that if an MST
base connector fails to link-train once, the training completely fails,
which makes this case significantly more common than a complete SST link
training failure.
Similar to the final failure state of SST, this patch zeros out
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