Factor out helpers that DP / DP_MST encoders can use to compute the link
rate/lane count and bpp limits. A follow-up patch will call these to
recalculate the limits if DSC compression is required.
Signed-off-by: Imre Deak <imre.d...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 61 +++++++++++++--------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 ++++++++++--------
2 files changed, 68 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7067ee3a4bd36..53697f361f950 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2187,29 +2187,25 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return 0;
}
-static int
-intel_dp_compute_link_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config,
- struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+static void
+intel_dp_compute_config_limits(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ bool respect_downstream_limits,
+ struct link_config_limits *limits)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->hw.adjusted_mode;
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct link_config_limits limits;
- bool joiner_needs_dsc = false;
- int ret;
+ &crtc_state->hw.adjusted_mode;
- limits.min_rate = intel_dp_common_rate(intel_dp, 0);
- limits.max_rate = intel_dp_max_link_rate(intel_dp);
+ limits->min_rate = intel_dp_common_rate(intel_dp, 0);
+ limits->max_rate = intel_dp_max_link_rate(intel_dp);
- limits.min_lane_count = 1;
- limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
+ limits->min_lane_count = 1;
+ limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
- limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
- limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config,
respect_downstream_limits);
+ limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
+ respect_downstream_limits);
if (intel_dp->use_max_params) {
/*
@@ -2220,16 +2216,35 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
* configuration, and typically on older panels these
* values correspond to the native resolution of the panel.
*/
- limits.min_lane_count = limits.max_lane_count;
- limits.min_rate = limits.max_rate;
+ limits->min_lane_count = limits->max_lane_count;
+ limits->min_rate = limits->max_rate;
}
- intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
"max rate %d max bpp %d pixel clock %iKHz\n",
- limits.max_lane_count, limits.max_rate,
- limits.max_bpp, adjusted_mode->crtc_clock);
+ limits->max_lane_count, limits->max_rate,
+ limits->max_bpp, adjusted_mode->crtc_clock);
+}
+
+static int
+intel_dp_compute_link_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ bool respect_downstream_limits)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct link_config_limits limits;
+ bool joiner_needs_dsc = false;
+ int ret;
+
+ intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits, &limits);
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c82..218c2dfd57adc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -306,6 +306,35 @@ static bool intel_dp_mst_has_audio(const struct
drm_connector_state *conn_state)
return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}
+static void
+intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct link_config_limits *limits)
+{
+ /*
+ * for MST we always configure max link bw - the spec doesn't
+ * seem to suggest we should do otherwise.
+ */
+ limits->min_rate = limits->max_rate =
+ intel_dp_max_link_rate(intel_dp);
+
+ limits->min_lane_count = limits->max_lane_count =
+ intel_dp_max_lane_count(intel_dp);
+
+ limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ /*
+ * FIXME: If all the streams can't fit into the link with
+ * their current pipe_bpp we should reduce pipe_bpp across
+ * the board until things start to fit. Until then we
+ * limit to <= 8bpc since that's what was hardcoded for all
+ * MST streams previously. This hack should be removed once
+ * we have the proper retry logic in place.
+ */
+ limits->max_bpp = min(crtc_state->pipe_bpp, 24);
+
+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -329,28 +358,7 @@ static int intel_dp_mst_compute_config(struct
intel_encoder *encoder,
intel_dp_mst_has_audio(conn_state) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
- /*
- * for MST we always configure max link bw - the spec doesn't
- * seem to suggest we should do otherwise.
- */
- limits.min_rate =
- limits.max_rate = intel_dp_max_link_rate(intel_dp);
-
- limits.min_lane_count =
- limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
-
- limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
- /*
- * FIXME: If all the streams can't fit into the link with
- * their current pipe_bpp we should reduce pipe_bpp across
- * the board until things start to fit. Until then we
- * limit to <= 8bpc since that's what was hardcoded for all
- * MST streams previously. This hack should be removed once
- * we have the proper retry logic in place.
- */
- limits.max_bpp = min(pipe_config->pipe_bpp, 24);
-
- intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
+ intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
conn_state, &limits);
--
2.37.2
