ping @Eric Farman.
ccw is the only tricky player in this series. Please help take a look in case of
any oversight here.
> From: Tian, Kevin
> Sent: Thursday, September 1, 2022 10:38 PM
>
> ccw is the only exception which cannot use vfio_alloc_device() because
> its private device structure is d
== Series Details ==
Series: drm/i915: Noop lrc_init_wa_ctx() on recent/future platforms
URL : https://patchwork.freedesktop.org/series/108278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12090_full -> Patchwork_108278v1_full
=
Hi Kevin,
On 9/1/22 16:37, Kevin Tian wrote:
> From: Yi Liu
>
> and replace kref. With it a 'vfio-dev/vfioX' node is created under the
> sysfs path of the parent, indicating the device is bound to a vfio
> driver, e.g.:
>
> /sys/devices/pci\:6f/\:6f\:01.0/vfio-dev/vfio0
>
> It is also a p
Hi Kevin,
On 9/8/22 08:19, Tian, Kevin wrote:
>> From: Eric Auger
>> Sent: Thursday, September 8, 2022 3:28 AM
>>> +/*
>>> + * Alloc and initialize vfio_device so it can be registered to vfio
>>> + * core.
>>> + *
>>> + * Drivers should use the wrapper vfio_alloc_device() for allocation.
>>> + *
On Wed, Sep 07, 2022 at 02:23:51PM -0400, Lyude Paul wrote:
> Surprised this didn't come up on Intel's CI (or at least it certainly didn't
> when the series that introduced this was tested),
Yes, this was a problem in CI which didn't have any MST sinks. Now there
is and the problem is visible:
htt
On 2022/9/8 17:06, Eric Auger wrote:
Hi Kevin,
On 9/1/22 16:37, Kevin Tian wrote:
From: Yi Liu
and replace kref. With it a 'vfio-dev/vfioX' node is created under the
sysfs path of the parent, indicating the device is bound to a vfio
driver, e.g.:
/sys/devices/pci\:6f/\:6f\:01.0/vfio-
On Thu, Sep 08, 2022 at 05:09:40PM +0800, Zheng Hacker wrote:
> Hi Zhenyu,
>
> This issue has been open for a few days. Could you plz write a patch
> for that :) I'm not familiar with the logical code here.
As this is only able to be hit in a theoretical system, it isn't that
high of a priority,
On 07/09/2022 16:03, Dixit, Ashutosh wrote:
On Wed, 07 Sep 2022 00:28:48 -0700, Tvrtko Ursulin wrote:
On 06/09/2022 19:29, Umesh Nerlige Ramappa wrote:
On Thu, Sep 01, 2022 at 04:55:22PM -0700, Dixit, Ashutosh wrote:
On Wed, 31 Aug 2022 15:45:49 -0700, Umesh Nerlige Ramappa wrote:
[snip]
On 9/8/22 11:17, Yi Liu wrote:
> On 2022/9/8 17:06, Eric Auger wrote:
>> Hi Kevin,
>>
>> On 9/1/22 16:37, Kevin Tian wrote:
>>> From: Yi Liu
>>>
>>> and replace kref. With it a 'vfio-dev/vfioX' node is created under the
>>> sysfs path of the parent, indicating the device is bound to a vfio
>>>
On 07/09/2022 14:48, Tvrtko Ursulin wrote:
On 06/09/2022 17:14, Tvrtko Ursulin wrote:
On 05/09/2022 10:34, Tvrtko Ursulin wrote:
On 01/09/2022 19:38, Niranjana Vishwanathapura wrote:
So far, different views (normal, partial, rotated and remapped)
into the same object are only supported fo
On 07/09/2022 18:26, Nirmoy Das wrote:
Fix regression introduced by commit:
"drm/i915: Individualize fences before adding to dma_resv obj"
which sets obj->read_domains to 0 for both read and write paths.
Also set obj->write_domain to 0 on read path which was removed by
the commit.
References: ht
On 9/8/2022 11:40 AM, Matthew Auld wrote:
On 07/09/2022 18:26, Nirmoy Das wrote:
Fix regression introduced by commit:
"drm/i915: Individualize fences before adding to dma_resv obj"
which sets obj->read_domains to 0 for both read and write paths.
Also set obj->write_domain to 0 on read path whi
On 9/8/2022 3:01 AM, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* drm/i915: Set correct domains values at
_i915_vma_move_to_active
*URL:* https://patchwork.freedesktop.org/series/108258/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patch
On 08/09/2022 10:46, Das, Nirmoy wrote:
On 9/8/2022 11:40 AM, Matthew Auld wrote:
On 07/09/2022 18:26, Nirmoy Das wrote:
Fix regression introduced by commit:
"drm/i915: Individualize fences before adding to dma_resv obj"
which sets obj->read_domains to 0 for both read and write paths.
Also set
== Series Details ==
Series: Revert "drm/i915/dg2: extend Wa_1409120013 to DG2" (rev2)
URL : https://patchwork.freedesktop.org/series/108266/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12091_full -> Patchwork_108266v2_full
===
On 9/8/2022 12:13 PM, Matthew Auld wrote:
On 08/09/2022 10:46, Das, Nirmoy wrote:
On 9/8/2022 11:40 AM, Matthew Auld wrote:
On 07/09/2022 18:26, Nirmoy Das wrote:
Fix regression introduced by commit:
"drm/i915: Individualize fences before adding to dma_resv obj"
which sets obj->read_domains
Hi,
On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
> Perf limit reasons bit positions were off by one.
>
> Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
> Cc: sta...@vger.kernel.org # v5.18+
> Cc: Sujaritha Sundaresan
> Cc: Andi Shyti
> Signed-off
== Series Details ==
Series: Initial Meteorlake Support (rev8)
URL : https://patchwork.freedesktop.org/series/106786/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12091_full -> Patchwork_106786v8_full
Summary
---
**
On Wed, Sep 07, 2022 at 01:30:41PM -0700, Lucas De Marchi wrote:
> Continue converting the driver to the convention of last version first,
> extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
> be handled by the first branch.
>
> With the new ranges it's easier to see what plat
Hi,
On Tue, Aug 30, 2022 at 10:01:11AM -0300, Maíra Canal wrote:
> On 8/29/22 10:11, Maxime Ripard wrote:
> > Multiple drivers (meson, vc4, sun4i) define analog TV 525-lines and
> > 625-lines modes in their drivers.
> >
> > Since those modes are fairly standard, and that we'll need to use them
>
Hi Noralf,
On Tue, Aug 30, 2022 at 09:01:08PM +0200, Noralf Trønnes wrote:
> > +static const struct drm_prop_enum_list tv_mode_names[] = {
>
> Maybe call it legacy_tv_mode_enums?
>
> >
> > + { VC4_VEC_TV_MODE_NTSC, "NTSC", },
> >
> > + { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", },
> >
> > + {
== Series Details ==
Series: i915: freq caps and perf_limit_reasons changes for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12091_full -> Patchwork_108091v2_full
===
On Thu, Sep 08, 2022 at 01:31:34PM +0200, Mateusz Kwiatkowski wrote:
> W dniu 08.09.2022 o 13:23, Maxime Ripard pisze:
> > Hi Noralf,
> >
> > On Tue, Aug 30, 2022 at 09:01:08PM +0200, Noralf Trønnes wrote:
> >>> +static const struct drm_prop_enum_list tv_mode_names[] = {
> >>
> >> Maybe call it leg
On 06/09/2022 18:46, Ville Syrjala wrote:
From: Ville Syrjälä
On gen3 the selftests are pretty much always tripping this:
<4> [383.822424] pci :00:02.0: drm_WARN_ON(dev_priv->mm.shrink_count)
<4> [383.822546] WARNING: CPU: 2 PID: 3560 at
drivers/gpu/drm/i915/i915_gem.c:1223 i915_gem_clea
On 9/8/2022 4:12 PM, Andi Shyti wrote:
Hi,
On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
Perf limit reasons bit positions were off by one.
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: sta...@vger.kernel.org # v5.18+
Cc: Sujaritha Sundares
Hi Dave and Daniel,
this is the weekly PR for drm-misc-fixes.
Best regards
Thomas
drm-misc-fixes-2022-09-08:
Short summary of fixes pull:
* edid: Fix EDID 1.4 range-descriptor parsing
* panfrost: Fix devfreq OPP
* ttm: Fix ghost-object bulk moves
The following changes since commit a3f7c10a26
On Thu, Sep 08, 2022 at 06:07:08PM +0530, Sundaresan, Sujaritha wrote:
>
> On 9/8/2022 4:12 PM, Andi Shyti wrote:
> > Hi,
> >
> > On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
> > > Perf limit reasons bit positions were off by one.
> > >
> > > Fixes: fa68bff7cf27 ("drm/i915/gt:
On 31.08.2022 14:49, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-12] are mapped to TC ports.
>
> v2:
> - Drop unused GPIO pins(MattR)
>
> BSpec: 4
On 01.09.2022 23:03, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-12] are mapped to TC ports.
>
> v2:
> - Drop unused GPIO pins(MattR)
>
> BSpec: 4
On Wed, Aug 31, 2022 at 04:23:21AM +0200, Mateusz Kwiatkowski wrote:
> I tested your patchset on my Pi and it mostly works. Good work! However,
> I noticed a couple of issues.
>
> > -static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
> > - struct drm_crtc_state
On Thu, Sep 08, 2022 at 01:23:50PM +0100, Tvrtko Ursulin wrote:
>
> On 06/09/2022 18:46, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On gen3 the selftests are pretty much always tripping this:
> > <4> [383.822424] pci :00:02.0: drm_WARN_ON(dev_priv->mm.shrink_count)
> > <4> [383.822
Hi Dave and Daniel,
A few fixes, but most targeting stable.
Here goes drm-intel-fixes-2022-09-08:
- Fix MIPI sequence block copy from BIOS' table. (Ville)
- Fix PCODE min freq setup when GuC's SLPC is in use. (Rodrigo)
- Implement Workaround for eDP. (Ville)
- Fix has_flat_ccs selection for DG1.
On Mon, 29 Aug 2022 15:11:50 +0200, Maxime Ripard wrote:
> Our mode_set implementation can be merged into our atomic_enable
> implementation to simplify things, so let's do this.
>
>
Applied to drm/drm-misc (drm-misc-next).
Thanks!
Maxime
Hi Ville,
I fixed a similar issue in DII but I couldn't reproduce it in drm
http://intel-gfx-pw.fi.intel.com/patch/228850/?series=15910&rev=2.
I wonder if that fixes the problem you are facing then I can send that
to drm.
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/
On 08/09/2022 15:32, Das, Nirmoy wrote:
Hi Ville,
I fixed a similar issue in DII but I couldn't reproduce it in drm
http://intel-gfx-pw.fi.intel.com/patch/228850/?series=15910&rev=2.
I wonder if that fixes the problem you are facing then I can send that
to drm.
diff --git a/drivers/gpu/d
On Thu, Sep 08, 2022 at 04:32:56PM +0200, Das, Nirmoy wrote:
> Hi Ville,
>
>
> I fixed a similar issue in DII but I couldn't reproduce it in drm
>
> http://intel-gfx-pw.fi.intel.com/patch/228850/?series=15910&rev=2.
>
> I wonder if that fixes the problem you are facing then I can send that
> t
== Series Details ==
Series: drm/i915: Kick rcu harder to free objects (rev2)
URL : https://patchwork.freedesktop.org/series/108196/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/108196/revisions/2/mbox/ not
applied
Applying: drm/i915: Kick rcu h
On Thu, 08 Sep 2022 05:37:08 -0700, Sundaresan, Sujaritha wrote:
>
> On 9/8/2022 4:12 PM, Andi Shyti wrote:
> > Hi,
> >
> > On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
> >> Perf limit reasons bit positions were off by one.
> >>
> >> Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs t
Perf limit reasons bit positions were off by one.
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: sta...@vger.kernel.org # v5.18+
Signed-off-by: Ashutosh Dixit
Acked-by: Andi Shyti
Reviewed-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_reg.h | 16 +
On Thu, 08 Sep 2022 08:58:21 -0700, Ashutosh Dixit wrote:
>
> Perf limit reasons bit positions were off by one.
>
> Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
> Cc: sta...@vger.kernel.org # v5.18+
> Signed-off-by: Ashutosh Dixit
> Acked-by: Andi Shyti
> Reviewed-
On 9/7/2022 11:01 PM, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* GSC support for XeHP SDV and DG2 (rev5)
*URL:* https://patchwork.freedesktop.org/series/106638/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v5/index.
On 07-09-2022 05:19, Matt Roper wrote:
> We're going to introduce an additional intel_gt for MTL's media unit
> soon. Let's provide a bit more multi-GT initialization framework in
> preparation for that. The initialization will pull the list of GTs for
> a platform from the device info structu
== Series Details ==
Series: drm/i915/gt: Fix perf limit reasons bit positions (rev2)
URL : https://patchwork.freedesktop.org/series/108277/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 07-09-2022 05:19, Matt Roper wrote:
> Xe_LPM+ platforms have "standalone media." I.e., the media unit is
> designed as an additional GT with its own engine list, GuC, forcewake,
> etc. Let's allow platforms to include media GTs in their device info.
>
> v2:
> - Simplify GSI register handl
== Series Details ==
Series: drm/i915/gt: Fix perf limit reasons bit positions (rev2)
URL : https://patchwork.freedesktop.org/series/108277/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12098 -> Patchwork_108277v2
Summary
On Thu, Sep 08, 2022 at 02:08:55PM +0300, Ville Syrjälä wrote:
On Wed, Sep 07, 2022 at 01:30:41PM -0700, Lucas De Marchi wrote:
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first b
struct intel_dsb can be an opaque type, hidden in intel_dsb.c. Make it
so. Reduce related includes while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_dsb.c |
On Fri, Sep 02, 2022 at 03:10:54PM -0700, Radhakrishna Sripada wrote:
> Future platforms can read the IP version from a register and the
> IP version numbers need not be hard coded in device info. Move the
> ip version for media and display to runtime info.
>
> On platforms where hard coding of IP
On Thu, Sep 01, 2022 at 11:03:34PM -0700, Radhakrishna Sripada wrote:
> From: José Roberto de Souza
>
> The GMD step field do not properly match the current stepping convention
> that we use(STEP_A0, STEP_A1, STEP_B0...).
>
> One platform could have { arch = 12, rel = 70, step = 1 } and the
> ac
== Series Details ==
Series: drm/i915/dsb: hide struct intel_dsb better
URL : https://patchwork.freedesktop.org/series/108310/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dsb: hide struct intel_dsb better
URL : https://patchwork.freedesktop.org/series/108310/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12099 -> Patchwork_108310v1
Summary
---
**S
On Thu, Sep 08, 2022 at 07:57:02PM +0300, Jani Nikula wrote:
> struct intel_dsb can be an opaque type, hidden in intel_dsb.c. Make it
> so. Reduce related includes while at it.
>
> Signed-off-by: Jani Nikula
One thing I was mildly worried about with dsb is the cost
of creating the batch (updatin
On Wed, Sep 07, 2022 at 04:33:17PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper
>
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the driver conditions to re
On Thu, Sep 01, 2022 at 11:03:36PM -0700, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-12] are mapped to TC ports.
>
> v2:
> - Drop unused GPIO pins
On Thu, Sep 01, 2022 at 11:03:37PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak
>
> Add support for display power wells on MTL. The differences from XE_LPD:
> - The AUX HW block is moved to the PICA block, where the registers are on
> an always-on power well and the functionality needs
On Thu, Sep 08, 2022 at 11:07:16AM -0700, Matt Roper wrote:
> On Thu, Sep 01, 2022 at 11:03:37PM -0700, Radhakrishna Sripada wrote:
> > From: Imre Deak
> >
> > Add support for display power wells on MTL. The differences from XE_LPD:
> > - The AUX HW block is moved to the PICA block, where the reg
On Thu, Sep 01, 2022 at 11:03:38PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak
>
> On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
> changed wrt. previous platforms, adjust the code accordingly.
>
> Signed-off-by: Imre Deak
> Signed-off-by: Radhakrishna Sripada
As no
On Thu, 08 Sep 2022, Ville Syrjälä wrote:
> On Thu, Sep 08, 2022 at 07:57:02PM +0300, Jani Nikula wrote:
>> struct intel_dsb can be an opaque type, hidden in intel_dsb.c. Make it
>> so. Reduce related includes while at it.
>>
>> Signed-off-by: Jani Nikula
>
> One thing I was mildly worried about
On 06/09/2022 23:35, Umesh Nerlige Ramappa wrote:
On Tue, Sep 06, 2022 at 10:48:50PM +0300, Lionel Landwerlin wrote:
On 23/08/2022 23:41, Umesh Nerlige Ramappa wrote:
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
Signe
From: Ville Syrjälä
Hoist all the skl+ wm related stuff from intel_pm.c into
its own file.
Ville Syrjälä (3):
drm/i915: Split intel_read_wm_latency() into per-platform versions
drm/i915: Extract skl_watermark.c
drm/i915: Use REG_FIELD_GET() to extract skl+ wm latencies
drivers/gpu/drm/i9
From: Ville Syrjälä
No reaon to have this humongous if ladder in intel_read_wm_latency().
Just split it into nicer per-platforms functions.
Also do the s/dev_priv/i915/ while touching all of this code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 201 +---
From: Ville Syrjälä
Replace the hand rolled stuff with REG_FIELD_GET() for reading
out the skl+ watermark latencies.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 22 +++-
drivers/gpu/drm/i915/i915_reg.h | 8 +++
2 files chang
On 9/8/2022 4:55 PM, Tvrtko Ursulin wrote:
On 08/09/2022 15:32, Das, Nirmoy wrote:
Hi Ville,
I fixed a similar issue in DII but I couldn't reproduce it in drm
http://intel-gfx-pw.fi.intel.com/patch/228850/?series=15910&rev=2.
I wonder if that fixes the problem you are facing then I can se
== Series Details ==
Series: drm/i915: Move skl+ wm code into its own file
URL : https://patchwork.freedesktop.org/series/108313/
State : warning
== Summary ==
Error: dim checkpatch failed
eff551e7ad3c drm/i915: Split intel_read_wm_latency() into per-platform versions
129d570bf892 drm/i915: Ex
== Series Details ==
Series: drm/i915: Move skl+ wm code into its own file
URL : https://patchwork.freedesktop.org/series/108313/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 9/8/2022 5:11 PM, Ville Syrjälä wrote:
On Thu, Sep 08, 2022 at 04:32:56PM +0200, Das, Nirmoy wrote:
Hi Ville,
I fixed a similar issue in DII but I couldn't reproduce it in drm
http://intel-gfx-pw.fi.intel.com/patch/228850/?series=15910&rev=2.
I wonder if that fixes the problem you are f
== Series Details ==
Series: drm/i915: Move skl+ wm code into its own file
URL : https://patchwork.freedesktop.org/series/108313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12100 -> Patchwork_108313v1
Summary
---
On Thu, Sep 01, 2022 at 11:03:40PM -0700, Radhakrishna Sripada wrote:
> Display version 14 platforms have different credits values
> compared to ADL-P. Update the credits based on pipe usage.
>
> v2: Simplify DBOX BW Credit definition(MattR)
>
> Bspec: 49213
>
> Cc: Jose Roberto de Souza
> Cc:
i915_gem_drain_freed_objects() might not be enough to
free all the objects and RCU delayed work might get
scheduled after the i915 device struct gets freed.
Call i915_gem_drain_workqueue() to catch all RCU delayed work.
Suggested-by: Chris Wilson
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i
i915_gem_drain_workqueue() call i915_gem_drain_freed_objects()
so no need to call that again.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_gem.c | 2 --
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 1 -
2 files changed, 3 deletions(-)
diff --git a/drivers/gpu/d
deletions(-)
---
base-commit: adc57f2b82896fed07bc8e34956c15bb1448fca2
change-id: 20220908-if-ladder-df33a06d4f4e
Best regards,
--
Lucas De Marchi
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_g
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
With the new ranges it's easier to see what platform a branch started to
be taken. Besides the >= 11 change, the branch tak
Instead of calling read_clock_frequency() to walk the if/else ladder
per platform, move the ladder to intel_gt_init_clock_frequency() and
use one function per branch.
With the new logic, it's now clear the call to
gen9_get_crystal_clock_freq() was just dead code, as gen9 is handled by
another func
On Thu, Sep 01, 2022 at 11:03:41PM -0700, Radhakrishna Sripada wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> In Display version 14, Transcoder Chicken Registers have updated address.
> This patch performs checks to use the right register when required.
>
> v2: Omit display version check
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix a potential UAF at device
unload
URL : https://patchwork.freedesktop.org/series/108314/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12100 -> Patchwork_108314v1
== Series Details ==
Series: drm/i915/gt: Fix perf limit reasons bit positions (rev2)
URL : https://patchwork.freedesktop.org/series/108277/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12098_full -> Patchwork_108277v2_full
On 9/6/2022 4:49 PM, Matt Roper wrote:
In a multi-GT system we need to initialize MMIO access for each GT, not
just the primary GT.
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_driver.c | 27 +
On 9/6/2022 4:49 PM, Matt Roper wrote:
In preparation for enabling a second GT, there are a number of GT/uncore
operations that happen during initialization or suspend flows that need
to be performed on each GT, not just the primary,
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Re
== Series Details ==
Series: drm/i915: A couple of if/else ladder refactors
URL : https://patchwork.freedesktop.org/series/108315/
State : warning
== Summary ==
Error: dim checkpatch failed
8e2c6bd18bc2 drm/i915: Invert if/else ladder for frequency read
-:120: WARNING:UNNECESSARY_ELSE: else is
== Series Details ==
Series: drm/i915: A couple of if/else ladder refactors
URL : https://patchwork.freedesktop.org/series/108315/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bito
== Series Details ==
Series: drm/i915: A couple of if/else ladder refactors
URL : https://patchwork.freedesktop.org/series/108315/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12100 -> Patchwork_108315v1
Summary
---
On 9/6/2022 4:49 PM, Matt Roper wrote:
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the sta
On 9/6/2022 4:49 PM, Matt Roper wrote:
When we hook up interrupts (in the next patch), interrupts for the media
GT are still processed as part of the primary GT's interrupt flow. As
such, we should share the same IRQ lock with the primary GT. Let's
convert gt->irq_lock into a pointer and jus
>
> On Fri, Aug 19, 2022 at 03:53:22PM -0700, Daniele Ceraolo Spurio wrote:
> > --- a/drivers/misc/mei/hw-me.c
> > +++ b/drivers/misc/mei/hw-me.c
> > @@ -590,7 +590,10 @@ static int mei_me_hbuf_write(struct mei_device
> *dev,
> > u32 dw_cnt;
> > int empty_slots;
> >
> > - if (WARN_ON(!
On Thu, Sep 08, 2022 at 02:16:27PM -0700, Ceraolo Spurio, Daniele wrote:
>
>
> On 9/6/2022 4:49 PM, Matt Roper wrote:
> > GT non-engine registers (referred to as "GSI" registers by the spec)
> > have the same relative offsets on standalone media as they do on the
> > primary GT, just with an addi
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the standalone media's
intel_uncore structure, it c
On 9/8/2022 3:45 PM, Matt Roper wrote:
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the sta
On Thu, Sep 08, 2022 at 09:32:12PM +0300, Lionel Landwerlin wrote:
On 06/09/2022 23:35, Umesh Nerlige Ramappa wrote:
On Tue, Sep 06, 2022 at 10:48:50PM +0300, Lionel Landwerlin wrote:
On 23/08/2022 23:41, Umesh Nerlige Ramappa wrote:
Some SKUs of same gen12 platform may have different oactxctr
== Series Details ==
Series: i915: Add "standalone media" support for MTL (rev5)
URL : https://patchwork.freedesktop.org/series/107908/
State : warning
== Summary ==
Error: dim checkpatch failed
6c1062d5ca5c drm/i915: Move locking and unclaimed check into
mmio_debug_{suspend, resume}
71776530
== Series Details ==
Series: i915: Add "standalone media" support for MTL (rev5)
URL : https://patchwork.freedesktop.org/series/107908/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: i915: Add "standalone media" support for MTL (rev5)
URL : https://patchwork.freedesktop.org/series/107908/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12101 -> Patchwork_107908v5
Summary
-
== Series Details ==
Series: drm/i915/dsb: hide struct intel_dsb better
URL : https://patchwork.freedesktop.org/series/108310/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12099_full -> Patchwork_108310v1_full
Summary
The following changes since commit 2f2f0181581d3e35bfdb9fc65f609ee9d3fbaeb7:
Mellanox: Add new mlxsw_spectrum firmware xx.2010.3146 (2022-09-02 07:28:59
-0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dg2_huc_7.10.6
for you to fetch changes up
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
operation itself is relatively simple (just send a message to the GSC
with the physical address of the HuC in LMEM), but there are timing
changes that requires special attention. In particular, to send a PXP
command we need to
Please ignore this cover letter, I've only realized I was missing a
title and aborted the git-send after sending it. Proper series coming in
a couple of mins.
Daniele
On 9/8/2022 5:10 PM, Daniele Ceraolo Spurio wrote:
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
op
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
operation itself is relatively simple (just send a message to the GSC
with the physical address of the HuC in LMEM), but there are timing
changes that requires special attention. In particular, to send a PXP
command we need to
From: Tomas Winkler
Fix kdoc for struct mei_ext_hdr and mei_ext_begin().
V4: New in the series
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
---
drivers/misc/mei/hw.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/driv
From: Tomas Winkler
GSC extend header is of variable size and data
is provided in a sgl list inside the header
and not in the data buffers, need to enable the path.
V2:
1. Add missing kdoc for mei_cl_cb
2. In mei_me_hbuf_write()
use dev_err() when validationg parameters instead of WARN_ON()
The GSC will perform both the load and the authentication, so we just
need to check the auth bit after the GSC has replied.
Since we require the PXP module to load the HuC, the earliest we can
trigger the load is during the pxp_bind operation.
Note that GSC-loaded HuC survives GT reset, so we need
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