[Intel-gfx] [PATCH] drm/i915/guc: Remove log size module parameters

Remove the module parameters for configuring GuC log size. We should instead rely on tuning the defaults to be usable for reporting bugs. Fixes: 8ad0152afb1b ("drm/i915/guc: Make GuC log sizes runtime configurable") Signed-off-by: Joonas Lahtinen Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Tvrtko Urs

Re: [Intel-gfx] [PATCH] drm/i915/guc: Remove log size module parameters

On Fri, 26 Aug 2022, Joonas Lahtinen wrote: > Remove the module parameters for configuring GuC log size. > > We should instead rely on tuning the defaults to be usable for > reporting bugs. Reviewed-by: Jani Nikula > > Fixes: 8ad0152afb1b ("drm/i915/guc: Make GuC log sizes runtime configurable"

Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel tree

On Fri, 26 Aug 2022, Stephen Rothwell wrote: > Hi all, > > After merging the drm-intel tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > > drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function > 'intel_guc_dump_time_info': > drivers/gpu/drm/i915/gt/uc/intel_guc.c:399:9: err

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Remove log size module parameters

== Series Details == Series: drm/i915/guc: Remove log size module parameters URL : https://patchwork.freedesktop.org/series/107780/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets (rev2)

== Series Details == Series: drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets (rev2) URL : https://patchwork.freedesktop.org/series/107620/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_107620v2_full ===

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Remove log size module parameters

== Series Details == Series: drm/i915/guc: Remove log size module parameters URL : https://patchwork.freedesktop.org/series/107780/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12030 -> Patchwork_107780v1 Summary ---

[Intel-gfx] [PATCH][next] drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat"

There is a spelling mistake in a drm_err message. Fix it. Signed-off-by: Colin Ian King --- drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/se

[Intel-gfx] [PATCH 0/5] drm/i915: some BUG_ON() removals

Avoid BUG_ON(). Remove some of the low-hanging fruit. Jani Nikula (5): drm/i915/crt: replace BUG_ON() with drm_WARN_ON() drm/i915/dpll: replace BUG_ON() with drm_WARN_ON() drm/i915/pch: replace BUG_ON() with drm_WARN_ON() drm/i915/perf: replace BUG_ON() with WARN_ON() drm/i915/fence: rep

[Intel-gfx] [PATCH 2/5] drm/i915/dpll: replace BUG_ON() with drm_WARN_ON()

Avoid BUG_ON(). Actually check the dpll count and bail out loudly with drm_WARN_ON() from the loop before overflowing i915->dpll.shared_dplls[]. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/

[Intel-gfx] [PATCH 1/5] drm/i915/crt: replace BUG_ON() with drm_WARN_ON()

Avoid BUG_ON(). Replace with drm_WARN_ON() and early return. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 6a

[Intel-gfx] [PATCH 4/5] drm/i915/perf: replace BUG_ON() with WARN_ON()

Avoid BUG_ON(). Replace with WARN_ON() and early return. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_perf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index f3c23fe9ad9c..0defbb43ceea 1006

[Intel-gfx] [PATCH 5/5] drm/i915/fence: replace BUG_ON() with BUILD_BUG_ON()

Avoid BUG_ON(). Since __i915_sw_fence_init() is always called via a wrapper macro, we can replace it with a compile time BUILD_BUG_ON(). Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_sw_fence.c | 2 -- drivers/gpu/drm/i915/i915_sw_fence.h | 6 +- 2 files changed, 5 insertions(+),

[Intel-gfx] [PATCH 3/5] drm/i915/pch: replace BUG_ON() with drm_WARN_ON()

Avoid BUG_ON(). Replace with drm_WARN_ON(). Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pch_refclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat"

== Series Details == Series: drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat" URL : https://patchwork.freedesktop.org/series/107784/ State : warning == Summary == Error: dim checkpatch failed 5a0ea1b0f38f drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat" -:22: WARNING:FR

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat"

== Series Details == Series: drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat" URL : https://patchwork.freedesktop.org/series/107784/ State : success == Summary == CI Bug Log - changes from CI_DRM_12030 -> Patchwork_107784v1 Summ

[Intel-gfx] [PATCH 0/4] Add DP MST DSC support to i915

Currently we have only DSC support for DP SST. Stanislav Lisovskiy (4): drm: Add missing DP DSC extended capability definitions. drm/i915: Fix intel_dp_mst_compute_link_config drm/i915: Add DSC support to MST path drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate functi

[Intel-gfx] [PATCH 2/4] drm/i915: Fix intel_dp_mst_compute_link_config

We currently always exit that bpp loop because drm_dp_atomic_find_vcpi_slots doesn't care if we actually can fit those or not. I think that wasn't the initial intention here, especially when we keep trying with lower bpps, we are supposed to keep trying until we actually find some _working_ configu

[Intel-gfx] [PATCH 3/4] drm/i915: Add DSC support to MST path

Whenever we are not able to get enough timeslots for required PBN, let's try to allocate those using DSC, just same way as we do for SST. v2: Removed intel_dp_mst_dsc_compute_config and refactored intel_dp_dsc_compute_config to support timeslots as a parameter(Ville Syrjälä) v3: - Rebased

[Intel-gfx] [PATCH 1/4] drm: Add missing DP DSC extended capability definitions.

Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Reviewed-by: Vinod Govindapillai Signed-off-by: Stanislav Lisovskiy

[Intel-gfx] [PATCH 4/4] drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function

We are using almost same code to loop through bpps while calling drm_dp_atomic_find_vcpi_slots - lets remove this duplication by introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 85 +++

[Intel-gfx] [RFC v1 0/1] Enabling Smooth Sync Feature.

When async flips are enabled to reduce latency, onscreen tears caused by the immediate transition from an older image to a newer image within a frame can be observable.The Smooth Sync feature uses both blending and dithering to smoothly transition from the old image to the new image over a programm

[Intel-gfx] [PATCH v2] drm/i915/guc: Remove log size module parameters

Remove the module parameters for configuring GuC log size. We should instead rely on tuning the defaults to be usable for reporting bugs. v2: - Use correct 1M unit Fixes: 8ad0152afb1b ("drm/i915/guc: Make GuC log sizes runtime configurable") Signed-off-by: Joonas Lahtinen Cc: Jani Nikula Cc: R

Re: [Intel-gfx] [PATCH] drm/i915/slpc: Set rps' min and max frequencies even with SLPC.

On Thu, 2022-08-25 at 16:59 -0700, Dixit, Ashutosh wrote: On Thu, 25 Aug 2022 15:23:15 -0700, Rodrigo Vivi wrote: We need to inform PCODE of a desired ring frequencies so PCODE update the memory frequencies to us. rps->min_freq and rps->max_freq are the frequencies used in that request. However th

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: some BUG_ON() removals

== Series Details == Series: drm/i915: some BUG_ON() removals URL : https://patchwork.freedesktop.org/series/107785/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC

We need to inform PCODE of a desired ring frequencies so PCODE update the memory frequencies to us. rps->min_freq and rps->max_freq are the frequencies used in that request. However they were unset when SLPC was enabled and PCODE never updated the memory freq. v2 (as Suggested by Ashutosh): if SLP

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add DP MST DSC support to i915 (rev8)

== Series Details == Series: Add DP MST DSC support to i915 (rev8) URL : https://patchwork.freedesktop.org/series/101492/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/101492/revisions/8/mbox/ not applied Applying: drm: Add missing DP DSC extende

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: some BUG_ON() removals

== Series Details == Series: drm/i915: some BUG_ON() removals URL : https://patchwork.freedesktop.org/series/107785/ State : success == Summary == CI Bug Log - changes from CI_DRM_12031 -> Patchwork_107785v1 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Remove log size module parameters (rev2)

== Series Details == Series: drm/i915/guc: Remove log size module parameters (rev2) URL : https://patchwork.freedesktop.org/series/107780/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Remove log size module parameters (rev2)

== Series Details == Series: drm/i915/guc: Remove log size module parameters (rev2) URL : https://patchwork.freedesktop.org/series/107780/ State : success == Summary == CI Bug Log - changes from CI_DRM_12031 -> Patchwork_107780v2 Summary --

Re: [Intel-gfx] [PATCH 1/5] drm/i915/crt: replace BUG_ON() with drm_WARN_ON()

On Fri, Aug 26, 2022 at 11:38:13AM +0300, Jani Nikula wrote: > Avoid BUG_ON(). Replace with drm_WARN_ON() and early return. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_crt.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/

Re: [Intel-gfx] [PATCH 2/5] drm/i915/dpll: replace BUG_ON() with drm_WARN_ON()

On Fri, Aug 26, 2022 at 11:38:14AM +0300, Jani Nikula wrote: > Avoid BUG_ON(). Actually check the dpll count and bail out loudly with > drm_WARN_ON() from the loop before overflowing > i915->dpll.shared_dplls[]. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Replace kmap() with kmap_local_page()

== Series Details == Series: drm/i915: Replace kmap() with kmap_local_page() URL : https://patchwork.freedesktop.org/series/107277/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_107277v1_full Summary

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev4)

== Series Details == Series: drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev4) URL : https://patchwork.freedesktop.org/series/107766/ State : success == Summary == CI Bug Log - changes from CI_DRM_12031 -> Patchwork_107766v4

[Intel-gfx] [PATCH 2/2] drm/i915/mtl: Limit scaler input to 4k in plane scaling

As part of die area reduction max input source modified to 4096 for MTL so modified range check logic of scaler. Cc: Manasi Navare Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/skl_scaler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i

[Intel-gfx] [PATCH 1/2] drm/i915/mtl: Added restriction for plane downscaling

The second Scaler (i.e. Scaler 2) does not support vertical downscaling (i.e. it's vertical scale factor must not be greater than 1.0). So, vertical plane downscaling is not supported on MTL, scale factor modified accordingly. Cc: Ville Syrjälä Cc: Manasi Navare Signed-off-by: Animesh Manna ---

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave and Daniel, Sorry for the delay here. I hope we still have time for these. But no big deal if this needs to wait until next week. Here goes drm-intel-fixes-2022-08-26: - GVT fixes including fix for a CommetLake regression in mmio table and misc doc and typo fixes - Fix CCS handling (Mat

[Intel-gfx] ✓ Fi.CI.IGT: success for Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation

== Series Details == Series: Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation URL : https://patchwork.freedesktop.org/series/107231/ State : success == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_1072

Re: [Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC

On Fri, 26 Aug 2022 03:13:18 -0700, Rodrigo Vivi wrote: > > We need to inform PCODE of a desired ring frequencies so PCODE update > the memory frequencies to us. rps->min_freq and rps->max_freq are the > frequencies used in that request. However they were unset when SLPC was > enabled and PCODE nev

Re: [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure

On Thu, Aug 25, 2022 at 06:51:12PM +0530, Badal Nilawar wrote: > From: Dale B Stimson > > The i915 HWMON module will be used to expose voltage, power and energy > values for dGfx. Here we set up i915 hwmon infrastructure including i915 > hwmon registration, basic data structures and functions. >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp: add drm_dp_phy_name() and use it in i915

== Series Details == Series: drm/dp: add drm_dp_phy_name() and use it in i915 URL : https://patchwork.freedesktop.org/series/107266/ State : success == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_107266v1_full Summar

Re: [Intel-gfx] [PATCH v9 1/8] overflow: Move and add few utility macros into overflow

On 25.08.2022 18:47, Kees Cook wrote: On Wed, Aug 24, 2022 at 05:45:07PM +0900, Gwan-gyeong Mun wrote: It moves overflows_type utility macro into overflow header from i915_utils header. The overflows_type can be used to catch the truncaion (overflow) between different data types. And it adds che

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/mtl: Added restriction for plane downscaling

== Series Details == Series: series starting with [1/2] drm/i915/mtl: Added restriction for plane downscaling URL : https://patchwork.freedesktop.org/series/107800/ State : success == Summary == CI Bug Log - changes from CI_DRM_12034 -> Patchwork_107800v1 =

[Intel-gfx] [PATCH v7 0/3] drm/i915/display: stop HPD workers before display driver unregister

Hi Imre, Jani, Ville, Arun, This patchset is replacement of patch "drm/i915/display: disable HPD workers before display driver unregister" [1]. Ive decided to split patch into two parts - fbdev and MST, there are different issues. Ive also dropped shutdown path, as it has slightly different requir

[Intel-gfx] [PATCH v7 1/3] drm/i915/hpd: suspend MST at the end of intel_modeset_driver_remove

i915->hotplug.dig_port_work can be queued from intel_hpd_irq_handler called by IRQ handler or by intel_hpd_trigger_irq called from dp_mst. Since dp_mst is suspended after irq handler uninstall, a cleaner approach is to cancel hpd work after intel_dp_mst_suspend, otherwise we risk use-after-free. I

[Intel-gfx] [PATCH v7 3/3] drm/i915/fbdev: do not create fbdev if HPD is suspended

In case of deferred FB setup core can try to create new framebuffer. Disallow it if hpd_suspended flag is set. Signed-off-by: Andrzej Hajda Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_fbdev.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/displa

[Intel-gfx] [PATCH v7 2/3] drm/i915/fbdev: suspend HPD before fbdev unregistration

HPD event after fbdev unregistration can cause registration of deferred fbdev which will not be unregistered later, causing use-after-free. To avoid it HPD handling should be suspended before fbdev unregistration. It should fix following GPF: [272.634530] general protection fault, probably for non

[Intel-gfx] ✗ Fi.CI.IGT: failure for Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation

== Series Details == Series: Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation URL : https://patchwork.freedesktop.org/series/107318/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_1073

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning

On 23.08.2022 13:24, Matt Roper wrote: > Although register tuning settings are generally implemented via the > workaround infrastructure, it turns out that the DRAW_WATERMARK register > is not properly saved/restored by hardware around power events (i.e., > RC6 entry) so updates to the value cannot

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: stop HPD workers before display driver unregister (rev15)

== Series Details == Series: drm/i915/display: stop HPD workers before display driver unregister (rev15) URL : https://patchwork.freedesktop.org/series/105557/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: stop HPD workers before display driver unregister (rev15)

== Series Details == Series: drm/i915/display: stop HPD workers before display driver unregister (rev15) URL : https://patchwork.freedesktop.org/series/105557/ State : success == Summary == CI Bug Log - changes from CI_DRM_12034 -> Patchwork_105557v15 =

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for Drop version numbers from firmware files (rev3)

On 8/25/2022 20:49, Patchwork wrote: Project List - Patchwork *Patch Details* *Series:* Drop version numbers from firmware files (rev3) *URL:* https://patchwork.freedesktop.org/series/107340/ *State:*success *Details:* https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v3/in

Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness

On Wed, Aug 24, 2022 at 06:17:19PM -0700, Dixit, Ashutosh wrote: On Fri, 05 Aug 2022 08:18:48 -0700, Umesh Nerlige Ramappa wrote: On Fri, Aug 05, 2022 at 10:45:30AM +0100, Tvrtko Ursulin wrote: > > On 05/08/2022 00:21, Umesh Nerlige Ramappa wrote: >> -static inline struct intel_guc *ce_to_guc(s

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning

On Thu, Aug 25, 2022 at 02:45:05AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning > URL : https://patchwork.freedesktop.org/series/107638/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_12

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Remove log size module parameters

On Fri, Aug 26, 2022 at 12:23:43PM +0300, Joonas Lahtinen wrote: > Remove the module parameters for configuring GuC log size. > > We should instead rely on tuning the defaults to be usable for > reporting bugs. > > v2: > - Use correct 1M unit > > Fixes: 8ad0152afb1b ("drm/i915/guc: Make GuC log

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/uc: Support for version reduced and multiple firmware files

On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote: From: John Harrison There was a misunderstanding in how firmware file compatibility should be managed within i915. This has been clarified as: i915 must support all existing firmware releases forever new minor firmware releases sho

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/uc: Support for version reduced and multiple firmware files

On 8/26/2022 09:35, Ceraolo Spurio, Daniele wrote: On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote: From: John Harrison There was a misunderstanding in how firmware file compatibility should be managed within i915. This has been clarified as:    i915 must support all existing firmware re

Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness

On Thu, Aug 25, 2022 at 06:44:50PM -0700, Dixit, Ashutosh wrote: On Thu, 04 Aug 2022 16:21:25 -0700, Umesh Nerlige Ramappa wrote: Hi Umesh, I am fairly new to this code so some questions will be below will be newbie questions, thanks for bearing with me. diff --git a/drivers/gpu/drm/i915/gt/in

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: HuC loading for DG2 (rev2)

== Series Details == Series: drm/i915: HuC loading for DG2 (rev2) URL : https://patchwork.freedesktop.org/series/107477/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12022_full -> Patchwork_107477v2_full Summary ---

Re: [Intel-gfx] [PATCH 1/1] drm/i915/dgfx: Release mmap on rpm suspend

On 25/08/2022 11:54, Anshuman Gupta wrote: Release all mmap mapping for all lmem objects which are associated with userfault such that, while pcie function in D3hot, any access to memory mappings will raise a userfault. Runtime resume the dgpu(when gem object lies in lmem). This will transition

[Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC

We need to inform PCODE of a desired ring frequencies so PCODE update the memory frequencies to us. rps->min_freq and rps->max_freq are the frequencies used in that request. However they were unset when SLPC was enabled and PCODE never updated the memory freq. v2 (as Suggested by Ashutosh): if SLP

[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable Pipewriteback (rev2)

== Series Details == Series: Enable Pipewriteback (rev2) URL : https://patchwork.freedesktop.org/series/107440/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12022_full -> Patchwork_107440v2_full Summary --- **FAILUR

[Intel-gfx] [CI] PR for versionless GuC and HuC files

The following changes since commit 8413c63c7a539a912be8851ce941eea32dcd1786: Merge branch 'lenovo-thinkpad-x13s' of https://github.com/mrhpearson/linux-firmware (2022-08-15 09:02:17 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_huc_nover

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/kms: Stop registering multiple /sys/class/backlight devs for a single display

== Series Details == Series: drm/kms: Stop registering multiple /sys/class/backlight devs for a single display URL : https://patchwork.freedesktop.org/series/107674/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12022_full -> Patchwork_107674v1_full ==

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev5)

== Series Details == Series: drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev5) URL : https://patchwork.freedesktop.org/series/107766/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107766v5

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add display sub-struct to drm_i915_private (rev2)

== Series Details == Series: drm/i915: add display sub-struct to drm_i915_private (rev2) URL : https://patchwork.freedesktop.org/series/107170/ State : success == Summary == CI Bug Log - changes from CI_DRM_12022_full -> Patchwork_107170v2_full =

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/uc: Support for version reduced and multiple firmware files

On 8/26/2022 9:40 AM, John Harrison wrote: On 8/26/2022 09:35, Ceraolo Spurio, Daniele wrote: On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote: From: John Harrison There was a misunderstanding in how firmware file compatibility should be managed within i915. This has been clarified as

Re: [Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC

On Fri, 26 Aug 2022 10:44:34 -0700, Rodrigo Vivi wrote: > > Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled") > Cc: # v5.15+ > Cc: Ashutosh Dixit > Tested-by: Sushma Venkatesh Reddy > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/gt/intel_llc.c | 24 +

[Intel-gfx] [PATCH] Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"

This reverts commit ca6920811aa5428270dd78af0a7a36b10119065a. The intent of Wa_14015141709 was to inform us that userspace can no longer control object-level preemption as it has on past platforms (i.e., by twiddling register bit CS_CHICKEN1[0]). The description of the workaround in the spec wasn

[Intel-gfx] [PATCH] drm/i915/ats-m: Add thread execution tuning setting

On client DG2 platforms, optimal performance is achieved with the hardware's default "age based" thread execution setting. However on ATS-M, switching this to "round robin after dependencies" provides better performance. We'll add a new "tuning" feature flag to the ATS-M device info to enable/dis

[Intel-gfx] [PATCH 00/11] drm/edid: Range descriptor stuff

From: Ville Syrjälä Various improvements (mostly) related to the EDID range descriptor handling. Entire series available here: https://github.com/vsyrjala/linux.git edid_range_descriptor Ville Syrjälä (11): drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets drm/edid: Clarify why we

[Intel-gfx] [PATCH 01/11] drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets

From: Ville Syrjälä EDID 1.4 introduced some extra flags in the range descriptor to support min/max h/vfreq >= 255. Consult them to correctly parse the vfreq limits. Note that some combinations of the flags are documented as "reserved" (as are some other values in the descriptor) but explicitly

[Intel-gfx] [PATCH 02/11] drm/edid: Clarify why we only accept the "range limits only" descriptor

From: Ville Syrjälä The current comment fails to clarify why we only accept the "range limits only" variant of the range descriptor. Reword it to make some actual sense. Cc: Manasi Navare Cc: Nicholas Kazlauskas Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: amd-...@lists.freedeskto

[Intel-gfx] [PATCH 03/11] drm/edid: s/monitor_rage/vrr_range/

From: Ville Syrjälä Rename info->monitor_range to info->vrr_range to actually reflect its usage. Cc: Manasi Navare Cc: Nicholas Kazlauskas Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: amd-...@lists.freedesktop.org Signed-off-by: Ville Syrjälä --- .../gpu/drm/amd/display/amdgpu_d

[Intel-gfx] [PATCH 04/11] drm/edid: Define more flags

From: Ville Syrjälä Replace a bunch of hex constants with proper definitions. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 18 +- include/drm/drm_edid.h | 14 +- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/dr

[Intel-gfx] [PATCH 05/11] drm/edid: Only parse VRR range for continuous frequency displays

From: Ville Syrjälä Since we only use the parsed vrefresh range to determine if VRR should be supported we should only accept continuous frequency displays here. Cc: Manasi Navare Cc: Nicholas Kazlauskas Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: amd-...@lists.freedesktop.org Si

[Intel-gfx] [PATCH 06/11] drm/edid: Extract drm_gtf2_mode()

From: Ville Syrjälä Extract the GTF vs. GTF2 logic into a separate function. We'll have a second user soon. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 47 -- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/d

[Intel-gfx] [PATCH 07/11] drm/edid: Use GTF2 for inferred modes

From: Ville Syrjälä For some resaon we only use the secondary GTF curve for the standard timings. Use it for inferred modes as well. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 35 ++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 08/11] drm/edid: Use the correct formula for standard timings

From: Ville Syrjälä Prefer the timing formula indicated by the range descriptor for generating the non-DMT standard timings. Previously we just used CVT for all EDID 1.4 continuous frequency displays without even checking if the range descriptor indicates otherwise. Now we check the range descri

[Intel-gfx] [PATCH 09/11] drm/edid: Unconfuse preferred timing stuff a bit

From: Ville Syrjälä For EDID 1.4 the first detailed timing is always preferred, for older EDIDs there was a feature flag to indicate the same. While correct, the code setting that up is rather confusing. Restate it in a slightly more straightforward manner. Signed-off-by: Ville Syrjälä --- dri

[Intel-gfx] [PATCH 10/11] drm/edid: Make version checks less convoluted

From: Ville Syrjälä Get rid of the confusing version_greater() stuff and simply compare edid->revision directly everwhere. Half the places already did it this way, and since we actually reject any EDID with edid->version!=1 it's a perfectly sane thing to do. Signed-off-by: Ville Syrjälä --- dr

[Intel-gfx] [PATCH 11/11] drm/i915: Infer vrefresh range for eDP if the EDID omits it

From: Ville Syrjälä A bunch of machines seem to have eDP panels where the EDID indicates continuous frequency support but fails to actually include the range descirptor. This violates the EDID 1.4 spec, but looks like the Windows driver just hacks around this by just assuming that the panel suppo

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"

== Series Details == Series: Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709" URL : https://patchwork.freedesktop.org/series/107818/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"

== Series Details == Series: Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709" URL : https://patchwork.freedesktop.org/series/107818/ State : success == Summary == CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107818v1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/ats-m: Add thread execution tuning setting

== Series Details == Series: drm/i915/ats-m: Add thread execution tuning setting URL : https://patchwork.freedesktop.org/series/107822/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ats-m: Add thread execution tuning setting

== Series Details == Series: drm/i915/ats-m: Add thread execution tuning setting URL : https://patchwork.freedesktop.org/series/107822/ State : success == Summary == CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107822v1 Summary -

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: Range descriptor stuff

== Series Details == Series: drm/edid: Range descriptor stuff URL : https://patchwork.freedesktop.org/series/107824/ State : warning == Summary == Error: dim checkpatch failed f3a0ff9bb39c drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets a3b12a2f939d drm/edid: Clarify why we only acc

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Range descriptor stuff

== Series Details == Series: drm/edid: Range descriptor stuff URL : https://patchwork.freedesktop.org/series/107824/ State : success == Summary == CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107824v1 Summary --- **SUCCESS**

[Intel-gfx] [PATCH] drm/i915/guc: Cancel GuC engine busyness worker synchronously

The worker is canceled in gt_park path, but earlier it was assumed that gt_park path cannot sleep and the cancel is asynchronous. This caused a race with suspend flow where the worker runs after suspend and causes an unclaimed register access warning. Cancel the worker synchronously since the gt_pa

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/uc: Add patch level version number support

On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote: From: John Harrison With the move to un-versioned filenames, it becomes more difficult to know exactly what version of a given firmware is being used. So add the patch level version number to the debugfs output. Also, support matching b

Re: [Intel-gfx] [PATCH v2 15/21] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox

On Thu, Aug 18, 2022 at 04:41:56PM -0700, Radhakrishna Sripada wrote: > From Meteorlake, Latency Level, SAGV bloack time are read from > LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type > and QGV information are also to be read from Mem SS registers. > > v2: > - Simplify MTL

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Cancel GuC engine busyness worker synchronously (rev2)

== Series Details == Series: drm/i915/guc: Cancel GuC engine busyness worker synchronously (rev2) URL : https://patchwork.freedesktop.org/series/106738/ State : success == Summary == CI Bug Log - changes from CI_DRM_12035 -> Patchwork_106738v2 ==

[Intel-gfx] [PATCH] drm/i915/guc: Cancel GuC engine busyness worker synchronously

The worker is canceled in gt_park path, but earlier it was assumed that gt_park path cannot sleep and the cancel is asynchronous. This caused a race with suspend flow where the worker runs after suspend and causes an unclaimed register access warning. Cancel the worker synchronously since the gt_pa

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/uc: Add patch level version number support

On 8/26/2022 16:54, Ceraolo Spurio, Daniele wrote: On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote: From: John Harrison With the move to un-versioned filenames, it becomes more difficult to know exactly what version of a given firmware is being used. So add the patch level version number

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Cancel GuC engine busyness worker synchronously (rev3)

== Series Details == Series: drm/i915/guc: Cancel GuC engine busyness worker synchronously (rev3) URL : https://patchwork.freedesktop.org/series/106738/ State : success == Summary == CI Bug Log - changes from CI_DRM_12035 -> Patchwork_106738v3 ==

[Intel-gfx] [PATCH v3 0/3] Drop version numbers from firmware files

From: John Harrison Upstream direction is to include the bare minimum of version numbers in firmware files and to replace them in the repo rather than accumulating them. For HuC, that means going completely versionless. For GuC, the major version needs to be kept as that indicates a break in back

[Intel-gfx] [PATCH v3 3/3] drm/i915/uc: Enable version reduced firmware files for newest platforms

From: John Harrison Going forwards, the intention is for GuC firmware files to be named for their major version only and HuC firmware files to have no version number in the name at all. This patch adds those entries for DG1/2 and ADL-P/S. Signed-off-by: John Harrison --- drivers/gpu/drm/i915/g

[Intel-gfx] [PATCH v3 2/3] drm/i915/uc: Add patch level version number support

From: John Harrison With the move to un-versioned filenames, it becomes more difficult to know exactly what version of a given firmware is being used. So add the patch level version number to the debugfs output. Also, support matching by patch level when selecting code paths for firmware compati

[Intel-gfx] [PATCH v3 1/3] drm/i915/uc: Support for version reduced and multiple firmware files

From: John Harrison There was a misunderstanding in how firmware file compatibility should be managed within i915. This has been clarified as: i915 must support all existing firmware releases forever new minor firmware releases should replace prior versions only backwards compatibility brea

Re: [Intel-gfx] [PATCH][next] drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat"

On 8/26/2022 01:10, Colin Ian King wrote: There is a spelling mistake in a drm_err message. Fix it. Signed-off-by: Colin Ian King Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers

Re: [Intel-gfx] [PATCH 01/11] drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets

On Sat, Aug 27, 2022 at 12:34:51AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > EDID 1.4 introduced some extra flags in the range > descriptor to support min/max h/vfreq >= 255. Consult them > to correctly parse the vfreq limits. > > Note that some combinations of the flags are document

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