From: Ville Syrjälä
Name all the ICL_PCODE_SAGV_DE_MEM_SS_CONFIG request/response
bits in a manner that we can actually understand what they're
doing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 18 +
From: Ville Syrjälä
Don't just mask off all the PSF GV points when SAGV gets disabled.
This should in fact cause the Pcode to reject the request since
at least one PSF point must remain enabled at all times.
Cc: sta...@vger.kernel.org
Cc: Stanislav Lisovskiy
Fixes: 192fbfb76744 ("drm/i915: Impl
From: Ville Syrjälä
If the mailbox returns an exceesively large SAGV block time let's just
reject it. This avoids having to worry about overflows when we add the
SAGV block time to the wm0 latency.
We shall put the limit arbitrarily at U16_MAX. >65msec latency
doesn't really make sense to me in
On Wed, 2022-03-09 at 13:51 +, Hogander, Jouni wrote:
> Hello Jose,
>
> See my question/comment below.
>
> On Tue, 2022-03-08 at 07:41 -0800, José Roberto de Souza wrote:
> > If a error happens and sink_not_reliable is set, PSR should be
> > disabled
> > for good but that is not happening.
>
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev5)
URL : https://patchwork.freedesktop.org/series/100899/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
If kernel is built with hung task detection enabled and
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT set to less than 60 seconds,
snd_hdac_i915_init() will trigger the hung task timeout in case i915 is
not available and taint the kernel.
Use wait_for_completion_killable_timeout() for the wait to
avoid this pr
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/101123/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
14d91959f9bf drm/mm: Add an iterator to optimally walk over
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/101123/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't
On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Don't just mask off all the PSF GV points when SAGV gets disabled.
> This should in fact cause the Pcode to reject the request since
> at least one PSF point must remain enabled at all times.
Good point, how
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev5)
URL : https://patchwork.freedesktop.org/series/100899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11346 -> Patchwork_22522
Summary
---
**FAILU
On Wed, Mar 09, 2022 at 08:59:59PM +0200, Lisovskiy, Stanislav wrote:
> On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Don't just mask off all the PSF GV points when SAGV gets disabled.
> > This should in fact cause the Pcode to reject the request s
On Wed, Mar 09, 2022 at 06:49:41PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> For modern platforms the spec explicitly states that a
> SAGV block time of zero means that SAGV is not supported.
> Let's extend that to all platforms. Supposedly there should
> be no systems where this isn'
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/101123/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11346 -> Patchwork_22523
==
== Series Details ==
Series: drm/i915: SAGV block time fixes (rev2)
URL : https://patchwork.freedesktop.org/series/101171/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, Mar 09, 2022 at 09:08:12PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 09, 2022 at 08:59:59PM +0200, Lisovskiy, Stanislav wrote:
> > On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Don't just mask off all the PSF GV points when SAGV gets
== Series Details ==
Series: ALSA: hda/i915 - avoid hung task timeout in i915 wait (rev3)
URL : https://patchwork.freedesktop.org/series/101156/
State : failure
== Summary ==
Applying: ALSA: hda/i915 - avoid hung task timeout in i915 wait
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: drm/i915: SAGV block time fixes (rev2)
URL : https://patchwork.freedesktop.org/series/101171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11346 -> Patchwork_22524
Summary
---
**SUCCESS*
On Wed, Mar 09, 2022 at 09:34:58PM +0200, Lisovskiy, Stanislav wrote:
> On Wed, Mar 09, 2022 at 09:08:12PM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 09, 2022 at 08:59:59PM +0200, Lisovskiy, Stanislav wrote:
> > > On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote:
> > > > From: Ville S
On Wed, Mar 09, 2022 at 09:29:58PM +0200, Lisovskiy, Stanislav wrote:
> On Wed, Mar 09, 2022 at 06:49:41PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > For modern platforms the spec explicitly states that a
> > SAGV block time of zero means that SAGV is not supported.
> > Let's ext
On 3/8/2022 01:43, Tvrtko Ursulin wrote:
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst
On 3/8/2022 01:41, Tvrtko Ursulin wrote:
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
It is not totally unbound as the heartbeat wi
From: Ville Syrjälä
Unify vlv/chv with earlier platforms so that the sturct dpll::dot
represents the /5 clock frequency (ie. DP symbol rate or HDMI
TMDS rate) rather than the *5 fast clock (/2 of the bitrate).
Makes life a little less confusing to get the same number back
in .dot which we fed int
== Series Details ==
Series: drm/i915/regs: move GEN12_SFC_DONE_MAX where it belongs
URL : https://patchwork.freedesktop.org/series/101197/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11341_full -> Patchwork_22521_full
Su
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev6)
URL : https://patchwork.freedesktop.org/series/100899/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev6)
URL : https://patchwork.freedesktop.org/series/100899/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11346 -> Patchwork_22526
Summary
---
**SUCCE
On 3/8/2022 8:36 AM, Alexander Usyskin wrote:
From: Tomas Winkler
GSC is a graphics system controller, it provides
a chassis controller for graphics discrete cards.
There are two MEI interfaces in GSC: HECI1 and HECI2.
Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000.
G
On Wed, Mar 09, 2022 at 11:09:13AM +0200, Jani Nikula wrote:
> Commit ce2fce2513c5 ("drm/i915: Only include i915_reg.h from .c files")
> moved GEN12_SFC_DONE_MAX from i915_regs.h to i915_reg_defs.h. Arguably
> it belongs next to the GEN12_SFC_DONE() definition, as it describes the
> number of GEN12
On Thu, Mar 03, 2022 at 03:32:22PM -0800, Manasi Navare wrote:
> With some VRR panels, user can turn VRR ON/OFF on the fly from the panel
> settings.
> When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore
> MSA bit
> in the DPCD. Currently the driver parses that onevery HPD
On Sat, Feb 26, 2022 at 01:55:30AM -0800, Alan Previn wrote:
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
lgtm,
Reviewed-by: Umesh Nerlige Ramappa
Umesh
---
.../gpu/drm/i915/
On 3/8/2022 8:36 AM, Alexander Usyskin wrote:
From: Tomas Winkler
GSC is a graphics system controller, based on CSE, it provides
a chassis controller for graphics discrete cards, as well as it
supports media protection on selected devices.
mei_gsc binds to a auxiliary devices exposed by Inte
On Thu, Mar 10, 2022 at 01:43:57AM +0200, Ville Syrjälä wrote:
> On Thu, Mar 03, 2022 at 03:32:22PM -0800, Manasi Navare wrote:
> > With some VRR panels, user can turn VRR ON/OFF on the fly from the panel
> > settings.
> > When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore
On Fri, Mar 04, 2022 at 05:10:33PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 03, 2022 at 02:41:23PM -0800, Navare, Manasi wrote:
> > On Wed, Feb 23, 2022 at 03:13:15PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > When using bigjoiner it's useful to know the offset of each
> >
On 3/8/2022 8:36 AM, Alexander Usyskin wrote:
Setup char device in spite of firmware handshake failure.
In order to provide host access to the firmware status registers and other
information required for the manufacturing process.
IMO this patch should be moved to after the patch that adds t
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.
Cc: Ashutosh Dixit
Cc: Matt Roper
UMD (m
From: Ville Syrjälä
Only seamless DRRS needs the frontbuffer tracking, so check for that.
Also use != consistently instead of randomly picing < as the comparison
operator.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_drrs.c | 4 ++--
1 file changed, 2 insertions(+), 2 de
From: Ville Syrjälä
Fix/clean up the DRRS code sufficiently that I feel
comfortable enabling it on all ilk+ CPU eDP ports.
PCH ports still need a bit of work.
The other thing I slapped on top is the beginnings of
static DRRS support (ie. actually changing the refresh
rate based on what the user
From: Ville Syrjälä
Pass the fixed_mode as const to intel_drrs_init() since it's
not supposed to mutate the mode.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_drrs.c | 2 +-
drivers/gpu/drm/i915/display/intel_drrs.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-
From: Ville Syrjälä
Use the standard [CONNECTOR:%d:%s] format in the DRRS debugs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_drrs.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c
b/driv
From: Ville Syrjälä
VBT hsa a field for the MSA timing delay, which supposedly
should be used with DRRS. Extract the data from the VBT.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
2 files changed, 6 in
From: Ville Syrjälä
Grab the DRRS MSA timing delay value from the VBT
and program things accordingly. Only ilk/snb/ivb have
this so presumably on hsw+ we don't need it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++--
drivers/gpu/drm/i915/displa
From: Ville Syrjälä
Make the drrs type enum less convoluted.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c| 10 +-
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_drrs.c| 10 +-
From: Ville Syrjälä
Make the DRRS refresh rate enum less magical.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_debugfs.c | 18 ++--
drivers/gpu/drm/i915/display/intel_drrs.c | 44 +--
drivers/gpu/drm/i915/i915_drv.h | 14 ++
3 f
From: Ville Syrjälä
Rename the PIPECONF refresh rate select bits to be
less cryptic. Also nothing eDP specific about these as they
also select between FP0 vs. FP1 for the DPLL and thus can be
used to change the refresh rate on other output types as well.
Signed-off-by: Ville Syrjälä
---
driver
From: Ville Syrjälä
Get rid of the ugly intel_dp dependency, and one more crtc->config
usage by storing the DRRS state under intel_crtc. intel_drrs_enable()
copies what it needs from the crtc state, after which DRRS can be
blissfully ignorant of anything going on around it.
This also lets multip
From: Ville Syrjälä
Nothing special about ivb+ here, if DRRS works on ivb+ port A
it should work just as well on ilk/snb. So let's enable
that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_drrs.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a
From: Ville Syrjälä
No reason to keep the DRRS enable/disable hidden insider the encoder
hooks. Let's just move them all the way up into platform independent
code so that all platforms get to use them. These are nops when
the state computation doesn't think DRRS is possible.
Signed-off-by: Ville
From: Ville Syrjälä
Let's start supporting static DRRS by trying to match the refresh
rate the user has requested, assuming the panel supports suitable
timings.
For now we stick to just our current two timings:
- fixed_mode: the panel's preferred mode
- downclock_mode: the lowest refresh rate mo
From: Ville Syrjälä
Absract away the details on where we store the fixed/downclock modes,
and also how we select them. Will be useful for static DRRS (aka.
allowing the user to select the refresh rate for the panel).
Only hooked these up into the DP code for now since that's
the only one that ca
== Series Details ==
Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
URL : https://patchwork.freedesktop.org/series/101219/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cd66c422f46c drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
-:106: ERROR:SPACING: space p
== Series Details ==
Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
URL : https://patchwork.freedesktop.org/series/101219/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Sat, Feb 26, 2022 at 01:55:31AM -0800, Alan Previn wrote:
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/
The following changes since commit f011ccb490f952ea35e9ce4d73ca9b7d0d2453c3:
linux-firmware: add firmware for MT7986 (2022-03-04 08:43:26 -0500)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware guc_v70.0.5_dg2
for you to fetch changes up to 850f9be3f587
On 3/8/2022 8:36 AM, Alexander Usyskin wrote:
Add a hook to retrieve the firmware version of the
GSC devices to bus-fixup.
GSC has a different MKHI clients GUIDs but the same message structure
to retrieve the firmware version as MEI so mei_fwver() can be reused.
CC: Ashutosh Dixit
Signed-off
On 3/8/2022 11:47, Teres Alexis, Alan Previn wrote:
On 3/1/2022 1:37 PM, John Harrison wrote:
On 2/25/2022 22:27, Alan Previn wrote:
...
This fixes a kernel page fault can happen when
multiple tests are running concurrently in a loop
and one is producing engine resets and consuming
the i915 err
== Series Details ==
Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
URL : https://patchwork.freedesktop.org/series/101219/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11346 -> Patchwork_22527
Summary
---
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS
URL : https://patchwork.freedesktop.org/series/101222/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d02f80fe9d06 drm/i915: Fix up some DRRS type checks
1d8de7687685 drm/i915: Constify intel_drr
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS
URL : https://patchwork.freedesktop.org/series/101222/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 3/9/2022 5:18 PM, John Harrison wrote:
On 3/8/2022 11:47, Teres Alexis, Alan Previn wrote:
On 3/1/2022 1:37 PM, John Harrison wrote:
On 2/25/2022 22:27, Alan Previn wrote:
...
This fixes a kernel page fault can happen when
multiple tests are running concurrently in a loop
and one is produ
On Sat, Feb 26, 2022 at 01:55:32AM -0800, Alan Previn wrote:
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS
URL : https://patchwork.freedesktop.org/series/101222/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11346 -> Patchwork_22528
Summary
-
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/101123/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11346_full -> Patchwork_22523_full
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.
v2: fix white space errors
Cc: Ashutosh D
On Sat, Feb 26, 2022 at 01:55:29AM -0800, Alan Previn wrote:
> Update GuC ADS size allocation to include space for
> the lists of error state capture register descriptors.
>
> Also, populate the lists of registers we want GuC to report back to
> Host on engine reset events. This list should includ
== Series Details ==
Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2)
URL : https://patchwork.freedesktop.org/series/101219/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: SAGV block time fixes (rev2)
URL : https://patchwork.freedesktop.org/series/101171/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11346_full -> Patchwork_22524_full
Summary
---
== Series Details ==
Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev2)
URL : https://patchwork.freedesktop.org/series/101219/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11347 -> Patchwork_22529
Summary
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev6)
URL : https://patchwork.freedesktop.org/series/100899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11346_full -> Patchwork_22526_full
Summary
---
On Thu, Mar 03, 2022 at 09:12:04PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We should round up when doing bandwidth calculations to make sure
> our estimates don't fall short of the actual number.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers
On Thu, Mar 03, 2022 at 09:12:05PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The current code also forgets to call intel_atomic_lock_global_state()
> when other stuff besides the final min_cdlck changes in the state.
> That means we may throw away data which actually has changed, and
Hi Dave & Daniel,
Here's a batch of -next-fixes from drm-intel-next/drm-intel-gt-next.
On GT side just a fix to relax GGTT alignment down 64K from 2M.
Addition of missing "name" attribute for GVT mdev device.
On display side async flip fixes and a static checker fix.
CI results had some display
== Series Details ==
Series: drm/i915/guc: Use iosys_map interface to update lrc_desc
URL : https://patchwork.freedesktop.org/series/101166/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11337_full -> Patchwork_22515_full
S
On 08/03/2022 17:27, Kai Vehmanen wrote:
If kernel is built with hung task detection enabled and
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT set to less than 60 seconds,
snd_hdac_i915_init() will trigger the hung task timeout in case i915 is
not available and taint the kernel.
Split the 60sec wait into a
On Tue, 08 Mar 2022, cgel@gmail.com wrote:
> From: Changcheng Deng
>
> Use min_t() in order to make code cleaner.
>
> Reported-by: Zeal Robot
> Signed-off-by: Changcheng Deng
Thanks, pushed to drm-intel-next.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 5 +
> 1 fil
Hi,
On Wed, 9 Mar 2022, Tvrtko Ursulin wrote:
> > - /* 60s timeout */
>
> Where does this 60s come from and why is the fix to work around
> DEFAULT_HUNG_TASK_TIMEOUT in a hacky way deemed okay? For instance would
> limiting the wait here to whatever the kconfig is set to be an
On Wed, 09 Mar 2022 09:36:54 +0100,
Tvrtko Ursulin wrote:
>
>
> On 08/03/2022 17:27, Kai Vehmanen wrote:
> > If kernel is built with hung task detection enabled and
> > CONFIG_DEFAULT_HUNG_TASK_TIMEOUT set to less than 60 seconds,
> > snd_hdac_i915_init() will trigger the hung task timeout in cas
On 09/03/2022 08:39, Kai Vehmanen wrote:
Hi,
On Wed, 9 Mar 2022, Tvrtko Ursulin wrote:
- /* 60s timeout */
Where does this 60s come from and why is the fix to work around
DEFAULT_HUNG_TASK_TIMEOUT in a hacky way deemed okay? For instance would
limiting the wait here t
Commit ce2fce2513c5 ("drm/i915: Only include i915_reg.h from .c files")
moved GEN12_SFC_DONE_MAX from i915_regs.h to i915_reg_defs.h. Arguably
it belongs next to the GEN12_SFC_DONE() definition, as it describes the
number of GEN12_SFC_DONE instances.
The unfortunate downside is obviously having to
On Tue, 08 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for bxt/glk PLL registers.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 +-
> drivers/gpu/drm/i915/gvt/handlers.c
On Wed, 09 Mar 2022 10:02:13 +0100,
Tvrtko Ursulin wrote:
>
>
> On 09/03/2022 08:39, Kai Vehmanen wrote:
> > Hi,
> >
> > On Wed, 9 Mar 2022, Tvrtko Ursulin wrote:
> >
> >>> - /* 60s timeout */
> >>
> >> Where does this 60s come from and why is the fix to work around
> >> DEFAULT_H
On Tue, 08 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of the pointless m2 int vs. frac split in bxt_clk_div
> and just store the whole divider as one.
>
> v2: Document the full divider as a proper decimal number
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
>
On Tue, 08 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Set the bxt/glk DPLL min dotclock to 25MHz (HDMI minimum)
> and the max to 594 MHz (HDMI max). The supported DP frequencies
> (162MHz-540MHz) fit within the same range.
>
> Signed-off-by: Ville Syrjälä
Acked-by: Jani Nikula
>
On Tue, 08 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> struct dp_link_dpll is a pointless wrapper around struct dpll.
> Just store the desired link rate into struct dpll::dot and
> we're done.
>
> v2: Document the full divider as a proper decimal number on chv
> Nuke bogus eDP 1.
On Tue, 08 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use chv_calc_dpll_params() to calculate the BXT DP DPLL VCO
> frequency.
>
> We need to add the m1 divider into bxt_dp_clk_val[] for this to work.
>
> v2: Make the WARN_ON() sensible
>
> Signed-off-by: Ville Syrjälä
I admit I d
On 09/03/2022 09:23, Takashi Iwai wrote:
On Wed, 09 Mar 2022 10:02:13 +0100,
Tvrtko Ursulin wrote:
On 09/03/2022 08:39, Kai Vehmanen wrote:
Hi,
On Wed, 9 Mar 2022, Tvrtko Ursulin wrote:
- /* 60s timeout */
Where does this 60s come from and why is the fix to work a
On Mon, 07 Mar 2022, Colin Ian King wrote:
> Don't populate the read-only array div1_vals on the stack but
> instead make it static const. Also makes the object code a little
> smaller.
Thanks, but this was just fixed in commit fe70b262e781 ("drm/i915: Move
a bunch of stuff into rodata from the s
On Tue, 08 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Remove the comment specifying the exact formulat for calculating
> the DPLL frequency from the *_find_best_dpll() functions. Each
> platform variant has its own way to calculate these and we have
> the code already to do that. Th
On Tue, 08 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Unify vlv/chv with earlier platforms so that the sturct dpll::dot
> represents the /5 clock frequency (ie. DP symbol rate or HDMI
> TMDS rate) rather than the *5 fast clock (/2 of the bitrate).
> Makes life a little less confusin
On Wed, 09 Mar 2022 10:48:49 +0100,
Tvrtko Ursulin wrote:
>
>
> On 09/03/2022 09:23, Takashi Iwai wrote:
> > On Wed, 09 Mar 2022 10:02:13 +0100,
> > Tvrtko Ursulin wrote:
> >>
> >>
> >> On 09/03/2022 08:39, Kai Vehmanen wrote:
> >>> Hi,
> >>>
> >>> On Wed, 9 Mar 2022, Tvrtko Ursulin wrote:
> >>>
== Series Details ==
Series: drm/i915: check before removing mm notifier
URL : https://patchwork.freedesktop.org/series/101170/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11338_full -> Patchwork_22516_full
Summary
--
On Tue, 2022-03-08 at 19:32 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> GLK doesn't support SAGV, so with CNL gone there is no
> use for having a DISPLAY_VER==10 SAGV block time in the code.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Vinod Govindapillai
> ---
> drivers/gpu/drm
On Tue, 2022-03-08 at 19:32 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I'd like to see the SAGV block time we got from the mailbox
> in the logs regardless of whether other factors prevent the
> use of SAGV.
>
> So let's adjust the code to always query the SAGV block time,
> log it, a
== Series Details ==
Series: drm/i915: SAGV block time fixes
URL : https://patchwork.freedesktop.org/series/101171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11338_full -> Patchwork_22517_full
Summary
---
**SUCCE
Hi,
can we have ack? or we need to do anything further to get r-o-b.
Thanks,
Mastan
-Original Message-
From: Katragadda, MastanX
Sent: 09 March 2022 07:16
To: Auld, Matthew ; Tvrtko Ursulin
; intel-gfx@lists.freedesktop.org
Cc: Surendrakumar Upadhyay, TejaskumarX
Subject: RE: [Intel-
On Tue, 2022-03-08 at 19:32 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> For modern platforms the spec explicitly states that a
> SAGV block time of zero means that SAGV is not supported.
> Let's extend that to all platforms. Supposedly there should
> be no systems where this isn't true,
On 09/03/2022 11:19, Katragadda, MastanX wrote:
Hi,
can we have ack? or we need to do anything further to get r-o-b.
There was just the potential strangeness around len <= 0, and exactly
how we are meant to handle that, but if you are confident that is
already covered in a sane way, then fee
== Series Details ==
Series: drm/i915/regs: move GEN12_SFC_DONE_MAX where it belongs
URL : https://patchwork.freedesktop.org/series/101197/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, Mar 09, 2022 at 10:41:28AM +, Govindapillai, Vinod wrote:
> On Tue, 2022-03-08 at 19:32 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > I'd like to see the SAGV block time we got from the mailbox
> > in the logs regardless of whether other factors prevent the
> > use of SA
On Wed, Mar 09, 2022 at 11:29:37AM +, Govindapillai, Vinod wrote:
> On Tue, 2022-03-08 at 19:32 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > For modern platforms the spec explicitly states that a
> > SAGV block time of zero means that SAGV is not supported.
> > Let's extend tha
== Series Details ==
Series: drm/i915/regs: move GEN12_SFC_DONE_MAX where it belongs
URL : https://patchwork.freedesktop.org/series/101197/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11341 -> Patchwork_22521
Summary
Hi,
On Wed, 9 Mar 2022, Takashi Iwai wrote:
>> Takashi Iwai wrote:
>>> The question is how often this problem hits. Basically it's a very
>>> corner case, and I even think we may leave as is; that's a matter of
>>> configuration, and lowering such a bar should expect some
>>> side-effect. OTOH,
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