Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/dg2: Introduce CD clock squashing table

Please ignore this. These CD clock squashing patches needs to be sent as a series. From: Patchwork Sent: Wednesday, November 17, 2021 10:59 PM To: Kahola, Mika Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/dg2: Introduce CD clock squashing table Patch

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display/dg2: Read CD clock from squasher table

Please ignore this. These CD clock squashing patches needs to be sent as a series. > -Original Message- > From: Patchwork > Sent: Wednesday, November 17, 2021 11:28 PM > To: Kahola, Mika > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ Fi.CI.BUILD: failure for drm/i915/display/dg2: Re

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display/dg2: Set CD clock squashing registers

Please ignore this. These CD clock squashing patches needs to be sent as a series. > -Original Message- > From: Patchwork > Sent: Thursday, November 18, 2021 12:06 AM > To: Kahola, Mika > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ Fi.CI.BUILD: failure for drm/i915/display/dg2: Set

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/dg2: Sanitize CD clock

Please ignore this. These CD clock squashing patches needs to be sent as a series. From: Patchwork Sent: Thursday, November 18, 2021 12:08 AM To: Kahola, Mika Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/dg2: Sanitize CD clock Patch Details Series: d

[Intel-gfx] [PATCH i-g-t] tests/core_hotunplug: Show device PCI bus address on errors

Strange -ENODEV responses from the kernel to i915 driver rebind attempts have been sporadically observed. After successfully unbinding the driver from a device by writing a string representing its PCI bus address to /sys/bus/pci/driver/i915/unbind, the test then fails while writing the same device

[Intel-gfx] [PATCH 0/4] drm/i915/display/dg2: Add CD clock squashing

Add support for CD clock squashing feature. Signed-off-by: Mika Kahola Signed-off-by: Ville Syrjälä Mika Kahola (4): drm/i915/display/dg2: Introduce CD clock squashing table drm/i915/display/dg2: Read CD clock from squasher table drm/i915/display/dg2: Sanitize CD clock drm/i915/display/

[Intel-gfx] [PATCH 1/4] drm/i915/display/dg2: Introduce CD clock squashing table

For CD clock squashing method, we need to define corresponding CD clock table for reference clocks, dividers and ratios for all CD clock options. BSpec: 54034 v2: Add CD squashing waveforms as part of CD clock table (Ville) v3: Waveform is 16 bits wide (Ville) [v4: vsyrjala: Nuke the non-squashe

[Intel-gfx] [PATCH 3/4] drm/i915/display/dg2: Sanitize CD clock

In case of CD clock squashing the divider is always 1. We don't need to calculate the divider in use so let's skip that for DG2. v2: Drop unnecessary local variable (Ville) v3: Avoid if-else structure (Ville) [v4: vsyrjala: Fix cd2x divider calculation (Uma), Introduce has_cdclk_squ

[Intel-gfx] [PATCH 4/4] drm/i915/display/dg2: Set CD clock squashing registers

Set CD clock squashing registers based on selected CD clock. v2: use slk_cdclk_decimal() to compute decimal values instead of a specific table (Ville) Set waveform based on CD clock table (Ville) Drop unnecessary local variable (Ville) v3: Correct function naming (Ville) Correct if

[Intel-gfx] [PATCH 2/4] drm/i915/display/dg2: Read CD clock from squasher table

To calculate CD clock with squasher unit, we set CD clock ratio to fixed value of 34. The CD clock value is read from CD clock squasher table. BSpec: 54034 v2: Read ratio from register (Ville) Drop unnecessary local variable (Ville) Get CD clock from the given table v3: Calculate CD cloc

[Intel-gfx] [PULL] drm-misc-next

Hi Dave and Daniel, here's the first PR for drm-misc-next for what will become Linux 5.17. The dma-buf interface got a new iterator-based interface with updates to several drivers. This change might have an effect on other subsystems as well. During development, we had linker errors as dma-buf s

[Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2

Bug in the register unit which results in WM1 register used when only WM0 is enabled on cursor. Software workaround is when only WM0 enabled on cursor, copy contents of CUR_WM_0[30:0] (exclude the enable bit) into CUR_WM_1[30:0]. v2: - s/dev_priv/i915/ (Ville Syrjälä) - Removed unneeded brac

Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: move the pre_pin earlier

On 18/11/2021 06:57, Thomas Hellström wrote: On Wed, 2021-11-17 at 19:49 +0100, Thomas Hellström wrote: On 11/17/21 15:20, Matthew Auld wrote: In intel_context_do_pin_ww, when calling into the pre_pin hook(which is passed the ww context) it could in theory return -EDEADLK(which is very likely

Re: [Intel-gfx] [PATCH 3/4] drm/i915/display/dg2: Sanitize CD clock

On Thu, 18 Nov 2021, Mika Kahola wrote: > In case of CD clock squashing the divider is always 1. We don't > need to calculate the divider in use so let's skip that for DG2. > > v2: Drop unnecessary local variable (Ville) > v3: Avoid if-else structure (Ville) > [v4: vsyrjala: Fix cd2x divider calcu

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915: move the pre_pin earlier

On 17/11/2021 19:53, Patchwork wrote: *Patch Details* *Series:* series starting with [v2,1/6] drm/i915: move the pre_pin earlier *URL:* https://patchwork.freedesktop.org/series/97026/ *State:*failure *Details:* https://intel-gfx-c

[Intel-gfx] [PATCH] drm/i915: Skip remap_io() calls for non-x86 platforms

From: Siva Mullati Only hw that supports mappable aperture would hit this path vm_fault_gtt/vm_fault_tmm, So we never hit these functions remap_io_mapping() and remap_io_sg in discrete, So skip this code for non-x86 architectures. Signed-off-by: Siva Mullati --- drivers/gpu/drm/i915/Makefile

Re: [Intel-gfx] [PATCH 3/4] drm/i915/display/dg2: Sanitize CD clock

> -Original Message- > From: Jani Nikula > Sent: Thursday, November 18, 2021 12:12 PM > To: Kahola, Mika ; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/display/dg2: Sanitize CD clock > > On Thu, 18 Nov 2021, Mika Kahola wrote: > > In case of CD clock sq

Re: [Intel-gfx] [PATCH] drm/i915: Skip remap_io() calls for non-x86 platforms

On Thu, 18 Nov 2021, Mullati Siva wrote: > From: Siva Mullati > > Only hw that supports mappable aperture would hit this path > vm_fault_gtt/vm_fault_tmm, So we never hit these functions > remap_io_mapping() and remap_io_sg in discrete, So skip this > code for non-x86 architectures. Please enabl

Re: [Intel-gfx] [PATCH 3/4] drm/i915/display/dg2: Sanitize CD clock

On Thu, 18 Nov 2021, "Kahola, Mika" wrote: >> -Original Message- >> From: Jani Nikula >> Sent: Thursday, November 18, 2021 12:12 PM >> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org >> Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/display/dg2: Sanitize CD clock >> >> On Thu, 18 Nov 2

Re: [Intel-gfx] [PATCH] drm/i915/vlv_dsi: Double pixelclock on read-back for dual-link panels

Hi, On 10/25/21 10:17, Jani Nikula wrote: > On Sun, 24 Oct 2021, Hans de Goede wrote: >> In intel_dsi_get_config() double the pclk returned by foo_dsi_get_pclk() >> for dual-link panels. This fixes the following WARN triggering: >> >> i915 :00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in

[Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support

TileF(Tile4 in bspec) format is 4K tile organized into 64B subtiles with same basic shape as for legacy TileY which will be supported by Display13. v2: - Fixed wrong case condition(Jani Nikula) - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) v3: - s/I915_TILING_F/TILING_4/g - s/I9

[Intel-gfx] [PATCH v4 1/6] drm/i915: Add support for moving fence waiting

From: Maarten Lankhorst For now, we will only allow async migration when TTM is used, so the paths we care about are related to TTM. The mmap path is handled by having the fence in ttm_bo->moving, when pinning, the binding only becomes available after the moving fence is signaled, and pinning a

[Intel-gfx] [PATCH v4 0/6] drm/i915/ttm: Async migration

This patch series deals with async migration and async vram management. It still leaves an important part out, which is async unbinding which will reduce latency further, at least when trying to migrate already active objects. Patches 1/6 deals with accessing and waiting for the TTM moving fence f

[Intel-gfx] [PATCH v4 2/6] drm/i915/ttm: Move the i915_gem_obj_copy_ttm() function

Move the i915_gem_obj_copy_ttm() function to i915_gem_ttm_move.h. This will help keep a number of functions static when introducing async moves. Signed-off-by: Thomas Hellström Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 47 --- drivers/gpu/drm/i915/

[Intel-gfx] [PATCH v4 5/6] drm/i915/ttm: Implement asynchronous TTM moves

Don't wait sync while migrating, but rather make the GPU blit await the dependencies and add a moving fence to the object. This also enables asynchronous VRAM management in that on eviction, rather than waiting for the moving fence to expire before freeing VRAM, it is freed immediately and the fen

[Intel-gfx] [PATCH v4 3/6] drm/i915/ttm: Drop region reference counting

There is an interesting refcounting loop: struct intel_memory_region has a struct ttm_resource_manager, ttm_resource_manager->move may hold a reference to i915_request, i915_request may hold a reference to intel_context, intel_context may hold a reference to drm_i915_gem_object, drm_i915_gem_object

[Intel-gfx] [PATCH v4 6/6] drm/i915/ttm: Update i915_gem_obj_copy_ttm() to be asynchronous

Update the copy function i915_gem_obj_copy_ttm() to be asynchronous for future users and update the only current user to sync the objects as needed after this function. Signed-off-by: Thomas Hellström --- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 40 ++-- drivers/gpu/drm/i91

[Intel-gfx] [PATCH v4 4/6] drm/i915/ttm: Correctly handle waiting for gpu when shrinking

With async migration, the shrinker may end up wanting to release the pages of an object while the migration blit is still running, since the GT migration code doesn't set up VMAs and the shrinker is thus oblivious to the fact that the GPU is still using the pages. Add waiting for gpu in the shrink

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/dg2: Add CD clock squashing

== Series Details == Series: drm/i915/display/dg2: Add CD clock squashing URL : https://patchwork.freedesktop.org/series/97058/ State : warning == Summary == $ dim checkpatch origin/drm-tip 406193c026fe drm/i915/display/dg2: Introduce CD clock squashing table -:9: WARNING:COMMIT_LOG_LONG_LINE:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display/dg2: Add CD clock squashing

== Series Details == Series: drm/i915/display/dg2: Add CD clock squashing URL : https://patchwork.freedesktop.org/series/97058/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dg2: Add CD clock squashing

== Series Details == Series: drm/i915/display/dg2: Add CD clock squashing URL : https://patchwork.freedesktop.org/series/97058/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900 -> Patchwork_21626 Summary --- **SUC

Re: [Intel-gfx] [PATCH v4 1/6] drm/i915: Add support for moving fence waiting

On 18/11/2021 13:02, Thomas Hellström wrote: From: Maarten Lankhorst For now, we will only allow async migration when TTM is used, so the paths we care about are related to TTM. The mmap path is handled by having the fence in ttm_bo->moving, when pinning, the binding only becomes available aft

Re: [Intel-gfx] [PATCH v4 3/6] drm/i915/ttm: Drop region reference counting

On 18/11/2021 13:02, Thomas Hellström wrote: There is an interesting refcounting loop: struct intel_memory_region has a struct ttm_resource_manager, ttm_resource_manager->move may hold a reference to i915_request, i915_request may hold a reference to intel_context, intel_context may hold a refere

Re: [Intel-gfx] [PATCH v4 4/6] drm/i915/ttm: Correctly handle waiting for gpu when shrinking

On 18/11/2021 13:02, Thomas Hellström wrote: With async migration, the shrinker may end up wanting to release the pages of an object while the migration blit is still running, since the GT migration code doesn't set up VMAs and the shrinker is thus oblivious to the fact that the GPU is still usin

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Implement WM0 cursor WA for DG2 (rev2)

== Series Details == Series: drm/i915/dg2: Implement WM0 cursor WA for DG2 (rev2) URL : https://patchwork.freedesktop.org/series/97022/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900 -> Patchwork_21627 Summary ---

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Skip remap_io() calls for non-x86 platforms

== Series Details == Series: drm/i915: Skip remap_io() calls for non-x86 platforms URL : https://patchwork.freedesktop.org/series/97069/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compil

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev4)

== Series Details == Series: drm/i915/dg2: Tile 4 plane format support (rev4) URL : https://patchwork.freedesktop.org/series/95715/ State : warning == Summary == $ dim checkpatch origin/drm-tip 419c0f4c0f6d drm/i915/dg2: Tile 4 plane format support -:28: WARNING:TYPO_SPELLING: 'assocating' may

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Tile 4 plane format support (rev4)

== Series Details == Series: drm/i915/dg2: Tile 4 plane format support (rev4) URL : https://patchwork.freedesktop.org/series/95715/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] [bug report] drm/i915/ttm: add tt shmem backend

Hello Matthew Auld, The patch 7ae034590cea: "drm/i915/ttm: add tt shmem backend" from Oct 18, 2021, leads to the following Smatch static checker warning: drivers/gpu/drm/i915/gem/i915_gem_ttm.c:335 i915_ttm_eviction_valuable() warn: signedness bug returning '(-16)' drivers/gpu/dr

Re: [Intel-gfx] [bug report] drm/i915/ttm: add tt shmem backend

On 18/11/2021 15:01, Dan Carpenter wrote: Hello Matthew Auld, The patch 7ae034590cea: "drm/i915/ttm: add tt shmem backend" from Oct 18, 2021, leads to the following Smatch static checker warning: drivers/gpu/drm/i915/gem/i915_gem_ttm.c:335 i915_ttm_eviction_valuable() warn: sign

Re: [Intel-gfx] [PATCH v10 08/10] dyndbg: add print-to-tracefs, selftest with it - RFC

On Thu, 18 Nov 2021 09:29:27 -0500 Jason Baron wrote: > On 11/16/21 3:46 AM, Pekka Paalanen wrote: > > On Fri, 12 Nov 2021 10:08:41 -0500 > > Jason Baron wrote: > > > >> On 11/12/21 6:49 AM, Vincent Whitchurch wrote: > >>> On Thu, Nov 11, 2021 at 03:02:04PM -0700, Jim Cromie wrote: > >>

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Tile 4 plane format support (rev4)

== Series Details == Series: drm/i915/dg2: Tile 4 plane format support (rev4) URL : https://patchwork.freedesktop.org/series/95715/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900 -> Patchwork_21629 Summary --- *

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/ttm: Async migration (rev5)

== Series Details == Series: drm/i915/ttm: Async migration (rev5) URL : https://patchwork.freedesktop.org/series/96798/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reject 5k on HDR planes for planar fb formats

== Series Details == Series: drm/i915: Reject 5k on HDR planes for planar fb formats URL : https://patchwork.freedesktop.org/series/97053/ State : success == Summary == CI Bug Log - changes from CI_DRM_10897_full -> Patchwork_21625_full Sum

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ttm: Async migration (rev5)

== Series Details == Series: drm/i915/ttm: Async migration (rev5) URL : https://patchwork.freedesktop.org/series/96798/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900 -> Patchwork_21630 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/6] drm/i915: move the pre_pin earlier (rev2)

== Series Details == Series: series starting with [v2,1/6] drm/i915: move the pre_pin earlier (rev2) URL : https://patchwork.freedesktop.org/series/97026/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separa

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915: move the pre_pin earlier

Just filed https://gitlab.freedesktop.org/drm/intel/-/issues/4565. igt@gem_lmem_swapping@.*random.* - skip - No dynamic tests executed. SKIP Rev 2 is already is there, so re-reporting is not required. Lakshmi. -Original Message- From: Auld, Matthew Sent: Thursday, November 18, 2021 2:2

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915: move the pre_pin earlier (rev2)

== Series Details == Series: series starting with [v2,1/6] drm/i915: move the pre_pin earlier (rev2) URL : https://patchwork.freedesktop.org/series/97026/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10900 -> Patchwork_21631 ===

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: drop intel_display.h include from intel_ddi.h (rev4)

== Series Details == Series: series starting with [1/5] drm/i915: drop intel_display.h include from intel_ddi.h (rev4) URL : https://patchwork.freedesktop.org/series/96981/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won'

[Intel-gfx] [PATCH] drm/i915: Don't disable interrupts and pretend a lock as been acquired in __timeline_mark_lock().

This is a revert of commits d67739268cf0e ("drm/i915/gt: Mark up the nested engine-pm timeline lock as irqsafe") 6c69a45445af9 ("drm/i915/gt: Mark context->active_count as protected by timeline->mutex") The existing code leads to a different behaviour depending on whether lockdep is enable

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: drop intel_display.h include from intel_ddi.h (rev4)

== Series Details == Series: series starting with [1/5] drm/i915: drop intel_display.h include from intel_ddi.h (rev4) URL : https://patchwork.freedesktop.org/series/96981/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900 -> Patchwork_21632

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Don't disable interrupts and pretend a lock as been acquired in __timeline_mark_lock().

== Series Details == Series: drm/i915: Don't disable interrupts and pretend a lock as been acquired in __timeline_mark_lock(). URL : https://patchwork.freedesktop.org/series/97082/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0120a13c3885 drm/i915: Don't disable interrupts an

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Don't disable interrupts and pretend a lock as been acquired in __timeline_mark_lock().

== Series Details == Series: drm/i915: Don't disable interrupts and pretend a lock as been acquired in __timeline_mark_lock(). URL : https://patchwork.freedesktop.org/series/97082/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each com

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't disable interrupts and pretend a lock as been acquired in __timeline_mark_lock().

== Series Details == Series: drm/i915: Don't disable interrupts and pretend a lock as been acquired in __timeline_mark_lock(). URL : https://patchwork.freedesktop.org/series/97082/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900 -> Patchwork_21633

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Do vblank evasion correctly if vrr push has already been sent

On Wed, Nov 17, 2021 at 03:09:45PM -0800, Navare, Manasi wrote: > On Wed, Nov 17, 2021 at 11:04:05PM +0200, Ville Syrjälä wrote: > > On Wed, Nov 17, 2021 at 01:10:13PM -0800, Navare, Manasi wrote: > > > On Wed, Nov 17, 2021 at 08:31:02PM +0200, Ville Syrjala wrote: > > > > From: Ville Syrjälä > >

Re: [Intel-gfx] [PATCH V4] drm/i915/gt: Hold RPM wakelock during PXP suspend

On 11/16/2021 10:03 PM, Tejas Upadhyay wrote: selftest --r live shows failure in suspend tests when RPM wakelock is not acquired during suspend. This changes addresses below error : <4> [154.177535] RPM wakelock ref not held during HW access <4> [154.177575] WARNING: CPU: 4 PID: 5772 at drive

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Declare .(de)gamma_lut_tests for icl+

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Thursday, October 14, 2021 11:49 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Declare .(de)gamma_lut_tests for > icl+ > > From: Ville Syrjälä > > All interpolated gam

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Disable DSB usage for now

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Thursday, October 14, 2021 11:49 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Disable DSB usage for now > > From: Ville Syrjälä > > Turns out the DSB has trouble corre

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: RPS tuning for light media playback (rev2)

== Series Details == Series: drm/i915/gt: RPS tuning for light media playback (rev2) URL : https://patchwork.freedesktop.org/series/97043/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers

Re: [Intel-gfx] [PATCH] drm/i915: Skip remap_io() calls for non-x86 platforms

Hi Mullati, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip v5.16-rc1 next-2028] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to

[Intel-gfx] [PATCH v5 0/1] Use i915 macros to check for PTEs

Instead of using _PAGE_RW and _PAGE_PRESENT to check for 0 and 1 bits, this series replaces them with GEN6_PTE_VALID and BYT_PTE_WRITEABLE. We should be using macros defined for i915 to check these bits, instead of macros defined by the mmu. Some arch does not have these macros defined, thus lea

[Intel-gfx] [PATCH v5] drm/i915: Re-use i915 macros for checking PTEs

Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check bits 0 and 1 for PTEs. These macros are defined per architectures, and some architectures do not have these defined (like arm64). This patch replaces these two macros with their i915 equivalent implementation. Signed-of

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: RPS tuning for light media playback (rev2)

== Series Details == Series: drm/i915/gt: RPS tuning for light media playback (rev2) URL : https://patchwork.freedesktop.org/series/97043/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900 -> Patchwork_21634 Summary -

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Re-use i915 macros for checking PTEs

== Series Details == Series: drm/i915: Re-use i915 macros for checking PTEs URL : https://patchwork.freedesktop.org/series/97090/ State : warning == Summary == $ dim checkpatch origin/drm-tip 07d207216906 drm/i915: Re-use i915 macros for checking PTEs -:6: WARNING:COMMIT_LOG_LONG_LINE: Possibl

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave and Daniel, Here goes drm-intel-fixes-2021-11-18: One quick fix for return error handling, one fix for ADL-P display and one revert targeting stable 5.4, for TGL's DSI display clocks Thanks, Rodrigo. The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf: Linux 5

Re: [Intel-gfx] [PATCH] drm/i915/display/dsc: Clamp the max DSC input BPP to connector's max bpp

@Jani , @Ville, can you take a look at this, this was how the original DSC patches clamped the max bpp, but with latest DSC changes looks like this is not obeyed anymore and needs to be fixed. Manasi On Thu, Nov 11, 2021 at 03:09:49PM -0800, Manasi Navare wrote: > Pipe_bpp limits are decided by

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking PTEs

== Series Details == Series: drm/i915: Re-use i915 macros for checking PTEs URL : https://patchwork.freedesktop.org/series/97090/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10901 -> Patchwork_21635 Summary --- **F

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/dg2: Add CD clock squashing

== Series Details == Series: drm/i915/display/dg2: Add CD clock squashing URL : https://patchwork.freedesktop.org/series/97058/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900_full -> Patchwork_21626_full Summary --

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Implement WM0 cursor WA for DG2 (rev2)

== Series Details == Series: drm/i915/dg2: Implement WM0 cursor WA for DG2 (rev2) URL : https://patchwork.freedesktop.org/series/97022/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900_full -> Patchwork_21627_full Summar

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Tile 4 plane format support (rev4)

== Series Details == Series: drm/i915/dg2: Tile 4 plane format support (rev4) URL : https://patchwork.freedesktop.org/series/95715/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10900_full -> Patchwork_21629_full Summary --

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ttm: Async migration (rev5)

== Series Details == Series: drm/i915/ttm: Async migration (rev5) URL : https://patchwork.freedesktop.org/series/96798/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10900_full -> Patchwork_21630_full Summary --- **F

Re: [Intel-gfx] [PATCH] drm/i915: Skip remap_io() calls for non-x86 platforms

Hi Mullati, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip v5.16-rc1 next-2028] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to

[Intel-gfx] [PATCH 1/1] drm/i915/dmc: Update DMC to v2.14 on ADL-P

The release notes mention that DMC v2.14 provides - 1. Fix for Flip queue roll over cases with DC6v 2. Enhancement for residency 3. Workaround for 3Dlut restore issue Signed-off-by: Madhumitha Tolakanahalli Pradeep --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 inse

[Intel-gfx] [PATCH 0/1] Bump DMC version on ADL-P to v2.14

Adding PR for CI to pick the firmware, The following changes since commit f5d519563ac9d2d1f382a817aae5ec5473811ac8: linux-firmware: Update AMD cpu microcode (2021-11-15 12:49:19 -0500) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware adlp_dmc_v2.14 for

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: drop intel_display.h include from intel_ddi.h (rev4)

== Series Details == Series: series starting with [1/5] drm/i915: drop intel_display.h include from intel_ddi.h (rev4) URL : https://patchwork.freedesktop.org/series/96981/ State : success == Summary == CI Bug Log - changes from CI_DRM_10900_full -> Patchwork_21632_full ==

[Intel-gfx] ✓ Fi.CI.BAT: success for Bump DMC version on ADL-P to v2.14

== Series Details == Series: Bump DMC version on ADL-P to v2.14 URL : https://patchwork.freedesktop.org/series/97093/ State : success == Summary == CI Bug Log - changes from CI_DRM_10904 -> Patchwork_21636 Summary --- **SUCCESS**

Re: [Intel-gfx] [bug report] drm/i915/ttm: add tt shmem backend

On Thu, Nov 18, 2021 at 03:15:31PM +, Matthew Auld wrote: > On 18/11/2021 15:01, Dan Carpenter wrote: > > Hello Matthew Auld, > > > > The patch 7ae034590cea: "drm/i915/ttm: add tt shmem backend" from Oct > > 18, 2021, leads to the following Smatch static checker warning: > > > > drivers/g