On Fri, Oct 08, 2021 at 02:56:29PM -0700, Matt Roper wrote:
From: Tvrtko Ursulin
Add some basic plumbing to support more than one dynamically allocated
struct intel_gt. Up to four gts are supported in i915->gts[], with slot
zero shadowing the existing i915->gt to enable source compatibility wi
On 10/15/2021 7:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Consolidate the double pfit call, and reorder things so that
intel_dp_output_format() and intel_dp_compute_link_config() are
back-to-back. They are intimately related, and will need to be
called twice to properly handle the "4:2:
On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote:
From: Paulo Zanoni
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then we read the
usual interrupt registers from the appropriate tile.
Note that this is jus
Hi Lyude,
On Mon, Oct 25, 2021 at 09:30:14PM -0400, Lyude Paul wrote:
> topic/amdgpu-dp2.0-mst-2021-10-25:
> UAPI Changes:
> Nope!
>
> Cross-subsystem Changes:
> drm_dp_update_payload_part1() takes a new argument for specifying what the
> VCPI slot start is
>
> Core Changes:
> Make the DP MST he
On 10/15/2021 7:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
We lack sufficient state tracking to figure out whether
we want the DFP to perform the RGB->YCbCr conversion for us
or not. So currently we are blindly just enabling that all the
time when supported by the DFP. That is nonsense.
On Tue, 2021-10-26 at 15:33 -0700, José Roberto de Souza wrote:
> PSR2 is supported in transcoder A and B on Alderlake-P.
>
> BSpec: 49185
> Cc: Mika Kahola
> Cc: Jouni Hogander
> Signed-off-by: José Roberto de Souza
LGTM
Reviewed-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/int
On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>
> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
> include asm/smp.h here.
>
> Reported-by: kernel test robot
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
Jani, would it make sense to cherry-pick this to -fixes?
On Tue, 26 Oct 2021, Lucas De Marchi wrote:
> On Wed, Oct 13, 2021 at 03:12:55PM +0300, Jani Nikula wrote:
>>On Fri, 08 Oct 2021, Matt Roper wrote:
>>> On a multi-tile platform, each tile has its own registers + GGTT space,
>>> and BAR 0 is extended to cover all of them. Upcoming patches will st
On Tue, 26 Oct 2021 11:36:33 -0400
Harry Wentland wrote:
> On 2021-10-14 15:44, Shankar, Uma wrote:
> >
...
> > +
> > +* Plane CTM
> > + * This is a Property to program the color transformation
> > matrix.
>
> No mode property here? Is there any hardware with
On Wed, 27 Oct 2021, Imre Deak wrote:
> On Tue, Oct 26, 2021 at 08:52:12PM +0300, Jani Nikula wrote:
>> AFAICT there are no intel_plane_caps references anywhere after this, and
>> it no longer looks like an enum, so perhaps it just shouldn't be an enum
>> anymore? Just make them macros?
>
> There
On Tue, 26 Oct 2021 11:02:31 -0400
Harry Wentland wrote:
> On 2021-10-12 17:01, Shankar, Uma wrote:
> >
> >
> >> -Original Message-
> >> From: Pekka Paalanen
> >> Sent: Tuesday, October 12, 2021 5:25 PM
> >> To: Shankar, Uma
> >> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.
On Wed, Oct 27, 2021 at 06:41:25AM +, Kasireddy, Vivek wrote:
> Hi Ville,
>
> >
> > On Mon, Oct 25, 2021 at 11:38:11PM -0700, Vivek Kasireddy wrote:
> > > On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
> > > more framebuffers/scanout buffers results in only one that is
GPU relocs are gone. There should be no need for this workaround anymore.
Remove it.
Signed-off-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuf
On Wed, Oct 27, 2021 at 12:36:17PM +0530, Nautiyal, Ankit K wrote:
>
> On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Consolidate the double pfit call, and reorder things so that
> > intel_dp_output_format() and intel_dp_compute_link_config() are
> > back-to-back. The
On Wed, Oct 27, 2021 at 12:57:37PM +0530, Nautiyal, Ankit K wrote:
>
> On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We lack sufficient state tracking to figure out whether
> > we want the DFP to perform the RGB->YCbCr conversion for us
> > or not. So currently we ar
On Wed, 27 Oct 2021, Matthew Auld wrote:
> On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>>
>> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
>> include asm/smp.h here.
>>
>> Reported-by: kernel test robot
>> Signed-off-by: Matthew Auld
>> Cc: Thomas Hellström
>
> Ja
On Wed, 27 Oct 2021, Jani Nikula wrote:
> On Wed, 27 Oct 2021, Matthew Auld wrote:
>> On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>>>
>>> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
>>> include asm/smp.h here.
>>>
>>> Reported-by: kernel test robot
>>> Signed-off
On Wed, 27 Oct 2021 at 09:58, Jani Nikula wrote:
>
> On Wed, 27 Oct 2021, Matthew Auld wrote:
> > On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
> >>
> >> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
> >> include asm/smp.h here.
> >>
> >> Reported-by: kernel test robo
On Tue, Oct 26, 2021 at 02:01:15PM +0300, Jani Nikula wrote:
> On Mon, 25 Oct 2021, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Looks like we never updated intel_bios_is_port_dp_dual_mode() when
> > the VBT port mapping became erratic on modern platforms. This
> > is causing us to look u
On Wed, 27 Oct 2021 at 09:36, Thomas Hellström
wrote:
>
> GPU relocs are gone. There should be no need for this workaround anymore.
> Remove it.
>
> Signed-off-by: Thomas Hellström
I was completely wrong here, sorry. Digging through the git history it
looks like this came from:
Commit 149c84077
Quoting Matthew Brost (2021-10-26 18:51:17)
> On Tue, Oct 26, 2021 at 11:59:35AM +0300, Joonas Lahtinen wrote:
> > Quoting Matthew Brost (2021-10-25 18:15:09)
> > > On Mon, Oct 25, 2021 at 12:37:02PM +0300, Joonas Lahtinen wrote:
> > > > Quoting Matthew Brost (2021-10-22 19:42:19)
> > > > > On Fri,
Avoid adding backend specific data to the tracepoints outside of
the LOW_LEVEL_TRACEPOINTS kernel config protection. These bits of
information are bound to change depending on the selected submission
method per platform and are not necessarily possible to maintain in
the future.
Fixes: dbf9da8d55e
On Wed, 27 Oct 2021, Matthew Auld wrote:
> On Wed, 27 Oct 2021 at 09:58, Jani Nikula wrote:
>>
>> On Wed, 27 Oct 2021, Matthew Auld wrote:
>> > On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>> >>
>> >> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
>> >> include asm/s
On Wed, 27 Oct 2021 at 10:44, Jani Nikula wrote:
>
> On Wed, 27 Oct 2021, Matthew Auld wrote:
> > On Wed, 27 Oct 2021 at 09:58, Jani Nikula
> > wrote:
> >>
> >> On Wed, 27 Oct 2021, Matthew Auld wrote:
> >> > On Thu, 21 Oct 2021 at 13:54, Matthew Auld
> >> > wrote:
> >> >>
> >> >> wbinvd_on_
DP 1.4 spec limits max compression bpp to
uncompressed bpp -1, which is supported from
XELPD onwards.
Instead of uncompressed bpp, max dsc input bpp
was being used to limit the max compression bpp.
Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4 compression BPPs")
Signed-off-by: Vandita Kulkar
On Wed, 27 Oct 2021 at 10:33, Joonas Lahtinen
wrote:
>
> Avoid adding backend specific data to the tracepoints outside of
> the LOW_LEVEL_TRACEPOINTS kernel config protection. These bits of
> information are bound to change depending on the selected submission
> method per platform and are not nec
== Series Details ==
Series: drm/i915/gem: Remove gpu reloc workaround
URL : https://patchwork.freedesktop.org/series/96333/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10795 -> Patchwork_21457
Summary
---
**FAILUR
On Tue, Oct 26, 2021 at 06:08:44PM -0400, Lyude Paul wrote:
> This simply adds proper support for panel backlights that can be controlled
> via VESA's backlight control protocol, but which also require that we
> enable and disable the backlight via PWM instead of via the DPCD interface.
> We also e
== Series Details ==
Series: drm/i915: Revert 'guc_id' from i915_request tracepoint
URL : https://patchwork.freedesktop.org/series/96336/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10795 -> Patchwork_21458
Summary
--
As we start to introduce asynchronous failsafe object migration,
where we update the object state and then submit asynchronous
commands we need to record what memory resources are actually used
by various part of the command stream. Initially for three purposes:
1) Error capture.
2) Asynchronous m
From: Thomas Hellström
The vma resource are needed for asynchronous bind management and are
similar to TTM resources. They contain the data needed for
asynchronous unbinding (typically the vm range, any backend
private information and a means to do refcounting and to hold
the unbinding for error
This patch series prepares error capture for asynchronous migration,
where the vma pages may not reflect the pages the GPU is currently
executing from but may be several migrations ahead.
The first patch deals with refcounting sg-list so that they don't
disappear under the capture code, which typi
With asynchronous migrations, the vma state may be several migrations
ahead of the state that matches the request we're capturing.
Address that by introducing an i915_vma_snapshot structure that
can be used to snapshot relevant state at request submission.
In order to make sure we access the correc
Quoting Dave Airlie (2021-10-26 03:34:52)
> On Mon, 25 Oct 2021 at 23:51, Daniel Vetter wrote:
> >
> > On Mon, Oct 25, 2021 at 3:49 PM Joonas Lahtinen
> > wrote:
> > >
> > > Add Tvrtko Ursulin as a co-maintainer for drm/i915 driver.
> > > Tvrtko will bring added bandwidth and focus to the GT/GEM
+ Jani and Rodrigo in order to pick this to -fixes.
Quoting Patchwork (2021-10-27 13:31:33)
> Patch Details
>
> Series: drm/i915: Revert 'guc_id' from i915_request tracepoint
> URL: https://patchwork.freedesktop.org/series/96336/
> State: success
> Details: https://intel-gfx-ci.01.org/tree
On 10/21/21 13:44, Matthew Auld wrote:
In theory if clflush_work_create() somehow fails here, and we don't yet
have mm.pages populated then we end up resetting cache_dirty, which is
likely wrong, since that will potentially skip the flush-on-acquire, if
it was needed.
It looks like intel_user_
On 10/21/21 13:44, Matthew Auld wrote:
We seem to have an unfortunate issue where we arrive from:
i915_gem_object_flush_if_display+0x86/0xd0 [i915]
intel_user_framebuffer_dirty+0x1a/0x50 [i915]
drm_mode_dirtyfb_ioctl+0xfb/0x1b0
Which can be before the pages are populated(and pi
Quoting Matthew Brost (2021-10-25 19:34:04)
> Hide the guc_id and tail fields, for request trace points, behind
> CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option. Trace points
> are ABI (maybe?) so don't change them without kernel developers Kconfig
> options.
I've pushed the simple fix to el
On 10/21/21 13:44, Matthew Auld wrote:
Move it next to its partner in crime; gpu_write_needs_clflush.
A motivation in the commit message?
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Otherwise:
Reviewed-by: Thomas Hellström
On 10/21/21 13:44, Matthew Auld wrote:
Should not be needed. Even with non-coherent display, we should be using
device local-memory there, and not system memory.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
On Tue, Oct 26, 2021 at 07:39:27PM +, Souza, Jose wrote:
> On Fri, 2021-10-22 at 13:32 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Disabling planes in the middle of the modeset seuqnece does not make
> > sense since userspace can anyway disable planes before the modeset
> > ev
== Series Details ==
Series: drm/i915: Revert 'guc_id' from i915_request tracepoint
URL : https://patchwork.freedesktop.org/series/96336/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10795_full -> Patchwork_21458_full
Summ
By using the modifier plane capability flags to encode the modifiers'
CCS type and tiling attributes, it becomes simpler to the check for
any of these capabilities when providing the list of supported
modifiers.
This also allows distinguishing modifiers on future platforms where
platforms with the
On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>
> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for a Cherry
> Trail tablet. It deviates from the typ
On Wed, 27 Oct 2021, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The i915 driver can use the backlight subsystem as an option, and usually
> selects it when CONFIG_ACPI is set. However it is possible to configure
> a kernel with modular backlight classdev support and a built-in i915
> driver,
On Wed, Oct 27, 2021 at 3:28 PM Arnd Bergmann wrote:
>
> Rather than having CONFIG_FB_BACKLIGHT select CONFIG_BACKLIGHT_CLASS_DEVICE,
> make any driver that needs it have a dependency on the class device
> being available, to prevent circular dependencies.
Acked-by: Miguel Ojeda
Cheers,
Miguel
From: Arnd Bergmann
The i915 driver can use the backlight subsystem as an option, and usually
selects it when CONFIG_ACPI is set. However it is possible to configure
a kernel with modular backlight classdev support and a built-in i915
driver, which leads to a linker error:
drivers/gpu/drm/i915/d
From: Arnd Bergmann
Rather than having CONFIG_FB_BACKLIGHT select CONFIG_BACKLIGHT_CLASS_DEVICE,
make any driver that needs it have a dependency on the class device
being available, to prevent circular dependencies.
This is the same way that the backlight is already treated for the DRM
subsystem
From: Arnd Bergmann
Selecting FB_DDC currently turns on CONFIG_I2C implicitly,
which is often not desired and can lead to circular dependencies.
Change this to a 'depends on' and change all drivers that
rely on FB_DDC to have an appropriate I2C dependency as well.
Signed-off-by: Arnd Bergmann
The PPS, RC_RANGE_PARAM, and RC_BUF_THRESH logging are clearly for
debugging, and should not be info level messages.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/
On Wed, 27 Oct 2021, Ville Syrjälä wrote:
> On Tue, Oct 26, 2021 at 02:01:15PM +0300, Jani Nikula wrote:
>> On Mon, 25 Oct 2021, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Looks like we never updated intel_bios_is_port_dp_dual_mode() when
>> > the VBT port mapping became erratic on
== Series Details ==
Series: drm/i915/dsc: Fix the usage of uncompressed bpp
URL : https://patchwork.freedesktop.org/series/96337/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10796 -> Patchwork_21459
Summary
---
**
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev2)
URL : https://patchwork.freedesktop.org/series/96281/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bf0df3812af8 drm/i915: Introduce refcounted sg-tables
69d21354f04a drm/i915: Update error cap
On Wed, Oct 27, 2021 at 03:27:12PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Selecting FB_DDC currently turns on CONFIG_I2C implicitly,
> which is often not desired and can lead to circular dependencies.
>
> Change this to a 'depends on' and change all drivers that
> rely on FB_DDC t
On Wed, 27 Oct 2021, "Hogander, Jouni" wrote:
> On Tue, 2021-10-26 at 15:33 -0700, José Roberto de Souza wrote:
>> PSR2 is supported in transcoder A and B on Alderlake-P.
>>
>> BSpec: 49185
>> Cc: Mika Kahola
>> Cc: Jouni Hogander
>> Signed-off-by: José Roberto de Souza
>
> LGTM
>
> Reviewed-b
On Wed, Oct 27, 2021 at 08:57:48AM +0100, Matthew Auld wrote:
On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
include asm/smp.h here.
Reported-by: kernel test robot
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Ja
On Wed, 27 Oct 2021, "Tolakanahalli Pradeep, Madhumitha"
wrote:
> On Mon, 2021-07-05 at 13:28 +0300, Jani Nikula wrote:
>> On Tue, 29 Jun 2021, "Souza, Jose" wrote:
>> > On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep
>> > wrote:
>> > > PCH display HPD IRQ is not detec
On Sat, 23 Oct 2021, Len Baker wrote:
> Sorry, but I'm missing something here. In linux-next this is the commit
> history of include/linux/stddef.h file:
>
> 3080ea5553cc stddef: Introduce DECLARE_FLEX_ARRAY() helper
> 50d7bd38c3aa stddef: Introduce struct_group() helper macro
> e7f18c22e6be stdde
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev2)
URL : https://patchwork.freedesktop.org/series/96281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10796 -> Patchwork_21460
Summary
-
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: - s/I915_TILING_F/TILING_4/g
- s/I9
On Mon, Oct 18, 2021 at 02:50:22PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Async flips are only capable of changing PLANE_SURF, hence we
> they can't easily be used with planar formats.
>
> Older platforms could require updating AUX_DIST as well, which
> is not possible. We'd have
== Series Details ==
Series: series starting with [1/3] fbdev: rework FB_DDC dependencies
URL : https://patchwork.freedesktop.org/series/96343/
State : failure
== Summary ==
Applying: fbdev: rework FB_DDC dependencies
Applying: fbdev: rework backlight dependencies
error: sha1 information is la
In theory if clflush_work_create() somehow fails here, and we don't yet
have mm.pages populated then we end up resetting cache_dirty, which is
likely wrong, since that will potentially skip the flush-on-acquire, if
it was needed.
It looks like intel_user_framebuffer_dirty() can arrive here before
We seem to have an unfortunate issue where we arrive from:
i915_gem_object_flush_if_display+0x86/0xd0 [i915]
intel_user_framebuffer_dirty+0x1a/0x50 [i915]
drm_mode_dirtyfb_ioctl+0xfb/0x1b0
which can be before the pages are populated(and pinned for display), and
so i915_gem_object_has_
Move it next to its partner in crime; gpu_write_needs_clflush. For
better readability lets keep gpu vs cpu at least in the same file.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 12
drivers/gpu/drm
Should not be needed. Even with non-coherent display, we should be using
device local-memory there, and not system memory.
v2: also add a warning in i915_gem_clflush_object
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström #v1
---
drivers/gpu/drm/i915/gem/i915_gem
== Series Details ==
Series: drm/i915/fb: Simplify modifier handling more (rev2)
URL : https://patchwork.freedesktop.org/series/96308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21461
Summary
---
On Wed, 27 Oct 2021 at 15:54, Lucas De Marchi wrote:
>
> On Wed, Oct 27, 2021 at 08:57:48AM +0100, Matthew Auld wrote:
> >On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
> >>
> >> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
> >> include asm/smp.h here.
> >>
> >> Report
On Mon, Oct 18, 2021 at 02:50:25PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The amount of plane registers we have to write has been steadily
> increasing, putting more pressure on the vblank evasion mechanism
> and forcing us to increase its time budget. Let's try to take some
> of t
This was for airlied to pull into drm-next
On Wed, 2021-10-27 at 09:18 +0200, Maxime Ripard wrote:
> Hi Lyude,
>
> On Mon, Oct 25, 2021 at 09:30:14PM -0400, Lyude Paul wrote:
> > topic/amdgpu-dp2.0-mst-2021-10-25:
> > UAPI Changes:
> > Nope!
> >
> > Cross-subsystem Changes:
> > drm_dp_update_pay
On 2021-10-27 04:00, Pekka Paalanen wrote:
> On Tue, 26 Oct 2021 11:36:33 -0400
> Harry Wentland wrote:
>
>> On 2021-10-14 15:44, Shankar, Uma wrote:
>>>
>
...
>> FWIW, AMD HW (depending on generation) can do these operations
>> (in this order):
>>
>> 1) 1D LUT (fixed or PWL programmable)
>
On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
Is it supported on all D13 or only on DG2? Could you point to the bspec
pag
== Series Details ==
Series: drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
URL : https://patchwork.freedesktop.org/series/96344/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21463
Summary
--
On Wed, Oct 27, 2021 at 05:23:59PM +0100, Matthew Auld wrote:
On Wed, 27 Oct 2021 at 15:54, Lucas De Marchi wrote:
On Wed, Oct 27, 2021 at 08:57:48AM +0100, Matthew Auld wrote:
>On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>>
>> wbinvd_on_all_cpus() is only defined on x86 it seems, plus
== Series Details ==
Series: drm/i915: make array states static const (rev2)
URL : https://patchwork.freedesktop.org/series/94688/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21464
Summary
---
**
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev2)
URL : https://patchwork.freedesktop.org/series/95715/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b258619cd9e1 drm/i915/dg2: Tile 4 plane format support
-:168: WARNING:LINE_CONTINUATIONS: Avoid unne
PSR2 is supported in transcoder A and B on Alderlake-P.
v2:
- explicity checking for transcoder A and B to avoid invalid transcoder
BSpec: 49185
Reviewed-by: Jouni Högander # v1
Cc: Jani Nikula
Cc: Mika Kahola
Cc: Jouni Hogander
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/
On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Chop skl_program_plane() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the c
== Series Details ==
Series: drm/i915/dsc: Fix the usage of uncompressed bpp
URL : https://patchwork.freedesktop.org/series/96337/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10796_full -> Patchwork_21459_full
Summary
---
On 27/10/2021 11:52, Thomas Hellström wrote:
As we start to introduce asynchronous failsafe object migration,
where we update the object state and then submit asynchronous
commands we need to record what memory resources are actually used
by various part of the command stream. Initially for three
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev2)
URL : https://patchwork.freedesktop.org/series/95715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21465
Summary
---
*
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/clflush: fixup handling of
cache_dirty
URL : https://patchwork.freedesktop.org/series/96348/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3f9f5df03650 drm/i915/clflush: fixup handling of cache_dirty
93b878411
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/clflush: fixup handling of
cache_dirty
URL : https://patchwork.freedesktop.org/series/96348/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
Hi,
On 10/27/21 15:38, Ville Syrjälä wrote:
> On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
>> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
>> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>>
>> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design for
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/clflush: fixup handling of
cache_dirty
URL : https://patchwork.freedesktop.org/series/96348/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21466
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev2)
URL : https://patchwork.freedesktop.org/series/96281/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10796_full -> Patchwork_21460_full
Sum
On Tue, Oct 26, 2021 at 05:48:20PM -0700, Umesh Nerlige Ramappa wrote:
> In preparation for GuC pmu stats, add a name to the execlists stats
> structure so that it can be differentiated from the GuC stats.
>
> Signed-off-by: Umesh Nerlige Ramappa
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c
Async flips are not supported by selective fetch and we had a check
for that but that check was only executed when doing modesets.
So moving this check to the page flip path, so it can be properly
handled.
This fix a failure in kms_async_flips@test-cursor.
Cc: Mika Kahola
Cc: Jouni Hogander
Sig
On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> DP 1.4 spec limits max compression bpp to
> uncompressed bpp -1, which is supported from
> XELPD onwards.
> Instead of uncompressed bpp, max dsc input bpp
> was being used to limit the max compression bpp.
So the input Pipe BPP wh
On 10/27/21 6:27 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
Rather than having CONFIG_FB_BACKLIGHT select CONFIG_BACKLIGHT_CLASS_DEVICE,
make any driver that needs it have a dependency on the class device
being available, to prevent circular dependencies.
This is the same way that the backli
On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
> On 10/20/2021 14:47, Matthew Brost wrote:
> > A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> > execlists. Doing as little as possible to support this interface for
> > execlists - basically just passing su
On Wed, Oct 27, 2021 at 04:59:00PM +0300, Jani Nikula wrote:
> The PPS, RC_RANGE_PARAM, and RC_BUF_THRESH logging are clearly for
> debugging, and should not be info level messages.
>
> Signed-off-by: Jani Nikula
I think in the patch commit title there is a typo 'dcs' i think you meant
drm/i915
On 10/27/2021 12:17, Matthew Brost wrote:
On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
On 10/20/2021 14:47, Matthew Brost wrote:
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execl
On Tue, Oct 26, 2021 at 05:48:21PM -0700, Umesh Nerlige Ramappa wrote:
> With GuC handling scheduling, i915 is not aware of the time that a
> context is scheduled in and out of the engine. Since i915 pmu relies on
> this info to provide engine busyness to the user, GuC shares this info
> with i915
On Wed, Oct 27, 2021 at 01:04:49PM -0700, John Harrison wrote:
> On 10/27/2021 12:17, Matthew Brost wrote:
> > On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
> > > On 10/20/2021 14:47, Matthew Brost wrote:
> > > > A weak implementation of parallel submission (multi-bb execbuf IOCTL)
== Series Details ==
Series: drm/i915/adlp: Extend PSR2 support in transcoder B (rev2)
URL : https://patchwork.freedesktop.org/series/96321/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10798 -> Patchwork_21467
Summary
---
On 2021-10-27 at 18:46:53 +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_
On 10/26/2021 23:36, Thomas Hellström wrote:
Hi, John,
On 10/26/21 21:55, John Harrison wrote:
On 10/21/2021 23:23, Thomas Hellström wrote:
On 10/21/21 22:37, Matthew Brost wrote:
On Thu, Oct 21, 2021 at 08:15:49AM +0200, Thomas Hellström wrote:
Hi, Matthew,
On Mon, 2021-10-11 at 16:47 -070
On 10/27/21 22:34, John Harrison wrote:
On 10/26/2021 23:36, Thomas Hellström wrote:
Hi, John,
On 10/26/21 21:55, John Harrison wrote:
On 10/21/2021 23:23, Thomas Hellström wrote:
On 10/21/21 22:37, Matthew Brost wrote:
On Thu, Oct 21, 2021 at 08:15:49AM +0200, Thomas Hellström wrote:
Hi,
== Series Details ==
Series: drm/i915/fb: Simplify modifier handling more (rev2)
URL : https://patchwork.freedesktop.org/series/96308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797_full -> Patchwork_21461_full
Summary
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