Hi, Christian,
We have a use-case in i915 with async evictions where we'd like to use
dma-fence-array in the following way
*Create in commit mode
*Add context and seqno,
*Publish (signaling critical section starts)
*Add fence pointers to the arrary
*Commit (signaling critical section ends, fen
On Tue, Oct 05, 2021 at 09:32:57PM -0700, lindsey.stanp...@gmail.com wrote:
> From: Cameron Nemo
>
> A recent commit [1] introduced an unintended behavioral change by
> reordering certain function calls. The sysfs_notify call for
> pin_assignment should only be invoked when the dp_altmode_notify
Hi,
Is it my checkout only or this causes a lot of build warnings for everyone?
./include/drm/drm_dp_helper.h:1120: warning:
"DP_TEST_264BIT_CUSTOM_PATTERN_7_0" redefined
1120 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
|
In file included from ./drivers/gpu/drm/amd/amdgpu/../di
On 07/10/2021 23:55, Oak Zeng wrote:
Fail this test earlier if i915_request_await_dma_fence
fails.
Why only this instance and not the other one in the same function?
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 9 -
1 file changed, 8 insert
Hi,
On 10/6/21 6:32 AM, lindsey.stanp...@gmail.com wrote:
> From: Cameron Nemo
>
> A recent commit [1] introduced an unintended behavioral change by
> reordering certain function calls. The sysfs_notify call for
> pin_assignment should only be invoked when the dp_altmode_notify call
> returns 0,
On 07/10/2021 19:18, Christian König wrote:
Am 07.10.21 um 17:53 schrieb Tvrtko Ursulin:
On 07/10/2021 16:18, Vudum, Lakshminarayana wrote:
-Original Message-
From: Tvrtko Ursulin
Sent: Thursday, October 7, 2021 6:41 AM
To: Christian König ;
intel-gfx@lists.freedesktop.org
Cc: Vud
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, October 7, 2021 11:11 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong ; Kahola, Mika
> ; Navare, Manasi D ;
> Souza, Jose ; Manna, Animesh
>
> Subject: Re: [PATCH v2 2/4] drm/i915/panelrepl
On 08/10/2021 10:17, Tvrtko Ursulin wrote:
On 07/10/2021 19:18, Christian König wrote:
Am 07.10.21 um 17:53 schrieb Tvrtko Ursulin:
On 07/10/2021 16:18, Vudum, Lakshminarayana wrote:
-Original Message-
From: Tvrtko Ursulin
Sent: Thursday, October 7, 2021 6:41 AM
To: Christian Köni
Hi Dave & Daniel,
Here goes the first PR towards 5.16.
As for the big things, this adds encrypted PXP (Protected Xe Path)
support for Gen12 integrated. Take a look at the "drm/i915/pxp: add
PXP documentation" for further details and the Mesa changes for how
the uAPI will look like.
Then adds DG1
Hi
Am 08.10.21 um 11:17 schrieb Nirmoy Das:
Debugfs API returns encoded error instead of NULL.
This patch cleanups drm debugfs error handling to
properly set dri and its minor's root dentry to NULL.
Also do not error out if dri/minor debugfs directory
creation fails as a debugfs error is not a
On Fri, 08 Oct 2021, Nirmoy Das wrote:
> Debugfs API returns encoded error instead of NULL.
> This patch cleanups drm debugfs error handling to
> properly set dri and its minor's root dentry to NULL.
>
> Also do not error out if dri/minor debugfs directory
> creation fails as a debugfs error is no
On Fri, Oct 08, 2021 at 01:00:06AM +0300, Imre Deak wrote:
> On Fri, Oct 08, 2021 at 12:32:57AM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 08, 2021 at 12:26:11AM +0300, Imre Deak wrote:
> > > On Fri, Oct 08, 2021 at 12:10:00AM +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 07, 2021 at 11:35:07PM
On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote:
> The I915_TILING_* definitions in the uapi header are intended solely for
> tiling modes that are visible to the old de-tiling fence ioctls. Since
> modern hardware does not support de-tiling fences, we should not add new
> definitions f
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator and its
users can observe an incosistent state which makes it impossible to use
safely. Such as:
<6> [187.517041] [IGT] gem_sync: execut
Hi Lucas,
> > I am reproposing this patch exactly as it was proposed initially
> > where the original interfaces are kept where they have been
> > originally placed. It might generate some duplicated code but,
> > well, it's debugfs and I don't see any issue. In the future we
> > can transform the
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The struct itself already has sufficient namespace. No need to
> duplicate it in the members.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
>
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> All the values we have in {icl_mg,tgl_dkl}_phy_ddi_buf_trans
> fit into u8. Shrink the types accordingly.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h |
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use <4 instead of <=3 as the terminating condition for the
> loops over the 4 lanes.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
> 1 file changed, 2 in
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add the FOO_LN() register macros for all the icl combo phy registers.
> Also get rid of the semi-pointless FOO_LN0() variants and just use
> the parametrized version.
>
> Signed-off-by: Ville Syrjälä
Might argue the phy should
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist,
> also the spec says to skip all loadgen stuff.
>
> The code was dead anyway since it wasn't actually writing the value
> anywhere.
>
> Signed-off-by: Ville Syrjälä
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the convoluted loadgen calculation into a small helper.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++-
> 1 file changed, 14 inse
On Fri, Oct 08, 2021 at 01:21:42PM +0300, Jani Nikula wrote:
> On Wed, 06 Oct 2021, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add the FOO_LN() register macros for all the icl combo phy registers.
> > Also get rid of the semi-pointless FOO_LN0() variants and just use
> > the parametrize
On 08/10/2021 11:21, Christian König wrote:
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator and
its
users can observe an incosistent
On Fri, Oct 08, 2021 at 12:40:47PM +0300, Jani Nikula wrote:
> On Fri, 08 Oct 2021, Nirmoy Das wrote:
> > Debugfs API returns encoded error instead of NULL.
> > This patch cleanups drm debugfs error handling to
> > properly set dri and its minor's root dentry to NULL.
> >
> > Also do not error out
[AMD Official Use Only]
Thanks, Greg and Jani. So I have to do the exact opposite.
We do have some NULL dentry check in the drm code. I will remove those instead.
Regards,
Nirmoy
From: Greg KH
Sent: Friday, October 8, 2021 1:07 PM
To: Jani Nikula
Cc: Das, Nirmo
Return early if crtc or connector's debugfs root dentries are NULL.
CC: Thierry Reding
CC: David Airlie
CC: Daniel Vetter
CC: Jonathan Hunter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/tegra/dc.c | 5 +
drivers/gpu/drm/tegra/dsi.c | 4
drivers/gpu/drm/tegra/hdmi.c | 5 +
Return early if dri minor root dentry is NULL.
CC: Zhenyu Wang
CC: Zhi Wang
CC: Jani Nikula
CC: Joonas Lahtinen
CC: Rodrigo Vivi
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gvt/debugfs.c | 3 +++
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
2 fil
Debugfs API returns encoded error instead of NULL.
This patch cleanups drm debugfs error handling to
properly set dri and its minor's root dentry to NULL.
Also do not error out if dri/minor debugfs directory
creation fails as a debugfs error is not a fatal error.
CC: Maarten Lankhorst
CC: Maxime
Return early if dri minor root dentry is NULL.
CC: Alex Deucher
CC: "Christian König"
CC: "Pan, Xinhui"
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/radeon/r100.c | 9 +
drivers/gpu/drm/radeon/r300.c | 3 +++
drivers/gpu/drm/radeon/r420.c | 3 +++
drivers/
Return early if dri minor root dentry is NULL.
CC: Russell King
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/armada/armada_debugfs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/armada/armada_debugfs.c
b/drivers/gpu/drm/armada
This patch series introduces failsafe migration blits.
The reason for this seemingly strange concept is that if the initial
clearing or readback of LMEM fails for some reason, and we then set up
either GPU- or CPU ptes to the allocated LMEM, we can expose old
contents from other clients.
So after
Move the release callback to after fence signaling to align with
what's done for upcoming VM_BIND user-fence signaling.
Finally call the work callback regardless of whether we have a fence
error or not and update the existing callbacks accordingly. We will
need this to intercept the error for fail
As we start to introduce asynchronous failsafe object migration,
where we update the object state and then submit asynchronous
commands we need to record what memory resources are actually used
by various part of the command stream. Initially for three purposes:
1) Error capture.
2) Asynchronous m
The TTM managers and, possibly, the gtt address space managers will
need to be able to order fences for async operation.
Using dma_fence_is_later() for this will require that the fences we hand
them are from a single fence context and ordered.
Introduce a struct dma_fence_work_timeline, and a func
If the initial fill blit or copy blit of an object fails, the old
content of the data might be exposed and read as soon as either CPU- or
GPU PTEs are set up to point at the pages.
Intercept the blit fence with an async dma_fence_work that checks the
blit fence for errors and if there are errors p
On eviction, TTM requires that migration fences from the same region are
ordered using dma_fence_is_later(). For request-based fences we therefore
need to use the same context for the migration, but now that we use a
dma_fence_work for error recovery, and, in addition, might need to coalesce
the mi
We are using a timeline-attached struct dma_fence_work to coalesce
dma-fences on eviction. In this mode we will not have a work callback
attached.
Similar to how the dma-fence-chain and dma-fence-array containers do this,
use irq work to signal to reduce latency.
Signed-off-by: Thomas Hellström
-
== Series Details ==
Series: series starting with [1/5] dri: cleanup debugfs error handling
URL : https://patchwork.freedesktop.org/series/95602/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
59b65376d0a0 dri: cleanup debugfs error handling
-:40: CHECK:PARENTHESIS_ALIGNMENT: Al
== Series Details ==
Series: series starting with [1/5] dri: cleanup debugfs error handling
URL : https://patchwork.freedesktop.org/series/95602/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator and its
users can observe an incosistent state which makes it impossible to use
safely.
Am 08.10.21 um 11:17 schrieb Nirmoy Das:
Return early if dri minor root dentry is NULL.
CC: Alex Deucher
CC: "Christian König"
CC: "Pan, Xinhui"
Signed-off-by: Nirmoy Das
Acked-by: Christian König
Where are the other patches from the series?
Thanks,
Christian.
---
drivers/gpu/drm/r
[AMD Official Use Only]
I sent all the patches to dr-devel. I think there is an issue with our email
server. Thunderbird is asking for a password every few minutes.
https://patchwork.freedesktop.org/series/95603/
Nirmoy
[sending this from my browser]
From: Koeni
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion
URL : https://patchwork.freedesktop.org/series/95605/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10699 -> Patchwork_21291
==
From: Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
F
From: Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
F
Hi,
please ignore! I run the command from the history and forgot that
I had to update the patch file. :)
V3 of this patch is coming soon.
Andi
On Fri, Oct 08, 2021 at 01:22:48PM +0200, Andi Shyti wrote:
> From: Andi Shyti
>
> The following interfaces:
>
> i915_wedged
> i915_forcewake_use
Am 08.10.21 um 12:49 schrieb Tvrtko Ursulin:
On 08/10/2021 11:21, Christian König wrote:
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterato
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
URL : https://patchwork.freedesktop.org/series/75333/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
99b302f7 drm/i915/gt: move remaining debugfs interfaces into gt
-:138: WARNING:FIL
On 10/7/2021 18:21, Matthew Brost wrote:
On Thu, Oct 07, 2021 at 03:03:04PM -0700, John Harrison wrote:
On 10/4/2021 15:06, Matthew Brost wrote:
Assign contexts in parent-child relationship consecutive guc_ids. This
is accomplished by partitioning guc_id space between ones that need to
be conse
On Fri, Oct 08, 2021 at 01:27:33PM +0200, Andi Shyti wrote:
> +
> + if (IS_CHERRYVIEW(i915)) {
> + seq_printf(m, "Master Interrupt Control:\t%08x\n",
> +intel_uncore_read(uncore, GEN8_MASTER_IRQ));
> +
> + for (i = 0; i < 4; i++) {
> +
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
URL : https://patchwork.freedesktop.org/series/75333/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21292
Summar
== Series Details ==
Series: Fixup header includes (rev2)
URL : https://patchwork.freedesktop.org/series/95587/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10697 -> Patchwork_21289
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: drm/i915: Failsafe migration blits
URL : https://patchwork.freedesktop.org/series/95617/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/inte
On 10/7/2021 12:50, John Harrison wrote:
On 10/4/2021 15:06, Matthew Brost wrote:
Add multi-lrc context registration H2G. In addition a workqueue and
process descriptor are setup during multi-lrc context registration as
these data structures are needed for multi-lrc submission.
v2:
(John Harr
On 10/4/2021 15:06, Matthew Brost wrote:
Implement multi-lrc submission via a single workqueue entry and single
H2G. The workqueue entry contains an updated tail value for each
request, of all the contexts in the multi-lrc submission, and updates
these values simultaneously. As such, the tasklet
== Series Details ==
Series: drm/i915: Failsafe migration blits
URL : https://patchwork.freedesktop.org/series/95617/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21293
Summary
---
**SUCCESS**
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev2)
URL : https://patchwork.freedesktop.org/series/95605/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dcabbee4ce57 dma-resv: Fix dma_resv_get_fences and dma_resv_copy_
On Fri, Oct 08, 2021 at 10:20:16AM -0700, John Harrison wrote:
> On 10/7/2021 12:50, John Harrison wrote:
> > On 10/4/2021 15:06, Matthew Brost wrote:
> > > Add multi-lrc context registration H2G. In addition a workqueue and
> > > process descriptor are setup during multi-lrc context registration a
On 10/4/2021 15:06, Matthew Brost wrote:
Update context and full GPU reset to work with multi-lrc. The idea is
parent context tracks all the active requests inflight for itself and
its' children. The parent context owns the reset replaying / canceling
Still its' should be its.
requests as need
On 10/4/2021 15:06, Matthew Brost wrote:
Display the workqueue status in debugfs for GuC contexts that are in
parent-child relationship.
v2:
(John Harrison)
- Output number children in debugfs
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_g
On 10/4/2021 15:06, Matthew Brost wrote:
Set number of engines before attempting to create contexts so the
function free_engines can clean up properly. Also check return of
alloc_engines for NULL.
v2:
(Tvrtko)
- Send as stand alone patch
(John Harrison)
- Check for alloc_engines return
Re-reported.
-Original Message-
From: De Marchi, Lucas
Sent: Friday, October 8, 2021 8:10 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.BAT: failure for Fixup header includes (rev2)
On Fri, Oct 08, 2021 at 06:44:35AM +, Patchwork wrote:
>==
On Fri, Oct 08, 2021 at 10:39:35AM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Update context and full GPU reset to work with multi-lrc. The idea is
> > parent context tracks all the active requests inflight for itself and
> > its' children. The parent context owns th
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev2)
URL : https://patchwork.freedesktop.org/series/95605/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21294
===
Ping
On Wed, Oct 06, 2021 at 08:37:03PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Taking a PM reference to prevent intel_gt_wait_for_idle from short
> > circuiting while a deregister context H2G is in flight. To do this must
> > issue the deregister H2G from a worker as
On Thu, Oct 07, 2021 at 12:35:08PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Introduce context parent-child relationship. Once this relationship is
> > created all pinning / unpinning operations are directed to the parent
> > context. The parent context is responsib
== Series Details ==
Series: series starting with [1/5] dri: cleanup debugfs error handling
URL : https://patchwork.freedesktop.org/series/95602/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10699_full -> Patchwork_21290_full
==
All display 9 and display 10 platforms has only 4 bits for the memory
frequency but display 11 platforms it changes to 8 bits.
Display 9 platforms has another register in bits 7:4 that prevents us
to have a single mask.
Also adding new mask with the current name in CRWebViewer, not
sure why curren
On 21/10/07 09:37PM, Fernando Ramos wrote:
> ---
> include/drm/drm_mode_config.h | 10 --
> 1 file changed, 10 deletions(-)
>
> diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
> index 48b7de80daf5..b214b07157f2 100644
>
This patch was missing the commit descrip
== Series Details ==
Series: drm/i915/icl: Fix read of memory frequency
URL : https://patchwork.freedesktop.org/series/95627/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fe3148c5e2ce drm/i915/icl: Fix read of memory frequency
-:17: WARNING:UNKNOWN_COMMIT_ID: Unknown commit id
This patch adds the following new sysfs frequency attributes;
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
- throttle_reason_thermal
- throttle_reason_prochot
- throttl
On 21/10/07 09:01PM, Patchwork wrote:
> == Series Details ==
>
> Series: drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers
> URL : https://patchwork.freedesktop.org/series/95578/
> State : warning
>
> == Summary ==
>
> $ dim sparse --fast origin/drm-tip
> Sparse version: v0.6.2
> Fast mode used
On 21/10/07 08:58PM, Patchwork wrote:
>
> 7bf784bb287c drm: cleanup: remove acquire_ctx from drm_mode_config
> -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate
> one
>
> -:27: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
>
> total: 1 errors, 1 warnings, 0 ch
On 21/10/07 11:58PM, Patchwork wrote:
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_21282_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_invalid_mode@clock-too-high:
> - shard-tg
On Fri, 2021-10-08 at 13:58 -0700, José Roberto de Souza wrote:
> All display 9 and display 10 platforms has only 4 bits for the memory
> frequency but display 11 platforms it changes to 8 bits.
>
> Display 9 platforms has another register in bits 7:4 that prevents us
> to have a single mask.
> Al
== Series Details ==
Series: drm/i915/icl: Fix read of memory frequency
URL : https://patchwork.freedesktop.org/series/95627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21295
Summary
---
**SUCCE
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev8)
URL : https://patchwork.freedesktop.org/series/95127/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
Some of our upcoming platforms, including the Xe_HP SDV, support a
"multi-tile" design. A multi-tile platform is effectively a platform
with multiple GT instances and local memory regions, all behind a single
PCI device. From an i915 perspective, this translates to multiple
intel_gt structures pe
From: Daniele Ceraolo Spurio
In coming patches we'll be doing the actual tile initialization between
these two uncore init phases.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 9 -
drivers/gpu/drm/i915/intel_uncore.c | 17 +
From: Tvrtko Ursulin
Add some basic plumbing to support more than one dynamically allocated
struct intel_gt. Up to four gts are supported in i915->gts[], with slot
zero shadowing the existing i915->gt to enable source compatibility with
legacy driver paths. A for_each_gt macro is added to itera
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/int
From: Paulo Zanoni
We'll be adding multi-tile support soon; on multi-tile platforms
interrupts are per-tile and every tile has the full set of
interrupt registers.
In this commit we start passing intel_gt instead of dev_priv for the
functions that are related to Xe_HP irq handling. Right now we'
From: Venkata Sandeep Dhanalakota
Iterate for_each_gt during release to support multi-tile
devices.
Cc: Tvrtko Ursulin
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --g
From: Daniele Ceraolo Spurio
Initialization and suspend/resume is replicated per-tile.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
drivers/gpu/drm/i
From: Paulo Zanoni
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then we read the
usual interrupt registers from the appropriate tile.
Note that this is just the first step of handling interrupts properly on
multi-tile
From: Michal Wajdeczko
Update CT debug macros by including tile ID in all messages.
Cc: Michał Winiarski
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/g
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
Bspec: 33407
Original-author: Abdiel
On a multi-tile platform, each tile has its own registers + GGTT space,
and BAR 0 is extended to cover all of them. Upcoming patches will start
exposing the tiles as multiple GTs within a single PCI device. In
preparation for supporting such setups, restructure the driver's probe
code a bit.
Onl
From: Paulo Zanoni
Loop through all the tiles when initializing and resetting interrupts.
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
URL : https://patchwork.freedesktop.org/series/75333/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21292_full
==
== Series Details ==
Series: series starting with [1/1] RFC : drm/i915: Adding new sysfs frequency
attributes
URL : https://patchwork.freedesktop.org/series/95629/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev8)
URL : https://patchwork.freedesktop.org/series/95127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21296
=
== Series Details ==
Series: i915: Initial multi-tile support
URL : https://patchwork.freedesktop.org/series/95631/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
21a66c454734 drm/i915: rework some irq functions to take intel_gt as argument
-:17: WARNING:BAD_SIGN_OFF: Non-standa
== Series Details ==
Series: i915: Initial multi-tile support
URL : https://patchwork.freedesktop.org/series/95631/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21298
Summary
---
**SUCCESS**
No
Hi Sujaritha,
On Fri, Oct 08, 2021 at 01:44:54PM -0700, Sujaritha Sundaresan wrote:
> This patch adds the following new sysfs frequency attributes;
> - punit_req_freq_mhz
> - throttle_reason_status
> - throttle_reason_pl1
> - throttle_reason_pl2
> - throttle_reason_pl
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev3)
URL : https://patchwork.freedesktop.org/series/95605/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f35815098fd4 dma-resv: Fix dma_resv_get_fences and dma_resv_copy_
On 10/8/2021 4:03 PM, Andi Shyti wrote:
Hi Sujaritha,
On Fri, Oct 08, 2021 at 01:44:54PM -0700, Sujaritha Sundaresan wrote:
This patch adds the following new sysfs frequency attributes;
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throt
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
v2:
- Include some additional refact
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev3)
URL : https://patchwork.freedesktop.org/series/95605/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21299
===
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