On Wed, 11 Aug 2021, Joonas Lahtinen wrote:
> Quoting Dave Airlie (2021-08-11 06:48:39)
>> dim: db47fe727e1f ("drm/i915/step:
>> s/_revid_tbl/_revids"): committer Signed-off-by
>> missing.
>>
>> I'm not sure how much pain it is to fix that up, but
>> commit db47fe727e1fc516cf60fc9ab8299605ef3c2d5
On Tue, 10 Aug 2021, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
>> On Mon, Aug 09, 2021 at 04:05:59PM +0200, Daniel Vetter wrote:
>> > On Fri, Aug 06, 2021 at 09:36:56AM +0300, Joonas Lahtinen wrote:
>> > > Hi Matt,
>> > >
>> > > Always use the dim tooling
== Series Details ==
Series: drm/i915/display: Fix the 12 BPC bits for PIPE_MISC reg (rev2)
URL : https://patchwork.freedesktop.org/series/93306/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10465_full -> Patchwork_20797_full
==
On Wed, 11 Aug 2021 at 17:11, Jani Nikula wrote:
>
> On Wed, 11 Aug 2021, Joonas Lahtinen wrote:
> > Quoting Dave Airlie (2021-08-11 06:48:39)
> >> dim: db47fe727e1f ("drm/i915/step:
> >> s/_revid_tbl/_revids"): committer Signed-off-by
> >> missing.
> >>
> >> I'm not sure how much pain it is to f
On Wed, 11 Aug 2021, Dave Airlie wrote:
> On Wed, 11 Aug 2021 at 17:11, Jani Nikula wrote:
>>
>> On Wed, 11 Aug 2021, Joonas Lahtinen wrote:
>> > Quoting Dave Airlie (2021-08-11 06:48:39)
>> >> dim: db47fe727e1f ("drm/i915/step:
>> >> s/_revid_tbl/_revids"): committer Signed-off-by
>> >> missing
On Thu, Aug 05 2021, Jason Gunthorpe wrote:
> Convert mbochs to use an atomic scheme for this like mtty was changed
> into. The atomic fixes various race conditions with probing. Add the
> missing error unwind. Also add the missing kfree of mdev_state->pages.
>
> Fixes: 681c1615f891 ("vfio/mbochs
On Thu, Aug 05 2021, Jason Gunthorpe wrote:
> From: Yishai Hadas
>
> PCI wants to have the usual open/close_device() logic with the slight
> twist that the open/close_device() must be done under a singelton lock
> shared by all of the vfio_devices that are in the PCI "reset group".
>
> The reset
On Wed, Aug 11, 2021 at 10:16:41AM +0300, Jani Nikula wrote:
> On Tue, 10 Aug 2021, Daniel Vetter wrote:
> > On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
> >> On Mon, Aug 09, 2021 at 04:05:59PM +0200, Daniel Vetter wrote:
> >> > On Fri, Aug 06, 2021 at 09:36:56AM +0300, Joonas Lahti
On Mon, Aug 09, 2021 at 07:32:26PM +, Matthew Brost wrote:
> On Mon, Aug 09, 2021 at 07:17:27PM +0200, Daniel Vetter wrote:
> > On Tue, Aug 03, 2021 at 03:29:43PM -0700, Matthew Brost wrote:
> > > Some workloads use lots of contexts that continually pin / unpin
> > > contexts. With GuC submissi
On Tue, Aug 10, 2021 at 05:29:46PM +, Matthew Brost wrote:
> On Tue, Aug 10, 2021 at 11:27:31AM +0200, Daniel Vetter wrote:
> > On Tue, Aug 10, 2021 at 11:23:39AM +0200, Daniel Vetter wrote:
> > > On Mon, Aug 09, 2021 at 07:13:11PM +, Matthew Brost wrote:
> > > > On Mon, Aug 09, 2021 at 06:
On Thu, Aug 05 2021, Jason Gunthorpe wrote:
> vfio_pci_try_bus_reset() is triggering a reset of the entire_dev set if
> any device within it has accumulated a needs_reset. This reset can only be
> done once all of the drivers operating the PCI devices to be reset are in
> a known safe state.
>
>
On Thu, Aug 05 2021, Jason Gunthorpe wrote:
> Like vfio_pci_dev_set_try_reset() this code wants to reset all of the
> devices in the "reset group" which is the same membership as the device
> set.
>
> Instead of trying to reconstruct the device set from the PCI list go
> directly from the device
On Thu, Aug 05 2021, Jason Gunthorpe wrote:
> Nothing uses this anymore, delete it.
>
> Signed-off-by: Yishai Hadas
> Reviewed-by: Christoph Hellwig
> Signed-off-by: Jason Gunthorpe
> ---
> drivers/vfio/mdev/vfio_mdev.c | 22 --
> drivers/vfio/vfio.c | 14 +--
On Wed, 11 Aug 2021, Daniel Vetter wrote:
> On Wed, Aug 11, 2021 at 10:16:41AM +0300, Jani Nikula wrote:
>> On Tue, 10 Aug 2021, Daniel Vetter wrote:
>> > On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
>> >> On Mon, Aug 09, 2021 at 04:05:59PM +0200, Daniel Vetter wrote:
>> >> > On Fr
> -Original Message-
> From: Intel-gfx On Behalf Of
> Shankar,
> Uma
> Sent: Wednesday, August 11, 2021 11:39 AM
> To: Nautiyal, Ankit K ;
> intel-gfx@lists.freedesktop.org
> Cc: Zanoni, Paulo R ; ville.syrj...@linux.intel.com;
> daniel.vet...@ffwll.ch; jani.nik...@linux.intel.com;
> j
On Wed, Aug 11, 2021 at 10:16:41AM +0300, Jani Nikula wrote:
> On Tue, 10 Aug 2021, Daniel Vetter wrote:
> > On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
> >> On Mon, Aug 09, 2021 at 04:05:59PM +0200, Daniel Vetter wrote:
> >> > On Fri, Aug 06, 2021 at 09:36:56AM +0300, Joonas Lahti
On Tue, 11 Aug 2021, "Lee, Shawn C" wrote:
>On Tue, 10 Aug 2021, Jani Nikula wrote:
>>On Tue, 10 Aug 2021, "Lee, Shawn C" wrote:
>>> On Tue, 10 Aug 2021, Jani Nikula wrote:
On Fri, 23 Jul 2021, Lee Shawn C wrote:
> DSI driver should have its own implementation to toggle gpio pins
== Series Details ==
Series: drm/i915/hdcp: HDCP2.2 MST dock fixes (rev4)
URL : https://patchwork.freedesktop.org/series/93570/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu/drm/am
On Wed, Aug 11, 2021 at 11:48:00AM +0200, Daniel Vetter wrote:
> On Wed, Aug 11, 2021 at 10:16:41AM +0300, Jani Nikula wrote:
> > On Tue, 10 Aug 2021, Daniel Vetter wrote:
> > > On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
> > >> On Mon, Aug 09, 2021 at 04:05:59PM +0200, Daniel Vett
== Series Details ==
Series: drm/i915/hdcp: HDCP2.2 MST dock fixes (rev4)
URL : https://patchwork.freedesktop.org/series/93570/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10467 -> Patchwork_20798
Summary
---
**SUC
== Series Details ==
Series: drm/i915/hdcp: HDCP2.2 MST dock fixes (rev4)
URL : https://patchwork.freedesktop.org/series/93570/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10467_full -> Patchwork_20798_full
Summary
--
On Wed, Aug 11, 2021 at 12:04:04PM +0200, Daniel Vetter wrote:
> On Tue, Aug 10, 2021 at 05:29:46PM +, Matthew Brost wrote:
> > On Tue, Aug 10, 2021 at 11:27:31AM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 10, 2021 at 11:23:39AM +0200, Daniel Vetter wrote:
> > > > On Mon, Aug 09, 2021 at 07:
On Wed, Aug 11, 2021 at 11:55:48AM +0200, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 07:32:26PM +, Matthew Brost wrote:
> > On Mon, Aug 09, 2021 at 07:17:27PM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 03, 2021 at 03:29:43PM -0700, Matthew Brost wrote:
> > > > Some workloads use lots of
On Tue, Aug 10, 2021 at 08:47:10AM +0200, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 06:20:51PM +, Matthew Brost wrote:
> > On Mon, Aug 09, 2021 at 04:27:01PM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 03, 2021 at 03:29:08PM -0700, Matthew Brost wrote:
> > > > Calling switch_to_kernel_co
On Tue, Aug 10, 2021 at 08:53:16AM +0200, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 06:37:01PM +, Matthew Brost wrote:
> > On Mon, Aug 09, 2021 at 04:30:06PM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 03, 2021 at 03:29:11PM -0700, Matthew Brost wrote:
> > > > Expose logical engine insta
On Tue, Aug 10, 2021 at 11:07:55AM +0200, Daniel Vetter wrote:
> On Tue, Aug 10, 2021 at 10:53:37AM +0200, Daniel Vetter wrote:
> > On Mon, Aug 09, 2021 at 06:58:23PM +, Matthew Brost wrote:
> > > On Mon, Aug 09, 2021 at 05:17:34PM +0200, Daniel Vetter wrote:
> > > > On Tue, Aug 03, 2021 at 03:
On Tue, Aug 10, 2021 at 10:53:37AM +0200, Daniel Vetter wrote:
> On Mon, Aug 09, 2021 at 06:58:23PM +, Matthew Brost wrote:
> > On Mon, Aug 09, 2021 at 05:17:34PM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 03, 2021 at 03:29:13PM -0700, Matthew Brost wrote:
> > > > Implement GuC parent-child
On Tue, Aug 10, 2021 at 04:52:11PM -0700, Juston Li wrote:
> When reading RepeaterAuth_Send_ReceiverID_List, RxInfo is read by itself
> once to retrieve the DEVICE_COUNT to calculate the size of the
> ReceiverID list then read a second time as a part of reading ReceiverID
> list.
>
> On some MST d
On Wed, 2021-08-11 at 15:34 -0400, Rodrigo Vivi wrote:
> On Tue, Aug 10, 2021 at 04:52:11PM -0700, Juston Li wrote:
> > When reading RepeaterAuth_Send_ReceiverID_List, RxInfo is read by
> > itself
> > once to retrieve the DEVICE_COUNT to calculate the size of the
> > ReceiverID list then read a sec
On Fri, 2021-08-06 at 10:41 -0700, Matt Roper wrote:
> The SFC_DONE register lives within the corresponding VD0/VD2/VD4/VD6
> forcewake domain and is not accessible if the vdbox in that domain is
> fused off and the forcewake is not initialized.
>
> This mistake went unnoticed because until recent
On Wed, Aug 11, 2021 at 01:55:48PM -0700, Souza, Jose wrote:
> On Fri, 2021-08-06 at 10:41 -0700, Matt Roper wrote:
> > The SFC_DONE register lives within the corresponding VD0/VD2/VD4/VD6
> > forcewake domain and is not accessible if the vdbox in that domain is
> > fused off and the forcewake is n
Update cp_irq_count_cached when reading messages rather than when
writing a message to make sure the value is up to date and not
stale from a previously handled CP_IRQ.
AKE flow doesn't always respond to a read with a ACK write msg.
E.g. AKE_Send_Pairing_Info will "timeout" because we received
a
Fixes to get HDCP2.2 over MST working on MST docking stations with
certain behaviors that cause the current flow to fail.
Tested with Dell WD-19 and Lenovo ThinkPad USB Type-C Dock Gen 2.
These fixes should make the flow more robust to handle behaviors that as
far as I can tell are unclear in the
When reading RepeaterAuth_Send_ReceiverID_List, RxInfo is read by itself
once to retrieve the DEVICE_COUNT to calculate the size of the
ReceiverID list then read a second time as a part of reading ReceiverID
list.
On some MST docking stations, RxInfo can only be read after the RxStatus
READY bit i
On some MST docking stations, rx_info can only be read after
RepeaterAuth_Send_ReceiverID_List and the RxStatus READY bit is set
otherwise the read will return -EIO.
This behavior causes the mst stream type1 capability test to fail to
read rx_info and determine if the topology supports type1 and f
On Thu, 5 Aug 2021 22:18:56 -0300
Jason Gunthorpe wrote:
> This is in support of Max's series to split vfio-pci. For that to work the
> reflck concept embedded in vfio-pci needs to be sharable across all of the
> new VFIO PCI drivers which motivated re-examining how this is
> implemented.
>
> A
== Series Details ==
Series: drm/i915/hdcp: HDCP2.2 MST dock fixes (rev5)
URL : https://patchwork.freedesktop.org/series/93570/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10470 -> Patchwork_20799
Summary
---
**SUC
== Series Details ==
Series: drm/i915/hdcp: HDCP2.2 MST dock fixes (rev5)
URL : https://patchwork.freedesktop.org/series/93570/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10470_full -> Patchwork_20799_full
Summary
--
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/intel_device_info.h
between commit:
3ffe82d701a4 ("drm/i915/xehp: handle new steering options")
from the drm tree and commit:
22e26af76903 ("drm/i915: Fork DG1 interrupt handler")
from the dr
On 9.7.2021 0.18, José Roberto de Souza wrote:
Same bit was required for Wa_14012131227 in DG1 now it is also
required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
1
Patch looks good to me.
I think we must add fixes tag with the below commit:
https://cgit.freedesktop.org/drm-tip/commit/?id=9488a030ac91447ea186ca3b7ec5c72ff03bc202
Reviewed-by: Ankit Nautiyal
On 7/27/2021 12:21 AM, Swati Sharma wrote:
drm_dp_dpcd_read/write already has debug error message.
From: Matt Atwood
intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to
use before intel_encoder->type is set. This causes incorrect max source
rate to be used for display 11+. On EHL and JSL, HBR3 is used instead of
HBR2, and on the other affected platforms, HBR2 is used instea
HBR3 support for display gen11+ platform is depends upon some
conditions which are mentioned below.
ICL:
- eDP (only on DDI-A): Up to HBR3 for higher Vccio.
- DP:
- (DDI-B, combo phy): upto HBR2.
- (DDI-C to DDI-F): upto HBR3
RKLC:
- eDP/DP: Up to HBR3? Vccio dependent? (missing
From: Jani Nikula
Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is
limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz.
Bspec: 20584, 20598, 49180, 49201
Cc: Imre Deak
Signed-off-by: Jani Nikula
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c
Only higher voltage sku can support HBR3 so a condition
check added in max source rate calculation for ehl/jsl.
Bspec: 32247, 20598
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Added support for platforms having DISPLAY13 like DG2, ADL_P and ADL_S.
Bspec: 53597, 53720, 53657, 54034, 49185, 55409
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/
From: Jani Nikula
Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP
can do 8.1 GHz on combo phy.
Bspec: 49182, 49205, 49202
Cc: Imre Deak
Signed-off-by: Jani Nikula
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 +++-
1 file
On 12.8.2021 6.27, Timo Aaltonen wrote:
On 9.7.2021 0.18, José Roberto de Souza wrote:
Same bit was required for Wa_14012131227 in DG1 now it is also
required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i91
Gen >= 12 onwards MOCS table doesn't have a setting for PTE
so I915_MOCS_PTE is not a valid index and it will have different
MOCS values based on the platform.
To detect these kinds of misprogramming, all the unspecified and
reserved MOCS indexes are set to WB_L3.
This series also contains patche
During to creation mocs table,used field of drm_i915_mocs_entry
is being checked, if used field is 0, then it will check values
of index 1. All the unspecified indexes of xxx_mocs_table[] will
contain control value and l3cc value of index I915_MOCS_PTE if
its initialized.
This patch is intended to
Now there are lots of Command and registers that require mocs index
programming.
So propagating mocs_index from mocs to gt so that it can be
used directly without having platform-specific checks.
Signed-off-by: Ayaz A Siddiqui
Cc: CQ Tang
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 4
d
From: Apoorva Singh
Blitter commands which does not have MOCS fields rely on
cacheability of BlitterCacheControlRegister which was mapped
to index 0 by default.Once we changed the MOCS value of
index 0 to L3 WB, tests like gem_linear_blits started failing
due to change in cacheability from UC to
From: Srinivasan Shanmugam
Program CMD_CCTL to use a mocs entry for uncached access.
This controls memory accesses by CS as it reads instructions
from the ring and batch buffers.
Signed-off-by: Srinivasan Shanmugam
Signed-off-by: Ayaz A Siddiqui
Cc: Chris Wilson
Cc: Matt Roper
---
drivers/g
In order to program unused and reserved mocs entries to L3_WB,
we need to create a separate mocs table for alderlake.
This patch will also covers wa_1608975824.
Cc: Lucas De Marchi
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 40 +++-
1 file
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