Aside from deleting lots of code the real motivation here is to switch
the mmap over to VM_PFNMAP, to be more consistent with what real gpu
drivers do. They're all VM_PFNMP, which means get_user_pages doesn't
work, and even if you try and there's a struct page behind that,
touching it and mucking a
== Series Details ==
Series: Minor revid/stepping and workaround cleanup (rev5)
URL : https://patchwork.freedesktop.org/series/92299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
486210f705f0 drm/i915/step: s/_revid_tbl/_revids
5a7f5fb477f9 drm/i915: Make pre-production detect
== Series Details ==
Series: Minor revid/stepping and workaround cleanup (rev5)
URL : https://patchwork.freedesktop.org/series/92299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10343 -> Patchwork_20590
Summary
---
== Series Details ==
Series: drm/i915/ehl: Resolve insufficient header credits in MIPI DSI
URL : https://patchwork.freedesktop.org/series/92498/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fa23f279ade1 drm/i915/ehl: Resolve insufficient header credits in MIPI DSI
-:6: WARNING
== Series Details ==
Series: drm/i915/ehl: Resolve insufficient header credits in MIPI DSI
URL : https://patchwork.freedesktop.org/series/92498/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10343 -> Patchwork_20591
Summary
On 7/10/2021 8:52 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Replicate the SLPC header file in GuC for the most part. There are
what you mean by "replicate" here?
some SLPC mode based parameters which haven't been included since
we are not using them.
Signe
== Series Details ==
Series: drm/fb-helper: Try to protect cleanup against delayed setup
URL : https://patchwork.freedesktop.org/series/92478/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10341_full -> Patchwork_20587_full
== Series Details ==
Series: drm/i915: Tweaked Wa_14010685332 for all PCHs (rev4)
URL : https://patchwork.freedesktop.org/series/88435/
State : failure
== Summary ==
Applying: drm/i915: Tweaked Wa_14010685332 for all PCHs
error: patch failed: drivers/gpu/drm/i915/display/intel_display_power.c:
== Series Details ==
Series: shmem helpers for vgem (rev6)
URL : https://patchwork.freedesktop.org/series/90670/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
00c2c63016d4 dma-buf: Require VM_PFNMAP vma for mmap
-:34: WARNING:TYPO_SPELLING: 'entires' may be misspelled - perhaps
== Series Details ==
Series: shmem helpers for vgem (rev6)
URL : https://patchwork.freedesktop.org/series/90670/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10343 -> Patchwork_20593
Summary
---
**FAILURE**
Serio
On 7/14/21 4:30 AM, Ville Syrjälä wrote:
On Tue, Jul 13, 2021 at 09:34:09AM +0800, Lu Baolu wrote:
On 7/12/21 11:47 PM, Ville Syrjälä wrote:
On Mon, Jul 12, 2021 at 07:23:07AM +0800, Lu Baolu wrote:
On 7/10/21 12:47 AM, Ville Syrjala wrote:
From: Ville Syrjälä
While running "gem_exec_big --r
On 7/10/2021 9:05 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Allocate data structures for SLPC and functions for
initializing on host side.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c |
From: Tvrtko Ursulin
On Xe_HP the fusing register is renamed and changed to have the "enable"
semantics, but otherwise remains compatible (mmio address, bitmask
ranges) with older platforms.
To simplify things we do not add a new register definition but just stop
inverting the fusing masks befor
From: Paulo Zanoni
The current interrupt handler is getting increasingly complicated and
Xe_HP changes will bring even more complexity. Let's split off a new
interrupt handler starting with DG1 (i.e., when the master tile
interrupt register was added to the design) and use that as the basis
for
From: Venkata Sandeep Dhanalakota
In Gen12 there are various fuse combinations and in each configuration
vdbox engine may be connected to SFC depending on which engines are
available, so we need to set the SFC capability based on fuse value from
the hardware. Even numbered physical instance alway
From: Lucas De Marchi
Our _FEATURES macro went back to GEN7, extending each other, making it
difficult to grasp what was really enabled/disabled. Take the
opportunity of the GEN -> XE_HP name break and also break with the
feature inheritance.
For XE_HP this basically goes from GEN12 back to GEN7
This series provides some of the initial enablement patches for two
upcoming discrete GPUs:
* XeHP SDV: Xe_HP (version 12.50) graphics IP, no display IP
* DG2: Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP
Both platforms will need additional enablement patches beyond what'
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the
interrupt handler support for them.
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: John Harrison
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_irq
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
v2:
- Re-order intel_gt_info and intel_device_info slightly to avoid
unnecessary padding now that we've increased the size of
intel_engine_mask_t. (Tvrtko)
Cc: Tvrtko Ursulin
Since we can't steer multicast register reads during ring-based
workaround verification, we need to define the multicast ranges where
failure to steer could potentially cause us to read back from a
fused-off register instance.
As with gen12, we can ignore the multicast ranges that the bspec
descri
From: John Harrison
Increasing the engine count causes a couple of local array variables
to exceed the kernel stack limit. So make them dynamic allocations
instead.
Signed-off-by: John Harrison
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the reset
support for them.
Signed-off-by: John Harrison
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_reset.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 8
2 files changed, 14 ins
From: Daniele Ceraolo Spurio
Xe_HP is more modular then its predecessors and as a consequence it has
more types of replicated registers. As with l3bank regions on previous
platforms, we may need to explicitly re-steer accesses to these new
types of ranges at runtime if we can't find a single def
From: Stuart Summers
Xe_HP changes the format of the context ID from past platforms.
Signed-off-by: Stuart Summers
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Matt Roper
---
.../drm/i915/gt/intel_execlists_submission.c | 74 ---
drivers/gpu/drm/i915/gt/intel_lrc.c
We no longer have traditional slices on Xe_HP platforms, but the
INSTDONE registers are replicated according to gslice representation
which is similar. We can mostly re-use the existing instdone code with
just a few modifications:
* Create an alternate instdone loop macro that will iterate over
Implement Xe_HP forcewake handling. While we're at it, let's reorder to
the forcewake assignment if/else ladder to match our usual driver
conventions.
Co-authored-by: Daniele Ceraolo Spurio
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
.../
From: Prathap Kumar Valsan
The layout of some engine contexts has changed on Xe_HP. Define the new
offsets.
Bspec: 45585, 46256
Signed-off-by: Prathap Kumar Valsan
Signed-off-by: Ramalingam C
Signed-off-by: Venkata Ramana Nayana
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Matt Roper
--
The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this
register is now a per-tile register at GTTMMADDR offset 0x250014.
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++-
dr
For tgl+, the per-context setting of MI_MODE[12] determines whether
the bits of a nested MI_BATCH_BUFFER_START instruction should be
interpreted in the traditional manner or whether they should
instead use a new tgl+ meaning that breaks backward compatibility, but
allows nesting into 3rd-level batc
Xe_HPG adds some additional INSTDONE_GEOM debug registers; the Mesa team
has indicated that having these reported in the error state would be
useful for debugging GPU hangs. These registers are replicated per-DSS
with gslice steering.
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
Acked-by: Li
DG2 has no shared DPLL's or DDI clock muxing. The Port PLL is embedded
within the PHY.
Bspec: 54032
Bspec: 54034
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 -
2 files ch
From: Gwan-gyeong Mun
The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.
Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/in
From: José Roberto de Souza
PSR2 is not supported on DG2.
Cc: Caz Yokoyama
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
Note that DG2 only has a single possible refclk frequency (38.4 MHz).
Bspec: 54034
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 24 --
1 file changed, 22 insertions(+), 2 deletions(-)
diff --g
Vswing programming for SNPS PHYs is just a single step -- look up the
value that corresponds to the voltage level from a table and program it
into the SNPS_PHY_TX_EQ register.
Bspec: 53920
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/int
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 destined transaction" and L3_LKP to "enable Lookup for
uncacheable accesses".
Bspec: 45101
Cc: Daniele Ceraolo Spuri
DG2 has Xe_LPD display (version 13) and Xe_HPG (version 12.55) graphics.
There are two variants (treated as subplatforms in the code): DG2-G10
and DG2-G11 that require independent programming in some areas (e.g.,
workarounds).
Bspec: 44472, 44474, 46197, 48028, 48077
Cc: Anusha Srivatsa
Signed-o
Although the bspec labels four of DG2's outputs as "combo PHY," the
underlying PHYs in both cases are actually Synopsys PHYs that are
programmed completely differently than the traditional Intel "combo" PHY
units. As such, we don't want intel_phy_is_combo to take us down legacy
programming paths,
DG2 extends our DDB to four DBuf slices; pipes A+B only have access to
the first two slices, whereas pipes C+D only have access to the second
two.
Confusingly, our bspec decided to switch from 1-based numbering
of dbuf slices (S1, S2) to 0-based numbering (S0, S1, S2, S3) in
Display13. At the mom
DG2 has some changes to the expected modesetting sequences when compared
to gen12. Adjust our driver logic accordingly. Although the DP
sequence is pretty similar to TGL's, there are some steps that change,
so let's split the handling for that out into a separate function.
v2:
- Switch wait_for
From: Lucas De Marchi
XeHP SDV is a Intel® dGPU without display. This is just the definition
of some basic platform macros, by large a copy of current state of
Tigerlake which does not reflect the end state of this platform.
v2:
- Switch to intel_step infrastructure for stepping matches. (Jani)
DG2 has outputs on DDI A-D attached to what the bspec diagram shows as
"Combo PHY A-D." Note that despite being labelled "combo" the PHYs on
these outputs are Synopsys PHYs rather than traditional Intel combo PHY
technology.
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i91
Define and initialize the MMIO ranges for which XeHP SDV requires MSLICE
and LNCF steering.
Bspec: 66534
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++-
drivers/gpu/drm/i915/gt/intel_workarounds.c
Due to the removal of legacy slices and the transition to a
gslice/cslice/mslice/etc. design, we'll internally store all DSS under
"slice0."
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 -
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
drivers/gpu/drm/
The DG2 forcewake table is very similar to the one used by XeHP SDV (and
both platforms are even presented as a single table in the bspec). For
the most part DG2 starts using a few additional ranges that were
'reserved' on XeHP SDV and stops using some others. However there is a
single range (0xd
As with DG1, DG2 has an ICL-style south display interface provided on
the same PCI device. Add a fake PCH to ensure DG2 takes the appropriate
codepaths for south display handling.
Bspec: 54871, 50062, 49961, 53673
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
Signe
DG2's replicated register ranges are almost the same at XeHP SDV with
the exception of one LNCF sub-range that switches to gslice steering.
We can re-use the XeHP SDV mslice steering table and just provide a
DG2-specific LNCF steering table.
Bspec: 66534
Cc: Daniele Ceraolo Spurio
Signed-off-by:
From: Stuart Summers
Starting in XeHP, the concept of slice has been removed in favor of
DSS (Dual-Subslice) masks for various workload types. These workloads have
been divided into those enabled for geometry and those enabled for compute.
i915 currently maintains a single set of S/SS/EU masks f
Although the BW_BUDDY registers still exist, they are not used for
anything on DG2. This change is expected to hold true for future dgpu's
too.
Bspec: 49218
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
1 file changed, 4 insertions(+)
diff --git a/d
From: Ankit Nautiyal
Add the functions to configure HDMI2.1 pcon for DG2, before DP link
training.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi
On DG2 we're supposed to just wait 600us after programming the well
before moving on; there won't be an ack from the hardware.
Bspec: 49296
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_display_power.c | 16
.../gpu/drm/i915/display/intel_display_power.h | 6
Bspec: 45101, 45427
Cc: Ramalingam C (v5)
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 0c9d0b93
At the moment we don't have a proper algorithm that can be used to
calculate PHY settings for arbitrary HDMI link rates. The PHY tables
here should support the regular modes of real-world HDMI monitors.
Bspec: 54032
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-off-by: Vandita Kulkarni
---
Although DG2_G10 platforms will always have all SQIDI's present and
don't need steering for registers in a SQIDI MMIO range, this isn't true
for DG2_G11 platforms; only SQIDI's 2 and 3 can be used on those.
We handle SQIDI ranges a bit differently from other types of explicit
steering. The SQIDI
From: Matthew Auld
Xe_HP no longer has "slices" in the same way that old platforms did.
There are new concepts (gslices, cslices, mslices) that apply in various
contexts, but for the purposes of fusing slices no longer exist and we
just have one large pool of dual-subslices (DSS) to work with.
Fu
DG2 does not use system DRAM information for BW_BUDDY programming or
watermark workarounds, so there's no need to read this out at startup.
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_dram.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
DG2 doesn't have a SAGV or QGV points that determine memory bandwidth.
Instead it has a constant amount of memory bandwidth available to
display that does not need to be reduced based on the number of active
planes.
For simplicity, we'll just modify driver initialization to create a
single dummy Q
Initialization of the PHY is handled by the hardware/firmware, but the
driver should wait up to 25ms for the PHY to report that its calibration
has completed.
Bspec: 49189
Bspec: 50107
Cc: Matt Atwood
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_display_power.c| 5 +
dr
From: Animesh Manna
In verify_mpllb_state() encoder is retrieved from best_encoder
of connector_state. As there will be only one connector_state
for bigjoiner and checking encoder may not be needed for
bigjoiner-slave. This code path related to mpll is done on dg2
and need this fix to avoid null
DG2's SNPS PHYs incorporate a dedicated port PLL called MPLLB which
takes the place of the shared DPLLs we've used on past platforms. Let's
add the MPLLB programming sequences; they'll be plugged into the rest of
the code in future patches.
Bspec: 54032
Bspec: 53881
Cc: Lucas De Marchi
Signed-of
From: Lucas De Marchi
Instead of maintaining the same if ladder in 3 different places, add a
function to read RP_STATE_CAP.
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 17
From: Akeem G Abodunrin
New LRI register offsets were introduced for DG2, this patch adds
those extra registers, and create new register table for setting offsets
to compare with HW generated context image - especially for gt_lrc test.
Also updates general purpose register with scratch offset for
DG2 supports compute DSS and has the same maximum number of DSS and EU
as XeHP SDV.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms (rev5)
URL : https://patchwork.freedesktop.org/series/92135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7a5fbcb1f150 drm/i915: Add XE_HP initial definitions
8bb98dab1d23 drm/i915: Fork DG1 interrupt hand
== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms (rev5)
URL : https://patchwork.freedesktop.org/series/92135/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/d
== Series Details ==
Series: drm/i915: Fix wm params for ccs
URL : https://patchwork.freedesktop.org/series/92491/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10342_full -> Patchwork_20589_full
Summary
---
**FAILUR
== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms (rev5)
URL : https://patchwork.freedesktop.org/series/92135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10344 -> Patchwork_20594
Summary
---
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