An async-put on an encoder specific power domain (for instance the AUX
PW domain) may be pending when removing the encoder. Make sure any such
async-puts are complete while the corresponding encoder is still in place
since at least AUX power wells require this to do a power well->PHY
lookup.
Signe
On ADL_P the power well->PHY mapping doesn't follow the mapping on previous
platforms, fix this up.
While at it remove the redundant dev_priv param from
icl_tc_phy_aux_ch().
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_power.c| 34 ++-
1 file changed, 18 i
It's possible that an already dequeued put_async_work() will release the
reference (*) that was put asynchronously after the dequeue happened.
This leaves an async-put work pending, without any reference to release.
A subsequent async-put may trigger the
drm_WARN_ON(!queue_delayed_work(&power_doma
On Wed, May 26, 2021 at 05:26:56PM +0300, Jani Nikula wrote:
> On Wed, 26 May 2021, Bhanuprakash Modem wrote:
> > It's useful to know the dithering state & pipe bpc for IGT testing.
> > This patch will expose the dithering state for the crtc via a debugfs
> > file "dither".
> >
> > Example usage:
On Wed, 26 May 2021, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> We have a few modparams which get conditionaly exposed based on a Kconfig
> options and in most cases this also means portions of the driver
> implementing the respective feature are also left out.
>
> Align the visibility of d
tldr; DMA buffers aren't normal memory, expecting that you can use
them like that (like calling get_user_pages works, or that they're
accounting like any other normal memory) cannot be guaranteed.
Since some userspace only runs on integrated devices, where all
buffers are actually all resident sys
shmem helpers seem a bit sloppy here by automatically rounding up when
actually creating the buffer, which results in under-reporting of what
we actually have. Caught by igt/vgem_basic tests.
Acked-by: Thomas Zimmermann
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: T
Aside from deleting lots of code the real motivation here is to switch
the mmap over to VM_PFNMAP, to be more consistent with what real gpu
drivers do. They're all VM_PFNMP, which means get_user_pages doesn't
work, and even if you try and there's a struct page behind that,
touching it and mucking a
Since
commit 96667f8a4382db9ed042332ca6ee165ae9b91307
Author: Daniel Vetter
Date: Fri Nov 27 17:41:21 2020 +0100
mm: Close race in generic_access_phys
it is race-free and can therefore be safely used for dynamic mappings
like we have too.
Cc: Jon Bloomfield
Signed-off-by: Daniel Vetter
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90582/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20198_full
Summary
--
Since
commit 96667f8a4382db9ed042332ca6ee165ae9b91307
Author: Daniel Vetter
Date: Fri Nov 27 17:41:21 2020 +0100
mm: Close race in generic_access_phys
it is race-free and can therefore be safely used for dynamic mappings
like we have too.
v2 git commit --amend
*sigh*
Cc: Jon Bloomfield
> From: Jani Nikula
> Sent: Wednesday, May 26, 2021 7:57 PM
> To: Modem, Bhanuprakash ; intel-
> g...@lists.freedesktop.org; Varide, Nischal ;
> Shankar, Uma ; Gupta, Anshuman
>
> Cc: Ville Syrjälä
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/debug: Expose Dither
> status via debugfs
> From: Jani Nikula
> Sent: Wednesday, May 26, 2021 7:34 PM
> To: Modem, Bhanuprakash ; intel-
> g...@lists.freedesktop.org; Varide, Nischal ;
> Shankar, Uma ; Gupta, Anshuman
>
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/xelpd: Enabling dithering after
> the CC1
>
> On Wed, 26 May 2021, Bha
On Wed, 26 May 2021, "Modem, Bhanuprakash" wrote:
>> From: Jani Nikula
>> When you're sending someone else's patches, you need to add your own
>> Signed-off-by here.
>
> Patch 2/2 in this series has a dependency on this patch. And I haven't
> made any changes in this patch, so not added my Signed
> -Original Message-
> From: Souza, Jose
> Sent: Monday, May 24, 2021 2:59 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce
> DMC_FW_MAIN
>
> On Mon, 2021-05-24 at 12:30 -0700, Anusha Srivatsa wrote:
> > This
== Series Details ==
Series: drm/i915: Move LMEM (VRAM) management over to TTM (rev4)
URL : https://patchwork.freedesktop.org/series/90022/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a8d995049a9a drm/i915: Untangle the vma pages_mutex
565669662415 drm/i915: Don't free shared
Hi Ville,
On Tue, 18 May 2021 at 12:17, Ville Syrjälä
wrote:
>
> On Tue, May 18, 2021 at 12:09:56PM +0100, Emil Velikov wrote:
> > Hi Ville,
> >
> > On Mon, 17 May 2021 at 18:24, Ville Syrjälä
> > wrote:
> > >
> > > On Sun, May 16, 2021 at 06:14:32PM +0100, Emil Velikov wrote:
> > > > From: Vive
== Series Details ==
Series: drm/i915: Move LMEM (VRAM) management over to TTM (rev4)
URL : https://patchwork.freedesktop.org/series/90022/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./driver
Media userspace was the last userspace to still use them, and they
converted now too:
https://github.com/intel/media-driver/commit/144020c37770083974bedf59902b70b8f444c799
This means no reason anymore to make relocations faster than they've
been for the first 9 years of gem. This code was added i
== Series Details ==
Series: drm/i915: Move LMEM (VRAM) management over to TTM (rev4)
URL : https://patchwork.freedesktop.org/series/90022/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10135 -> Patchwork_20203
Summary
We check for dmc_payload being there at various points in the driver.
Replace it with the helper.
v2: rebased.
v3: Move intel_dmc to intel_dmc.h in another patch (Lucas)
v4: Remove headers not needed from intel_dmc.h
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De March
Move struct intel_dmc from i915_drv.h to intel_dmc.h.
v2: Add includes along with moving the struct.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.h | 21 +
drivers/gpu/drm/i915/i915_drv.h | 18 +-
2 files changed, 22 inse
Use new format of debug messages across intel_csr.
While at it, change some function definitions which now
need dev_priv for drm_err and drm_info etc.
v2: use container_of() (Jani)
v3: Indentation fixes. (Jani)
Cc: Jani Nikula
Suggested-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Revie
On Tue, May 25, 2021 at 04:17:53PM -0500, Jason Ekstrand wrote:
> This patch is analogous to the previous sync file export patch in that
> it allows you to import a sync_file into a dma-buf. Unlike the previous
> patch, however, this does add genuinely new functionality to dma-buf.
> Without this,
On Tue, May 25, 2021 at 08:54:38AM -0700, Matthew Brost wrote:
> On Tue, May 25, 2021 at 04:27:49PM +0100, Tvrtko Ursulin wrote:
> >
> > On 25/05/2021 14:56, Daniel Vetter wrote:
> > > On Fri, May 21, 2021 at 11:32:12AM -0700, Matthew Brost wrote:
> > > > As discussed in [1] start merging some sup
On Tue, May 25, 2021 at 08:53:42AM -0700, Matthew Brost wrote:
> On Tue, May 25, 2021 at 03:56:56PM +0200, Daniel Vetter wrote:
> > On Fri, May 21, 2021 at 11:32:12AM -0700, Matthew Brost wrote:
> > > As discussed in [1] start merging some support patches as a precursor to
> > > GuC submission the
On 5/26/21 1:32 PM, Thomas Hellström wrote:
From: Maarten Lankhorst
The paltform should exclusively use mmap_offset, one less path to worry
Hmm, Thought this was fixed, but s/paltform/platform/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.
From: Ville Syrjälä
The FIFO underrun recovery mechanism has a boatload of cases
where it can't be used. The description is also a bit ambiguous
as it doesn't specify whether plane downscaling needs to be considered
or just pipe downscaling. We may not even have sufficient state
tracking to decid
From: Ville Syrjälä
Implement Wa_22012358565 to avoid underrun with 32bpp cursor
in some high bandwidth scenarios. The implementation calls for
overriding the arbitration slots for the planes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 4 +++
drivers/gpu/
On 5/26/21 1:32 PM, Thomas Hellström wrote:
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we s
On Wed, May 26, 2021 at 02:25:26PM +0200, Michal Wajdeczko wrote:
>
>
> On 26.05.2021 08:42, Matthew Brost wrote:
> > From: Michal Wajdeczko
> >
> > In upcoming patch we will allow more CTB requests to be sent in
> > parallel to the GuC for processing, so we shouldn't assume any more
> > that G
On Wed, May 26, 2021 at 02:36:18PM +0200, Michal Wajdeczko wrote:
>
>
> On 26.05.2021 08:42, Matthew Brost wrote:
> > Ensure H2G buffer updates are visible before descriptor tail updates by
> > inserting a barrier between the H2G buffer update and the tail. The
> > barrier is simple wmb() for SME
On Wed, May 26, 2021 at 09:57:10AM +0100, Tvrtko Ursulin wrote:
>
> On 25/05/2021 18:21, Matthew Brost wrote:
> > On Tue, May 25, 2021 at 10:21:00AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 06/05/2021 20:13, Matthew Brost wrote:
> > > > Add non blocking CTB send function, intel_guc_send_nb. In
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90583/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20199_full
Summary
--
On Wed, May 26, 2021 at 10:25:13AM +0100, Tvrtko Ursulin wrote:
>
> On 25/05/2021 18:01, Matthew Brost wrote:
> > On Tue, May 25, 2021 at 10:52:01AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 06/05/2021 20:14, Matthew Brost wrote:
> > > > Disable semaphores when using GuC scheduling as semaphore
On Wed, May 26, 2021 at 10:21:05AM +0100, Tvrtko Ursulin wrote:
>
> On 25/05/2021 18:07, Matthew Brost wrote:
> > On Tue, May 25, 2021 at 11:06:00AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 06/05/2021 20:14, Matthew Brost wrote:
> > > > When running the GuC the GPU can't be considered idle if
On Wed, May 26, 2021 at 10:30:27AM +0100, Tvrtko Ursulin wrote:
>
> On 25/05/2021 18:15, Matthew Brost wrote:
> > On Tue, May 25, 2021 at 10:24:09AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 06/05/2021 20:13, Matthew Brost wrote:
> > > > With the introduction of non-blocking CTBs more than one
== Series Details ==
Series: drm/i915/display: relax 2big checking around initial fb (rev2)
URL : https://patchwork.freedesktop.org/series/89863/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10136 -> Patchwork_20204
Summar
== Series Details ==
Series: drm/i915/params: Align visibility of device level and global modparams
(rev2)
URL : https://patchwork.freedesktop.org/series/90588/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2f2ca20ce0cd drm/i915/params: Align visibility of device level and glo
On 5/26/2021 01:40, Tvrtko Ursulin wrote:
On 25/05/2021 18:52, Matthew Brost wrote:
On Tue, May 25, 2021 at 11:16:12AM +0100, Tvrtko Ursulin wrote:
On 06/05/2021 20:14, Matthew Brost wrote:
From: John Harrison
The serial number tracking of engines happens at the backend of
request submissio
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself must be engine
agnostic - any direct register writes must be relative to the engine
and not absolute ad
As discussed in [1] we are breaking that large series into a several
smaller ones. This series is stand alone patch part of step #4 which has
no other dependencies or patches relevant to it.
Taking ownership of the patch in this series from John Harrison per his
request.
Trybot CI [2] looks good,
Hi Daniel,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.13-rc3 next-20210526]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
== Series Details ==
Series: drm/i915/params: Align visibility of device level and global modparams
(rev2)
URL : https://patchwork.freedesktop.org/series/90588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10136 -> Patchwork_20205
== Series Details ==
Series: Adding Wa_14010733141 for SFC reset
URL : https://patchwork.freedesktop.org/series/90587/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20200_full
Summary
---
**FA
Introduce i915_sched_engine object which is lower level data structure
that i915_scheduler / generic code can operate on without touching
execlist specific structures. This allows additional submission backends
to be added without breaking the layering.
This is a bit of detour to integrating the i
As discussed in [1] we are breaking that large series into a several
smaller ones. This series is stand alone patch part of step #4 which has
no other dependencies or patches relevant to it.
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/89844/
Matthew Brost (1):
dr
== Series Details ==
Series: Catchup with a few dropped patches (rev2)
URL : https://patchwork.freedesktop.org/series/90611/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
06eaaa77f454 drm/i915: Take rcu_read_lock for querying fence's driver/timeline
names
699c8e356b0c drm/i915
== Series Details ==
Series: Catchup with a few dropped patches (rev2)
URL : https://patchwork.freedesktop.org/series/90611/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/in
On Wed, 2021-05-26 at 20:35 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The FIFO underrun recovery mechanism has a boatload of cases
> where it can't be used. The description is also a bit ambiguous
> as it doesn't specify whether plane downscaling needs to be considered
> or just pipe
Hi Daniel,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.13-rc3 next-20210526]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
On ADL_P the TBT AUX power wells depend on the PW#2 power well, add the
corresponding power domain dependencies.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_powe
On Thu, May 06, 2021 at 12:13:45PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> Base offset and count of the GuC scratch registers, used for
> sending MMIO messages to GuC, can be initialized earlier with
> other GuC members that also depends on platform.
>
> Signed-off-by: Michal Wa
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90594/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20202_full
Summary
--
On Wed, 2021-05-26 at 20:36 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Implement Wa_22012358565 to avoid underrun with 32bpp cursor
> in some high bandwidth scenarios. The implementation calls for
> overriding the arbitration slots for the planes.
Reviewed-by: José Roberto de Souza
On Thu, May 06, 2021 at 12:13:48PM -0700, Matthew Brost wrote:
> From: Daniele Ceraolo Spurio
>
> GuC has its own defines for the engine classes. They're currently
> mapping 1:1 to the defines used by the driver, but there is no guarantee
> this will continue in the future. Given that we've been
== Series Details ==
Series: Catchup with a few dropped patches (rev2)
URL : https://patchwork.freedesktop.org/series/90611/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20206
Summary
---
**FAILUR
From: Daniele Ceraolo Spurio
GuC has its own defines for the engine classes. They're currently
mapping 1:1 to the defines used by the driver, but there is no guarantee
this will continue in the future. Given that we've been caught off-guard
in the past by similar divergences, we can prepare for t
As discussed in [1] we are breaking that large series into a several
smaller ones. This series includes 2 patches with no other dependencies
and are fully reviewed discussed as part of step #4.
Assuming CI looks good these patches can be merged immediately.
[1] https://patchwork.freedesktop.org/s
From: Michal Wajdeczko
Base offset and count of the GuC scratch registers, used for
sending MMIO messages to GuC, can be initialized earlier with
other GuC members that also depends on platform.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Cc: Daniel
== Series Details ==
Series: series starting with [1/3] drm/i915/ddi: Flush encoder power domain ref
puts during driver unload
URL : https://patchwork.freedesktop.org/series/90613/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20207
== Series Details ==
Series: series starting with [1/3] dma-buf: Require VM_PFNMAP vma for mmap
URL : https://patchwork.freedesktop.org/series/90615/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9b58329fed19 dma-buf: Require VM_PFNMAP vma for mmap
-:34: WARNING:TYPO_SPELLING:
On Wed, 2021-05-26 at 23:34 +0300, Imre Deak wrote:
> On ADL_P the TBT AUX power wells depend on the PW#2 power well, add the
> corresponding power domain dependencies.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c |
== Series Details ==
Series: series starting with [1/3] dma-buf: Require VM_PFNMAP vma for mmap
URL : https://patchwork.freedesktop.org/series/90615/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20208
Su
== Series Details ==
Series: drm/i915: Use generic_access_phys (rev2)
URL : https://patchwork.freedesktop.org/series/90616/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
12c4102fd7e8 drm/i915: Use generic_access_phys
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description
v2: Add struct intel_dmc to intel_dmc.h in a separate
patch
v3: Minor code shuffling and indentation fixes
v4: Checkpatch fixes.
Anusha Srivatsa (3):
drm/i915/dmc: s/DRM_ERROR/drm_err
drm/i915/dmc: Add intel_dmc_has_payload() helper
drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
.../
We check for dmc_payload being there at various points in the driver.
Replace it with the helper.
v2: rebased.
v3: Move intel_dmc to intel_dmc.h in another patch (Lucas)
v4: Remove headers not needed from intel_dmc.h
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De March
Move struct intel_dmc from i915_drv.h to intel_dmc.h.
v2: Add includes along with moving the struct.
Reviewed-by: José Roberto de Souza
Reviewed-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.h | 21 +
drivers/gpu/drm/i915/i91
Use new format of debug messages across intel_csr.
While at it, change some function definitions which now
need dev_priv for drm_err and drm_info etc.
v2: use container_of() (Jani)
v3: Indentation fixes. (Jani)
Cc: Jani Nikula
Suggested-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Revie
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --
Load DMC v2.06 on ADLP. The release notes mention that
this version enables few power savings features.
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a
This series is rebased on top of the new
"Resend More DMC cleanup" series:
https://patchwork.freedesktop.org/series/90635/
Anusha Srivatsa (7):
drm/i915/dmc: s/DRM_ERROR/drm_err
drm/i915/dmc: Add intel_dmc_has_payload() helper
drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
drm/i915/dmc
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc
We check for dmc_payload being there at various points in the driver.
Replace it with the helper.
v2: rebased.
v3: Move intel_dmc to intel_dmc.h in another patch (Lucas)
v4: Remove headers not needed from intel_dmc.h
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De March
Move struct intel_dmc from i915_drv.h to intel_dmc.h.
v2: Add includes along with moving the struct.
Reviewed-by: José Roberto de Souza
Reviewed-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.h | 21 +
drivers/gpu/drm/i915/i91
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anu
Use new format of debug messages across intel_csr.
While at it, change some function definitions which now
need dev_priv for drm_err and drm_info etc.
v2: use container_of() (Jani)
v3: Indentation fixes. (Jani)
Cc: Jani Nikula
Suggested-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Revie
== Series Details ==
Series: drm/i915: Use generic_access_phys (rev2)
URL : https://patchwork.freedesktop.org/series/90616/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20209
Summary
---
**FAILURE
== Series Details ==
Series: drm/i915: Disable gpu relocations
URL : https://patchwork.freedesktop.org/series/90619/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b90d93e39441 drm/i915: Disable gpu relocations
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit descri
== Series Details ==
Series: drm/i915: Disable gpu relocations
URL : https://patchwork.freedesktop.org/series/90619/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20210
Summary
---
**SUCCESS**
N
Add entry for i915 GuC submission / DRM scheduler integration plan.
Follow up patch with details of new parallel submission uAPI to come.
v2:
(Daniel Vetter)
- Expand explaination of why bonding isn't supported for GuC
submission
- CC some of the DRM scheduler maintainers
- Add priority
Add entry for i915 new parallel submission uAPI plan.
v2:
(Daniel Vetter):
- Expand logical order explaination
- Add dummy header
- Only allow N BBs in execbuf IOCTL
- Configure parallel submission per slot not per gem context
v3:
(Marcin Ślusarz):
- Lot's of typos / bad english fixed
Subject and patches say it all.
v2: Address comments, patches have details of changes
v3: Address comments, patches have details of changes
Signed-off-by: Matthew Brost
Matthew Brost (2):
drm/doc/rfc: i915 GuC submission / DRM scheduler
drm/doc/rfc: i915 new parallel submission uAPI plan
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/dmc: s/DRM_ERROR/drm_err
URL : https://patchwork.freedesktop.org/series/90622/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20211
Summa
== Series Details ==
Series: series starting with [1/2] drm/i915/adl_p: Disable FIFO underrun
recovery
URL : https://patchwork.freedesktop.org/series/90623/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ef764ff14f5d drm/i915/adl_p: Disable FIFO underrun recovery
b3b08f413c07 d
On Thu, 27 May 2021 at 02:37, Daniel Vetter wrote:
>
> Media userspace was the last userspace to still use them, and they
> converted now too:
>
> https://github.com/intel/media-driver/commit/144020c37770083974bedf59902b70b8f444c799
>
> This means no reason anymore to make relocations faster than
== Series Details ==
Series: series starting with [1/2] drm/i915/adl_p: Disable FIFO underrun
recovery
URL : https://patchwork.freedesktop.org/series/90623/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20212
== Series Details ==
Series: Engine relative MMIO
URL : https://patchwork.freedesktop.org/series/90627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20213
Summary
---
**SUCCESS**
No regressions
== Series Details ==
Series: Introduce i915_sched_engine object
URL : https://patchwork.freedesktop.org/series/90630/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20214
Summary
---
**SUCCESS**
On 5/26/2021 12:11 PM, Matthew Brost wrote:
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself must be engine
agnostic - any direct register writes m
== Series Details ==
Series: drm/i915/adlp: Add missing TBT AUX -> PW#2 power domain dependencies
URL : https://patchwork.freedesktop.org/series/90631/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20215
== Series Details ==
Series: A couple more prerequisite patches to GuC submission
URL : https://patchwork.freedesktop.org/series/90633/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c0541f4725ff drm/i915/guc: Early initialization of GuC send registers
55e2a1c441b5 drm/i915/guc:
== Series Details ==
Series: drm/i915: Move LMEM (VRAM) management over to TTM (rev4)
URL : https://patchwork.freedesktop.org/series/90022/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10135_full -> Patchwork_20203_full
Su
On 5/25/2021 6:32 AM, Daniel Vetter wrote:
On Mon, May 24, 2021 at 10:48:00PM -0700, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setti
On 5/25/2021 11:36 AM, Tang, CQ wrote:
-Original Message-
From: Intel-gfx On Behalf Of
Daniele Ceraolo Spurio
Sent: Monday, May 24, 2021 10:48 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vetter, Daniel ; Huang Sean Z
; dri-de...@lists.freedesktop.org; Chris Wilson
; Kondapally Kalyan
== Series Details ==
Series: A couple more prerequisite patches to GuC submission
URL : https://patchwork.freedesktop.org/series/90633/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20216
Summary
---
On Wed, May 26, 2021 at 06:34:44PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 5/26/2021 12:11 PM, Matthew Brost wrote:
> > With virtual engines, it is no longer possible to know which specific
> > physical engine a given request will be executed on at the time that
> > request is generated. Th
== Series Details ==
Series: Resend More DMC cleanup
URL : https://patchwork.freedesktop.org/series/90635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10138 -> Patchwork_20217
Summary
---
**SUCCESS**
No regressi
== Series Details ==
Series: Pipe DMC Support (rev3)
URL : https://patchwork.freedesktop.org/series/90445/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4cd719dde218 drm/i915/dmc: s/DRM_ERROR/drm_err
45f377900c6c drm/i915/dmc: Add intel_dmc_has_payload() helper
d03d3a511e95 drm
== Series Details ==
Series: Pipe DMC Support (rev3)
URL : https://patchwork.freedesktop.org/series/90445/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_disp
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