LGTM.
Reviewed-by: Ankit Nautiyal
On 3/24/2021 5:00 PM, Anshuman Gupta wrote:
As documented in HDCP 2.2 DP Errata spec transmitter should abort the
authentication protocol in case transmitter has not received the
entire {AKE_Send_Cert, AKE_Send_H_prime, AKE_Send_Paring_Info} msg
within {110,7,
struct drm_i915_private, struct intel_crtc_state and
struct intel_crtc have been declared before.
Remove the duplicate.
Signed-off-by: Wan Jiabing
---
drivers/gpu/drm/i915/display/intel_crt.h | 1 -
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_vrr.h
On Mon, 22 Mar 2021, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> gcc-11 introdces a harmless warning for cap_inode_getsecurity:
>
> security/commoncap.c: In function ‘cap_inode_getsecurity’:
> security/commoncap.c:440:33: error: ‘memcpy’ reading 16 bytes from a region
> of size 0 [-Werror=s
On Mon, 22 Mar 2021, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> gcc-11 warns that intel_dp_check_mst_status() has a local array of
> fourteen bytes and passes the last four bytes into a function that
> expects a six-byte array:
>
> drivers/gpu/drm/i915/display/intel_dp.c: In function
> ‘inte
On Thu, Mar 25, 2021 at 02:44:14AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Accidentally transposed the arguments to skl_plane_wm_level()
> which is causing us to mistakenly think that the plane watermarks
> have/have not changed when the opposite may be true. Swap the
> arguments so
Hi all,
The latest version of the drm-misc tree consists of just 2 commits on
top of Linus' v5.12-rc1-dontuse tag.
--
Cheers,
Stephen Rothwell
pgp3hJ0faDbsT.pgp
Description: OpenPGP digital signature
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Thank you for offering your valuable advice.
Will send the updated version soon.
> -Original Message-
> From: Alex Williamson
> Sent: Saturday, March 20, 2021 3:27 AM
> To: Gao, Fred
> Cc: k...@vger.kernel.org; intel-gfx@lists.freedesktop.org; Zhenyu Wang
> ; Fonn, Swee Yee
> Subject: R
Before opregion version 2.0 VBT data is stored in opregion mailbox #4,
but when VBT data exceeds 6KB size and cannot be within mailbox #4
then from opregion v2.0+, Extended VBT region, next to opregion is
used to hold the VBT data, so the total size will be opregion size plus
extended VBT region si
On Thu, Mar 25, 2021 at 9:48 AM Stephen Rothwell wrote:
>
> Hi all,
>
> The latest version of the drm-misc tree consists of just 2 commits on
> top of Linus' v5.12-rc1-dontuse tag.
Yeah committer pushed patches to the wrong tree, which meant you get
the wrong tree. We'll fix for tomorrow.
-Daniel
Instead of doing what we do currently, which will never work with
PROVE_LOCKING, do the same as AMD does, and something similar to
relocation slowpath. When all locks are dropped, we acquire the
pages for pinning. When the locks are taken, we transfer those
pages in .get_pages() to the bo. As a fin
Hi Dave and Daniel,
with GT fence revocation runtime PM logic targeting 4.12+ stable,
here goes drm-intel-fixes-2021-03-25-1:
- DisplayPort LTTPR fixes around link training and limiting it
according to supported spec version. (Imre)
- Fix enabled_planes bitmask to really represent only logicall
On Thu, Mar 25, 2021 at 02:44:15AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The dbuf bandwidth calculations don't need the planes to be
> added to the state. Each plane's data rate has already been
> precalculated and stored in the crtc state, and that with
> the dbuf slice usage for
Acked-by: Simon Ser
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Hi Dave, Daniel,
It's still a fairly quiet week, but here's this week's drm-misc-next PR
maxime
drm-misc-next-2021-03-25:
drm-misc-next for 5.13:
UAPI Changes:
- New USB connector type
Cross-subsystem Changes:
Core Changes:
- ttm: Introduce a per-device LRU lock, remove swap LRU
Driver C
dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
despite Wa_14010685332 original sequence thus blocks entry to deeper s0ix state.
The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked
Wa_14010685332 sequence for every PCH since PCH_CNP.
Fixes: b89689
On 24/03/2021 17:18, Jason Ekstrand wrote:
On Wed, Mar 24, 2021 at 6:36 AM Tvrtko Ursulin
wrote:
On 24/03/2021 09:52, Daniel Vetter wrote:
On Wed, Mar 24, 2021 at 09:28:58AM +, Tvrtko Ursulin wrote:
On 23/03/2021 17:51, Jason Ekstrand wrote:
This API is entirely unnecessary and I'd
On Thu, Mar 25, 2021 at 10:48 AM Tvrtko Ursulin
wrote:
>
>
> On 24/03/2021 17:18, Jason Ekstrand wrote:
> > On Wed, Mar 24, 2021 at 6:36 AM Tvrtko Ursulin
> > wrote:
> >>
> >>
> >> On 24/03/2021 09:52, Daniel Vetter wrote:
> >>> On Wed, Mar 24, 2021 at 09:28:58AM +, Tvrtko Ursulin wrote:
> >>
On 3/25/21 10:23 AM, Maarten Lankhorst wrote:
Instead of doing what we do currently, which will never work with
PROVE_LOCKING, do the same as AMD does, and something similar to
relocation slowpath. When all locks are dropped, we acquire the
pages for pinning. When the locks are taken, we transf
On Thu, Mar 25, 2021 at 03:02:13PM +0530, Anshuman Gupta wrote:
> dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
> despite Wa_14010685332 original sequence thus blocks entry to deeper s0ix
> state.
>
> The Tweaked Wa_14010685332 sequence fixes this issue, therefore use
On Thu, Mar 25, 2021 at 10:55:11AM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/25/21 10:23 AM, Maarten Lankhorst wrote:
> > Instead of doing what we do currently, which will never work with
> > PROVE_LOCKING, do the same as AMD does, and something similar to
> > relocation slowpath. When all l
On Thu, Mar 25, 2021 at 11:35:53AM +0200, Lisovskiy, Stanislav wrote:
> On Thu, Mar 25, 2021 at 02:44:15AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The dbuf bandwidth calculations don't need the planes to be
> > added to the state. Each plane's data rate has already been
> > pr
drm-misc-fixes-2021-03-25:
drm-misc-fixes for v5.12:
- Use FOLL_FORCE and FOLL_LONGTERM in etnaviv
The following changes since commit 6909115442759efef3d4bc5d9c54d7943f1afc14:
drm/omap: dsi: fix unsigned expression compared with zero (2021-03-17
13:59:23 +0200)
are available in the Git reposit
After the recently added commit fe0f1e3bfdfe ("drm/i915: Shut down
displays gracefully on reboot"), the DSI panel on a Cherry Trail based
Predia Basic tablet would no longer properly light up after reboot.
I've managed to reproduce this without rebooting by doing:
chvt 3; echo 1 > /sys/class/graph
Instead of sleeping panel_pwr_cycle_delay ms when turning the panel off,
record the time it is turned off and if necessary wait any (remaining)
time when the panel is turned on again.
Also sleep the remaining time on shutdown, because on reboot the
GOP will immediately turn on the panel again.
Cc
dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
despite Wa_14010685332 original sequence, thus blocks entry to deeper s0ix
state.
The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked
Wa_14010685332 sequence for every PCH since PCH_CNP.
v2:
- remov
On Thu, Mar 25, 2021 at 05:39:47PM +0530, Anshuman Gupta wrote:
> dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
> despite Wa_14010685332 original sequence, thus blocks entry to deeper s0ix
> state.
>
> The Tweaked Wa_14010685332 sequence fixes this issue, therefore use
On Wed, 24 Mar 2021, Anshuman Gupta wrote:
> HDCP DP 2.2 errata is part of HDCP DP 2.3 specs
> as well.
>
> Anshuman Gupta (2):
> drm/i915/hdcp: Add DP HDCP2.2 timeout to read entire msg
> drm/hdcp: DP HDCP2.2 errata LC_Send_L_Prime=16
>
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 45 ++
On Thu, Mar 25, 2021 at 9:05 AM Jani Nikula wrote:
> > Clearly something is wrong here, but I can't quite figure out what.
> > Changing the array size to 16 bytes avoids the warning, but is
> > probably the wrong solution here.
>
> Ugh. drm_dp_channel_eq_ok() does not actually require more than
>
On 3/25/21 3:53 AM, Arnd Bergmann wrote:
On Thu, Mar 25, 2021 at 9:05 AM Jani Nikula wrote:
Clearly something is wrong here, but I can't quite figure out what.
Changing the array size to 16 bytes avoids the warning, but is
probably the wrong solution here.
Ugh. drm_dp_channel_eq_ok() does not
== Series Details ==
Series: drm/i915: missing workarounds and refactors
URL : https://patchwork.freedesktop.org/series/88408/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter
or member '
== Series Details ==
Series: drm/i915: missing workarounds and refactors
URL : https://patchwork.freedesktop.org/series/88408/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9894 -> Patchwork_19849
Summary
---
**FAILU
XE_LPD brings enhanced underrun recovery: the hardware can somewhat
mitigate underruns by using an interpolated replacement pixel (soft
underrun) or the previous pixel (hard underrun). Furthermore, underruns
can now be caused downstream by the port, even if the pipe itself is
operating properly.
Let's start preparing for upcoming platforms that will use an XE_LPD
design.
v2:
- Use the now-preferred "XE_LPD" term to refer to this design
- Utilize DISPLAY_VER() rather than a feature flag
- Drop unused mbus_size field (Lucas)
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.
The previous version of this series was here:
https://lists.freedesktop.org/archives/intel-gfx/2021-March/262168.html
The preparation patches that convert display/ to use DISPLAY_VER()
instead of INTEL_GEN() have landed on drm-tip now, so this is mostly
just a straightforward rebase of the
The DDI naming template for display version 12 went A-C, TC1-TC6. With
XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
The XE_LPD design keeps the register offsets and bitfields relating to
the TC outputs in the same location they were previously. The new "D"
and "E" output
From: Juha-Pekka Heikkilä
XE_LPD supports plane strides up to 128KB.
v2:
- Drop a duplicated comment
- Add missing horizontal pixels for cpp!=8 case (Lucas)
- Take into account larger possible offsets for warnings
Cc: Vandita Kulkarni
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Matt
XE_LPD continues to use the same "skylake-style" watermark
programming as other recent platforms. The only change to the watermark
calculations compared to Display12 is that XE_LPD now allows a
maximum of 255 lines vs the old limit of 31.
Due to the larger possible lines value, the corresponding
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
XE_LPD's plane support is identical to RKL and ADL-S --- 5 universal + 1
cursor with NV12 UV support on planes 1-3 and NV12 Y support on planes
4-5.
v2:
- Drop the extra 90/270 rotation check in skl_plane_check_fb(); the DRM
property code will already prevent userspace from passing us values
From: Vandita Kulkarni
Add methods to calculate rc parameters for all bpps, against the fixed
arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
formats. Our hw doesn't support YUV compression yet. The calculations
used here are from VESA C model for DSC 1.1
v2:
- Checkp
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.
While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.
v2:
- Maintain bit order rather than logical order. (Luca
From: Vandita Kulkarni
We need slice height to calculate few RC parameters
hence assign slice height first.
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
d
From: Clinton Taylor
Add ADL-P to the device_info table and support MACROS.
Bspec: 49185, 55372, 55373
Cc: Matt Atwood
Cc: Matt Roper
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
If VT-d is active, the memory bandwidth usage of the display is 5%
higher. Take this into account when determining whether we can support
a display configuration.
Bspec: 64631
Cc: Matt Atwood
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_bw.c |
From: Vandita Kulkarni
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1
v2:
- Add include guard to header (Jani)
- Move the big tables to a .c file (Chris, Jani, Lucas)
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/displa
From: Clinton Taylor
Add 18 known PCI device IDs
Bspec: 55376
Cc: Caz Yokoyama
Cc: Matt Atwood
Cc: Matt Roper
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
include/drm/i915_pciids.h | 21 +
1 file changed, 21 insertions(+)
di
From: Clinton Taylor
Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we
would assign the DDC pin map based on the PCH, but it can also change
based on the CPU. From Bspec 20124: "The physical port to pin pair
mapping are defined in the Bspec per PCH. Mapping can further change
From: Vandita Kulkarni
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
1 file changed, 10 insertions(+), 10
From: Uma Shankar
Enable LPSP for XE_LPD and get the proper power well
enable check in place. For XE_LPD it is PW2 which
need to check for LPSP.
v2:
- Move the XE_LPD check outside of the switch. (Lucas)
Cc: Anshuman Gupta
Cc: Animesh Manna
Cc: Matt Roper
Cc: Lucas De Marchi
Suggested-by:
From: Manasi Navare
On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield
replacing the pipeline full and deprecating the pipeline override
bit.
This patch adds this corresponding bitfield in the register defs,
crtc state vrr structure and populates this in vrr compute
config and vrr ena
XE_LPD reduces the number of regular watermark latency levels from 8
to 6 on non-dgfx platforms. However the hardware also adds a special
purpose SAGV wateramrk (and an accompanying transition watermark) that
will be used by the hardware in place of the level 0 values during SAGV
transitions.
Bsp
ADL-P further extends the bits in PLANE_WM that represent blocks and
lines; we need to extend our masks accordingly. Since these bits are
reserved and MBZ on earlier platforms, it's safe to use the larger
bitmask on all platforms.
Bspec: 50419
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-of
From: Anusha Srivatsa
Load DMC v2.08 on ADLP. The release notes mention that
this version enables few power savings features.
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_c
From: Vandita Kulkarni
Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 +
From: Vandita Kulkarni
On adlp the two mbuses have two display pipes and
two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
Mbus2. The Mbus can be joined and all the DBUFS can be
used on Pipe A or B.
Bspec: 49255
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton Tayl
From: Anusha Srivatsa
Most of the context WA are already implemented for previous platforms.
Adding adl_p platform tag to reflect so.
BSpec: 54369
Cc: Matt Roper
Cc: Aditya Swarup
Cc: Madhumitha Tolakanahalli Pradeep
Cc: Radhakrishna Sripada
Cc: José Roberto de Souza
Cc: Swathi Dhanavanthr
From: Animesh Manna
No need for checking dsc flag for uncompressed pipe joiner mode
validation.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
1 file changed, 5 insertions(+), 2
From: José Roberto de Souza
Alderlake-P don't have programing sequences for MBUS or DBUF during
display initializaiton, instead it requires programing to those
registers during modeset because it to depend on the pipes left
enabled.
Bspec: 49213
Cc: Matt Roper
Signed-off-by: José Roberto de Sou
From: Clint Taylor
Initial GuC/HuC definitions for ADL_P
Cc: Anusha Srivatsa
Cc: Matt Roper
Signed-off-by: Clint Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/driv
From: José Roberto de Souza
Implementation details are in the HSD 22011320316, requiring CD clock
to be at least 307MHz to make DC states to work.
Cc: Matt Roper
Cc: Anusha Srivatsa
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu
From: Anusha Srivatsa
ADL-P has 3 possible refclk frequencies: 19.2MHz,
24MHz and 38.4MHz
BSpec: 55409, 49208
Cc: Matt Roper
Cc: Clinton Taylor
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display
From: Anusha Srivatsa
The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4.
The first two are connected to combo phys while
the rest are connected to TC phys.
Cc: Matt Roper
Cc: Clinton Taylor
Cc: Lucas De Marchi
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Tay
From: Vandita Kulkarni
Update MBUS_CTL register if the 2 mbus can be joined as per the current
DDB allocation and active pipes, also update hashing mode and pipe
select bits as per the sequence mentioned in the bspec.
Cc: Stanislav Lisovskiy
Cc: José Roberto de Souza
Signed-off-by: Vandita Ku
From: Animesh Manna
Respective bit for master or slave to be set for uncompressed
bigjoiner in dss_ctl1 register.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++
drivers/gpu/drm
From: José Roberto de Souza
When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display
has the control over the TC phy.
The "not safe" naming is confusing using ownership make it easier
to read also future platforms will have a new register that does the
same job as DP_PHY_MODE_STATUS_NOT_SAF
From: José Roberto de Souza
On ADL-P TC cold is exited and blocked when legacy aux is powered,
that is exacly the same of what ICL need for static TC ports.
TODO: When a TBT hub or monitor is connected it will cause TBT and
legacy aux to be powered at the same time, hopefully this will not
cause
From: Anusha Srivatsa
ADL_P has same memory characteristics as ADL_S platform.
Bspec: 64631
Cc: José Roberto de Souza
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed,
From: José Roberto de Souza
Buffer compression is not usable in A stepping.
Cc: Matt Roper
Cc: Anusha Srivatsa
Cc: Clinton A Taylor
Cc: Juha-Pekka Heikkilä
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
.../d
From: Mika Kahola
Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.
BSpec: 54956
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++-
.../drm/i915/display/i
From: Ville Syrjälä
The dbuf slices are going to be split across several MBUS units.
The actual dbuf programming will use offsets relative to the
MBUS unit. To accomodate that we shall store the MBUS relative
offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[].
For crtc_state->wm.skl
From: Mika Kahola
Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz.
For all other modes, we can enable loadgen sharing feature.
BSpec: 55359
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/
From: José Roberto de Souza
Implements changes around PSR for alderlake-P:
- EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
- Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
removed setting SU_REGION_START/END_ADDR will do this job
- SU_REGION_START/END_A
From: José Roberto de Souza
ADL-P have basically the same TC connection and disconnection
sequences as ICL and TGL, the major difference is the new registers.
So here adding functions without the icl prefix in the name and
making the new functions call the platform specific function to access
th
From: Ville Syrjälä
Move intel_modeset_all_pipes() to a central place so that we can
use it elsewhere as well. No functional changes.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c
From: José Roberto de Souza
Adding a new hook to ADL-P just to avoid another platform check in
gen12lp_init_clock_gating() but also open to it.
BSpec: 54369
Cc: Matt Roper
Cc: Anusha Srivatsa
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
d
From: Animesh Manna
For uncompressed big joiner DSC engine will not be used so will avoid
compute config of DSC.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 6
From: Anusha Srivatsa
When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.
Cc: Matt Roper
Cc: Clint Taylor
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
From: Anusha Srivatsa
The clocks in ALD_P is similar to that of TGL.
The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL.
This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to intel_combo_pll_enable_reg() for being lookup
place for PLL_ENABLE register in combo phy c
From: José Roberto de Souza
Alderlake P have modular FIA like TGL but it is always modular in all
skus, not like TGL that we had to read a register to check if it is
monolithic or modular.
BSpec: 55480
BSpec: 50572
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylo
From: Umesh Nerlige Ramappa
Enable relevant OA formats for ADL_P.
Cc: Ashutosh Dixit
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --g
From: Mika Kahola
Today when the DSI controller is paired with the Combo-PHY it
uses the high-speed (HS) Word clock for its low power (LP)
transmit PPI communication to the DPHY. The interface signaling
only changes state at an Escape clock frequency (i.e. its
effectively running on a virtual Tx
== Series Details ==
Series: series starting with [1/2] drm/i915: add gem/gt TODO
URL : https://patchwork.freedesktop.org/series/88413/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
591bc42605c7 drm/i915: add gem/gt TODO
-:41: WARNING:FILE_PATH_CHANGES: added, moved or deleted
== Series Details ==
Series: series starting with [1/2] drm/i915: add gem/gt TODO
URL : https://patchwork.freedesktop.org/series/88413/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter
or
== Series Details ==
Series: series starting with [1/2] drm/i915: add gem/gt TODO
URL : https://patchwork.freedesktop.org/series/88413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9895 -> Patchwork_19850
Summary
---
Seems it has been overlooked during mesonification.
It's a shared module that's meant to be LD_PRELOAD-ed to intercept
EXECBUFFER2 calls for the purpose of replaying them later.
Signed-off-by: Arkadiusz Hiler
---
benchmarks/meson.build | 8
1 file changed, 8 insertions(+)
diff --git a
Signed-off-by: Arkadiusz Hiler
---
.gitlab-ci.yml | 18 --
Dockerfile.build-debian | 8
2 files changed, 26 deletions(-)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e226d9d7..2b03fc98 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -154,17 +154,6 @@
Autotools have been deprecated in favor of Meson since early 2019.
Cc: Daniel Vetter
Cc: Petri Latvala
Cc: Tomi Sarvela
Signed-off-by: Arkadiusz Hiler
---
Makefile.am | 44 ---
autogen.sh | 17 -
benchmarks/Makefile.am | 28 --
benchmark
It's not a even a proper test.
Suggested-by: Petri Latvala
Signed-off-by: Arkadiusz Hiler
---
tests/Makefile.sources | 4 --
tests/ddx_intel_after_fbdev | 73 -
2 files changed, 77 deletions(-)
delete mode 100755 tests/ddx_intel_after_fbdev
diff --git
...and add it to test-list-full.txt just like we do when building with
autotools.
Signed-off-by: Arkadiusz Hiler
---
tests/meson.build | 13 +
1 file changed, 13 insertions(+)
diff --git a/tests/meson.build b/tests/meson.build
index 54a1a3c7..8e3cd390 100644
--- a/tests/meson.build
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix transposed arguments to
skl_plane_wm_level()
URL : https://patchwork.freedesktop.org/series/88420/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:10
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix transposed arguments to
skl_plane_wm_level()
URL : https://patchwork.freedesktop.org/series/88420/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9895 -> Patchwork_19851
=
As part of the System Managemenent Interface (SMI), use the HWMON
subsystem to display power utilization.
The following standard HWMON power sensors are currently supported
(and appropriately scaled):
/sys/class/drm/card0/device/hwmon/hwmon
- energy1_input
- power1_cap
-
== Series Details ==
Series: drivers: gpu: drm: Remove repeated declaration
URL : https://patchwork.freedesktop.org/series/88431/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter
or membe
On Mon, 2021-03-08 at 15:56 +0200, Jani Nikula wrote:
> Add new runtime info field for stepping. Add new helpers for accessing
> them. As we'll be switching platforms over to the new scheme
> incrementally, check for non-initialized steppings.
>
> In case a platform does not have separate display
On Mon, 2021-03-08 at 15:56 +0200, Jani Nikula wrote:
> Add new symbolic names for revision ids, and convert KBL revids to use
> them via the new stepping check macros.
>
> This also fixes theoretical out of bounds access to kbl_revids array.
>
> v2: Rename stepping->step
>
> Signed-off-by: Jani
== Series Details ==
Series: drivers: gpu: drm: Remove repeated declaration
URL : https://patchwork.freedesktop.org/series/88431/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9895 -> Patchwork_19852
Summary
---
**SU
On Mon, 2021-03-08 at 15:56 +0200, Jani Nikula wrote:
> This changes the way revids not present in the array are handled:
>
> - For gaps in the array, the next present revid is used.
>
> - For revids beyond the array, the new STEP_FUTURE is used instead of
> the last revid in the array.
>
> In
On Mon, 2021-03-08 at 15:56 +0200, Jani Nikula wrote:
> Matter of taste. Match the prefix for everything else related to
> steppings. No functional changes.
Reviewed-by: José Roberto de Souza
For the renaming patches, 6, 7 and 8 I'm also fine with the current naming up
to you.
>
> Signed-off-
The changes looks good but can you resend changing the commit message to:
"drm/i915: Remove repeated declaration"?
To better match with i915 patches.
With this change you can add
Reviewed-by: José Roberto de Souza
On Thu, 2021-03-25 at 13:00 +0800, Wan Jiabing wrote:
> struct drm_i915_private,
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