[Intel-gfx] [RFC PATCH 2/2] drm/i915/dp: Retry AUX requests 7 times.

Given that intel_dp_aux_xfer retries 5 times, so configure drm_dpcd_access to retry only 7 times, which means the max number of retries for i915 = 7 * 5 = 35 times. Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 ++ 1 file changed, 2 insertions(+) diff --

[Intel-gfx] [RFC PATCH 1/2] drm/dp: Make number of AUX retries configurable by display drivers.

The number of AUX retries specified in the DP specs is 7. Currently, to make Dell 4k monitors happier, the number of retries are 32. i915 also retries 5 times (intel_dp_aux_xfer) which means in the case of AUX timeout we actually retries 32 * 5 = 160 times. So making the number of aux retires a

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Add a check for object size for corner cases

== Series Details == Series: drm/i915/gem: Add a check for object size for corner cases URL : https://patchwork.freedesktop.org/series/86934/ State : success == Summary == CI Bug Log - changes from CI_DRM_9755 -> Patchwork_19648 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RFC,1/2] drm/dp: Make number of AUX retries configurable by display drivers.

== Series Details == Series: series starting with [RFC,1/2] drm/dp: Make number of AUX retries configurable by display drivers. URL : https://patchwork.freedesktop.org/series/86937/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9b605e7f6e6f drm/dp: Make number of AUX retries c

Re: [Intel-gfx] [RFC PATCH 1/2] drm/dp: Make number of AUX retries configurable by display drivers.

Hi Am 10.02.21 um 09:33 schrieb Khaled Almahallawy: The number of AUX retries specified in the DP specs is 7. Currently, to make Dell 4k monitors happier, the number of retries are 32. i915 also retries 5 times (intel_dp_aux_xfer) which means in the case of AUX timeout we actually retries 32 *

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [RFC,1/2] drm/dp: Make number of AUX retries configurable by display drivers.

== Series Details == Series: series starting with [RFC,1/2] drm/dp: Make number of AUX retries configurable by display drivers. URL : https://patchwork.freedesktop.org/series/86937/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each co

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [RFC,1/2] drm/dp: Make number of AUX retries configurable by display drivers.

== Series Details == Series: series starting with [RFC,1/2] drm/dp: Make number of AUX retries configurable by display drivers. URL : https://patchwork.freedesktop.org/series/86937/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9755 -> Patchwork_19649

[Intel-gfx] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

From: Tvrtko Ursulin Implement a default view where clients are aggregated by their PID. Toggled by pressing 'H' similar to top(1). Signed-off-by: Tvrtko Ursulin --- man/intel_gpu_top.rst | 1 + tools/intel_gpu_top.c | 109 +- 2 files changed, 97 inse

[Intel-gfx] [PATCH i-g-t 1/3] intel_gpu_top: Wrap interactive header

From: Tvrtko Ursulin Slight improvement with regards to wrapping header components to fit console width. If a single element is wider than max it can still overflow but it should now work better for practical console widths. Signed-off-by: Tvrtko Ursulin --- tools/intel_gpu_top.c | 81

[Intel-gfx] [PATCH i-g-t 3/3] intel_gpu_top: Interactive help screen

From: Tvrtko Ursulin Show a list of supported interactive commands when pressing 'h'. Signed-off-by: Tvrtko Ursulin --- man/intel_gpu_top.rst | 1 + tools/intel_gpu_top.c | 68 ++- 2 files changed, 61 insertions(+), 8 deletions(-) diff --git a/man/inte

[Intel-gfx] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

From: Tvrtko Ursulin Implement a default view where clients are aggregated by their PID. Toggled by pressing 'H' similar to top(1). v2: * Fix memory leak. Signed-off-by: Tvrtko Ursulin --- man/intel_gpu_top.rst | 1 + tools/intel_gpu_top.c | 121 +-

[Intel-gfx] [PATCH] drm/i915: Check for scratch page scribbling

Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson --- .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 31

[Intel-gfx] [PATCH] drm/i915: Check for scratch page scribbling

Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson --- .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 31

Re: [Intel-gfx] [RFC PATCH 1/2] drm/dp: Make number of AUX retries configurable by display drivers.

On Wed, 2021-02-10 at 09:55 +0100, Thomas Zimmermann wrote: > Hi > > Am 10.02.21 um 09:33 schrieb Khaled Almahallawy: > > The number of AUX retries specified in the DP specs is 7. > > Currently, to make Dell 4k monitors happier, the number of retries > > are 32. > > i915 also retries 5 times (inte

[Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling

Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson --- .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 31

[Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address

The surface_state_base is an offset into the batch, so we need to pass the correct batch address for STATE_BASE_ADDRESS. Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Prathap Kumar Valsan Cc: Akeem G Abodunrin --- dr

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

Quoting Tvrtko Ursulin (2021-02-10 09:37:55) > +static struct clients *aggregated_clients(struct clients *clients) > +{ > + struct client *ac, *c, *cp = NULL; > + struct clients *aggregated; > + int tmp, num = 0; > + > + /* Sort by pid first to make it easy to aggregate whil

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 3/3] intel_gpu_top: Interactive help screen

Quoting Tvrtko Ursulin (2021-02-10 09:37:56) > From: Tvrtko Ursulin > > Show a list of supported interactive commands when pressing 'h'. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.fre

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

Hi, On 2/10/21 12:07 AM, Chris Wilson wrote: > Quoting Hans de Goede (2021-02-09 11:46:46) >> Hi, >> >> On 2/9/21 12:27 AM, Chris Wilson wrote: >>> Quoting Hans de Goede (2021-02-08 20:38:58) Hi All, We (Fedora) have been receiving reports from multiple users about gfx issues

Re: [Intel-gfx] [PATCH i-g-t 1/3] intel_gpu_top: Wrap interactive header

Quoting Tvrtko Ursulin (2021-02-10 09:37:54) > From: Tvrtko Ursulin > > Slight improvement with regards to wrapping header components to fit > console width. If a single element is wider than max it can still > overflow but it should now work better for practical console widths. I'm not fond of

Re: [Intel-gfx] [PATCH] drm/i915/gem: Add a check for object size for corner cases

Quoting Anand Moon (2021-02-10 07:59:29) > Add check for object size to return appropriate error -E2BIG or -EINVAL > to avoid WARM_ON and sucessfull return for some testcase. No. You miss the point of having those warnings. We need to inspect the code to remove the last remaining "int pagenum", an

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling

Chris Wilson writes: > Periodically check, for example when idling and upon closing user > contexts, whether or not some client has written into unallocated PTE in > their ppGTT. > > Signed-off-by: Chris Wilson > --- > .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++-- > drivers/gpu/

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address

Chris Wilson writes: > The surface_state_base is an offset into the batch, so we need to pass > the correct batch address for STATE_BASE_ADDRESS. > > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Prathap Kumar Va

[Intel-gfx] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

From: Tvrtko Ursulin Implement a default view where clients are aggregated by their PID. Toggled by pressing 'H' similar to top(1). v2: * Fix memory leak. v3: * Do not allow sort by client id in aggregated mode. * Tweak sort criteria and sorting decisions. (Chris) Signed-off-by: Tvrtko Urs

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

On 10/02/2021 10:35, Chris Wilson wrote: Quoting Tvrtko Ursulin (2021-02-10 09:37:55) +static struct clients *aggregated_clients(struct clients *clients) +{ + struct client *ac, *c, *cp = NULL; + struct clients *aggregated; + int tmp, num = 0; + + /* Sort by pid first t

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

Quoting Tvrtko Ursulin (2021-02-10 10:55:44) > > On 10/02/2021 10:35, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2021-02-10 09:37:55) > > Ok, that works very well. Hmm. The sort order does seem a little jumpy > > though. May I suggest ac->id = -c->pid; instead of num; > > Done it although I

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Add a check for object size for corner cases

== Series Details == Series: drm/i915/gem: Add a check for object size for corner cases URL : https://patchwork.freedesktop.org/series/86934/ State : success == Summary == CI Bug Log - changes from CI_DRM_9755_full -> Patchwork_19648_full S

Re: [Intel-gfx] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

Quoting Tvrtko Ursulin (2021-02-10 10:53:43) > +static struct clients *display_clients(struct clients *clients) > +{ > + struct client *ac, *c, *cp = NULL; > + struct clients *aggregated; > + int tmp, num = 0; > + > + if (!aggregate_pids) > + return sort_client

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling

Quoting Mika Kuoppala (2021-02-10 10:49:55) > Chris Wilson writes: > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c > > b/drivers/gpu/drm/i915/gt/intel_gtt.c > > index d34770ae4c9a..5ac9eb4a3a92 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c

[Intel-gfx] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

From: Tvrtko Ursulin Implement a default view where clients are aggregated by their PID. Toggled by pressing 'H' similar to top(1). v2: * Fix memory leak. v3: * Do not allow sort by client id in aggregated mode. * Tweak sort criteria and sorting decisions. (Chris) v4: * More tweaks to cod

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Check for scratch page scribbling (rev2)

== Series Details == Series: drm/i915: Check for scratch page scribbling (rev2) URL : https://patchwork.freedesktop.org/series/86939/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.

Re: [Intel-gfx] [PATCH] drm/vblank: Document drm_crtc_vblank_restore constraints

On Tue, Feb 09, 2021 at 05:36:07PM +0200, Ville Syrjälä wrote: > On Tue, Feb 09, 2021 at 11:15:23AM +0100, Daniel Vetter wrote: > > I got real badly confused when trying to review a fix from Ville for > > this. Let's try to document better what's required for this, and check > > the minimal setting

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Check for scratch page scribbling

== Series Details == Series: series starting with [1/2] drm/i915: Check for scratch page scribbling URL : https://patchwork.freedesktop.org/series/86940/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separat

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling

Chris Wilson writes: > Quoting Mika Kuoppala (2021-02-10 10:49:55) >> Chris Wilson writes: >> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c >> > b/drivers/gpu/drm/i915/gt/intel_gtt.c >> > index d34770ae4c9a..5ac9eb4a3a92 100644 >> > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c >> > +++ b/driv

[Intel-gfx] [PATCH] drm/i915/adl_s: Add gmbus pin mapping

Add table to map the GMBUS pin pairs to GPIO registers and port to DDC mapping for ADL_S as per below Bspec. Bspec:20124, 53597. Cc: Aditya Swarup Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Anand Moon --- drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++-- 1 file changed

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Disallow plane x+w>stride on ilk+ with X-tiling

On 9.2.2021 17.21, Ville Syrjälä wrote: On Tue, Feb 09, 2021 at 09:22:09AM +, Chris Wilson wrote: Quoting Ville Syrjala (2021-02-09 02:19:16) From: Ville Syrjälä ilk+ planes get notably unhappy when the plane x+w exceeds the stride. This wasn't a problem previously because we always align

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Check for scratch page scribbling

== Series Details == Series: series starting with [1/2] drm/i915: Check for scratch page scribbling URL : https://patchwork.freedesktop.org/series/86940/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9757 -> Patchwork_19651

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address

Quoting Mika Kuoppala (2021-02-10 10:50:18) > Chris Wilson writes: > > > The surface_state_base is an offset into the batch, so we need to pass > > the correct batch address for STATE_BASE_ADDRESS. > > > > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > > Signed-off-by:

[Intel-gfx] [CI] drm/i915/gt: Correct surface base address for renderclear

The surface_state_base is an offset into the batch, so we need to pass the correct batch address for STATE_BASE_ADDRESS. Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Prathap Kumar Valsan Cc: Akeem G Abodunrin Cc: Han

Re: [Intel-gfx] [RFC PATCH 8/9] drm/gem: Associate GEM objects with drm cgroup

On Wed, Feb 10, 2021 at 08:52:29AM +0100, Thomas Zimmermann wrote: > Hi > > Am 09.02.21 um 11:54 schrieb Daniel Vetter: > > *: vmwgfx is the only non-gem driver, but there's plans to move at least > > vmwgfx internals (maybe not the uapi, we'll see) over to gem. Once that's > > done it's truly all

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

Quoting Hans de Goede (2021-02-10 10:37:19) > Hi, > > On 2/10/21 12:07 AM, Chris Wilson wrote: > > Quoting Hans de Goede (2021-02-09 11:46:46) > >> Hi, > >> > >> On 2/9/21 12:27 AM, Chris Wilson wrote: > >>> Quoting Hans de Goede (2021-02-08 20:38:58) > Hi All, > > We (Fedora) have

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_s: Add gmbus pin mapping

== Series Details == Series: drm/i915/adl_s: Add gmbus pin mapping URL : https://patchwork.freedesktop.org/series/86944/ State : success == Summary == CI Bug Log - changes from CI_DRM_9757 -> Patchwork_19652 Summary --- **SUCCESS**

Re: [Intel-gfx] [PATCH] Revert "drm/atomic: document and enforce rules around "spurious" EBUSY"

On Tue, Feb 09, 2021 at 04:14:01PM -0800, Manasi Navare wrote: > This reverts commit fb6473a48b635c55d04eb94e579eede52ef39550. > > These additional checks added to avoid EBUSY give unnecessary WARN_ON > in case of big joiner used in i915 in which case even if the modeset > is requested on a single

Re: [Intel-gfx] [PATCH] Revert "drm/atomic: document and enforce rules around "spurious" EBUSY"

On Wednesday, February 10th, 2021 at 2:16 PM, Daniel Vetter wrote: > On Tue, Feb 09, 2021 at 04:14:01PM -0800, Manasi Navare wrote: > > > These additional checks added to avoid EBUSY give unnecessary WARN_ON > > in case of big joiner used in i915 in which case even if the modeset > > is requeste

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Correct surface base address for renderclear

== Series Details == Series: drm/i915/gt: Correct surface base address for renderclear URL : https://patchwork.freedesktop.org/series/86947/ State : success == Summary == CI Bug Log - changes from CI_DRM_9757 -> Patchwork_19653 Summary

[Intel-gfx] [PULL] drm-misc-fixes

Hi Dave and Daniel, here's this week's PR for drm-misc-fixes. There's a buffer overflow in vc4 and a memory leak in xlnx. The rest appear to be mere bug fixes. Best regards Thomas drm-misc-fixes-2021-02-10: * dp_mst: Don't report un-attached ports as connected * sun4i: tcon1 sync polarity fix;

Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree

Op 2021-02-10 om 04:11 schreef Stephen Rothwell: > Hi all, > > After merging the drm-misc tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > > drivers/gpu/drm/v3d/v3d_sched.c:263:1: error: return type is an incomplete > type > 263 | v3d_gpu_reset_for_timeout(struct v3d_de

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Add DDR5 and LPDDR5 BW buddy page entries

On Tue, 2021-02-09 at 22:22 +, Patchwork wrote: Patch Details Series: drm/i915/display: Add DDR5 and LPDDR5 BW buddy page entries URL:https://patchwork.freedesktop.org/series/86908/ State: success Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19643/index.html CI Bug L

Re: [Intel-gfx] [PATCH] Revert "drm/atomic: document and enforce rules around "spurious" EBUSY"

On Wed, Feb 10, 2021 at 01:38:45PM +, Simon Ser wrote: > On Wednesday, February 10th, 2021 at 2:16 PM, Daniel Vetter > wrote: > > > On Tue, Feb 09, 2021 at 04:14:01PM -0800, Manasi Navare wrote: > > > > > These additional checks added to avoid EBUSY give unnecessary WARN_ON > > > in case of

Re: [Intel-gfx] [PATCH] drm/i915/adl_s: Add gmbus pin mapping

On 2/10/21 3:54 AM, Anand Moon wrote: > Add table to map the GMBUS pin pairs to GPIO registers and port to DDC > mapping for ADL_S as per below Bspec. Has this patch been tested on an ADLS system? Upstream CI AFAIK doesn't have support for ADL-S. Also comments below.. > > Bspec:20124, 53597. >

Re: [Intel-gfx] [PATCH] drm/i915/vbt: update DP max link rate table

On Mon, Feb 08, 2021 at 01:31:57PM +, Lee, Shawn C wrote: > On Fri, Feb 05, 2021, at 8:26 p.m, Ville Syrjälä wrote: > >On Mon, Feb 01, 2021 at 11:02:28PM +0800, Lee Shawn C wrote: > >> According to Bspec #20124, max link rate table for DP was updated at > >> BDB version 230. Max link rate can

Re: [Intel-gfx] [RFC PATCH 1/2] drm/dp: Make number of AUX retries configurable by display drivers.

On Wed, 2021-02-10 at 00:33 -0800, Khaled Almahallawy wrote: > The number of AUX retries specified in the DP specs is 7. Currently, to make > Dell 4k monitors happier, the number of retries are 32. > i915 also retries 5 times (intel_dp_aux_xfer) which means in the case of AUX > timeout we actually

[Intel-gfx] [PATCH] i915/perf: Drop the check for report reason in OA

After fixing the OA_TAIL_PTR corruption, there are no more reports with reason field of zero. Drop the check for report reason. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_perf.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/dri

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/perf: Drop the check for report reason in OA (rev2)

== Series Details == Series: i915/perf: Drop the check for report reason in OA (rev2) URL : https://patchwork.freedesktop.org/series/84478/ State : success == Summary == CI Bug Log - changes from CI_DRM_9760 -> Patchwork_19654 Summary -

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adl_s: Add gmbus pin mapping

== Series Details == Series: drm/i915/adl_s: Add gmbus pin mapping URL : https://patchwork.freedesktop.org/series/86944/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9757_full -> Patchwork_19652_full Summary --- **F

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Correct surface base address for renderclear

== Series Details == Series: drm/i915/gt: Correct surface base address for renderclear URL : https://patchwork.freedesktop.org/series/86947/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9757_full -> Patchwork_19653_full Su

Re: [Intel-gfx] [RFC PATCH 8/9] drm/gem: Associate GEM objects with drm cgroup

On 2/9/2021 2:54 AM, Daniel Vetter wrote: > On Tue, Jan 26, 2021 at 01:46:25PM -0800, Brian Welty wrote: >> This patch adds tracking of which cgroup to make charges against for a >> given GEM object. We associate the current task's cgroup with GEM objects >> as they are created. First user of t

[Intel-gfx] [PATCH 1/6] drm/i915/gt: Sanitize GPU during prepare-to-suspend

After calling intel_gt_suspend_prepare(), the driver starts to turn off various subsystems, such as clearing the GGTT, before calling intel_gt_suspend_late() to relinquish control over the GT. However, if we still have internal GPU state active as we clear the GGTT, the GPU may write back its inter

[Intel-gfx] [PATCH 2/6] drm/i915: Clear internal GT state on hibernate

Call intel_gt_suspend_late() to disable the GT before hibernation. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index 000e1cd8e920..da0

[Intel-gfx] [PATCH 6/6] drm/i915: Remove unused debug functions

Remove or hide unused debug functions from clang, or else it moans. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_sw_fence.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index

[Intel-gfx] [PATCH 5/6] drm/i915: Check for scratch page scribbling

Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- .../drm/i915/gem/selftests/i915_gem_context.c | 24 +++--- .../drm/i915/gem/self

[Intel-gfx] [PATCH 3/6] drm/i915/selftests: Declare suspend_state before testing suspend

As we mock the suspend routines to exercise suspending driver and manipulating backing storage across the suspend, declare the suspend target as we do. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem.c | 40 +-- 1 file changed, 30 insertions(+), 10 del

[Intel-gfx] [PATCH 4/6] drm/i915/selftests: Restrict partial-tiling to write into the object

Check that the address we are about to write into maps into the object to avoid stray writes into the scratch page. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation

On Fri, Jan 29, 2021 at 02:01:32PM +0200, Jani Nikula wrote: On Fri, 29 Jan 2021, Chris Wilson wrote: Quoting Jani Nikula (2021-01-29 11:12:02) On Thu, 28 Jan 2021, Matt Roper wrote: > From: Vandita Kulkarni > > Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by > the V

Re: [Intel-gfx] [PATCH] drm/i915/gt: Ratelimit heartbeat completion probing

Chris, I applied this patch to DII. I could not apply automatically, so I do it manually. The only problem is following in selftest code: Dii code: +err_reset: intel_engine_set_heartbeat(engine, CONFIG_DRM_I915_HEARTBEAT_INTERVAL); your code: +err_reset: reset_heartbeat(engin

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915/gt: Sanitize GPU during prepare-to-suspend

== Series Details == Series: series starting with [1/6] drm/i915/gt: Sanitize GPU during prepare-to-suspend URL : https://patchwork.freedesktop.org/series/86962/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checke

Re: [Intel-gfx] [PATCH] Revert "drm/atomic: document and enforce rules around "spurious" EBUSY"

On Wed, Feb 10, 2021 at 05:07:03PM +0200, Ville Syrjälä wrote: > On Wed, Feb 10, 2021 at 01:38:45PM +, Simon Ser wrote: > > On Wednesday, February 10th, 2021 at 2:16 PM, Daniel Vetter > > wrote: > > > > > On Tue, Feb 09, 2021 at 04:14:01PM -0800, Manasi Navare wrote: > > > > > > > These addi

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/gt: Sanitize GPU during prepare-to-suspend

== Series Details == Series: series starting with [1/6] drm/i915/gt: Sanitize GPU during prepare-to-suspend URL : https://patchwork.freedesktop.org/series/86962/ State : success == Summary == CI Bug Log - changes from CI_DRM_9761 -> Patchwork_19655

[Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 160 PTE, warning that the accesses will wrap around the ends of the GGTT. Currently, we fill the en

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

Quoting Hans de Goede (2021-02-10 10:37:19) > Hi, > > On 2/10/21 12:07 AM, Chris Wilson wrote: > > Quoting Hans de Goede (2021-02-09 11:46:46) > >> Hi, > >> > >> On 2/9/21 12:27 AM, Chris Wilson wrote: > >>> Quoting Hans de Goede (2021-02-08 20:38:58) > Hi All, > > We (Fedora) have

Re: [Intel-gfx] [PATCH 01/18] drm/i915/display13: add Display13 characteristics

On Thu, Jan 28, 2021 at 11:23:56AM -0800, Matt Roper wrote: Let's start preparing for upcoming platforms that will use a Display13 design. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_pci.c | 11 +++ drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH 02/18] drm/i915/display13: Handle proper AUX interrupt bits

On Thu, Jan 28, 2021 at 11:23:57AM -0800, Matt Roper wrote: Display13 has new AUX interrupt bits for DDI-D and DDI-E. Bspec: 50064 Cc: Anusha Srivatsa Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_irq.c | 12 +++- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 13 ins

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Refine VT-d scanout workaround

== Series Details == Series: drm/i915: Refine VT-d scanout workaround URL : https://patchwork.freedesktop.org/series/86967/ State : success == Summary == CI Bug Log - changes from CI_DRM_9761 -> Patchwork_19656 Summary --- **SUCCESS*

Re: [Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting

On Thu, Jan 28, 2021 at 11:23:58AM -0800, Matt Roper wrote: Display13 brings enhanced underrun recovery: the hardware can somewhat mitigate underruns by using an interpolated replacement pixel (soft underrun) or the previous pixel (hard underrun). Furthermore, underruns can now be caused downst

Re: [Intel-gfx] [PATCH 04/18] drm/i915/display13: Define plane capabilities

On Thu, Jan 28, 2021 at 11:23:59AM -0800, Matt Roper wrote: Display13's plane support is identical to RKL --- 5 universal + 1 cursor with NV12 UV support on planes 1-3 and NV12 Y support on planes 4-5. Bspec: 53657 Bspec: 49251 Cc: Lucas De Marchi Signed-off-by: Matt Roper --- drivers/gpu/drm/

Re: [Intel-gfx] [PATCH 05/18] drm/i915/display13: Support 128k plane stride

On Thu, Jan 28, 2021 at 11:24:00AM -0800, Matt Roper wrote: From: Juha-Pekka Heikkilä Display13 supports plane strides up to 128KB. Cc: Vandita Kulkarni Signed-off-by: Juha-Pekka Heikkilä Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 6 - drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH 06/18] drm/i915/display13: Only enable legacy gamma for now

On Thu, Jan 28, 2021 at 11:24:01AM -0800, Matt Roper wrote: The multi-segment gamma used on past platforms is gone and replaced by a logarithmic LUT. Until logarithmic LUT is enabled, let's just turn off uapi color management (aside from legacy gamma) since it doesn't really make sense to expose

Re: [Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells

On Thu, Jan 28, 2021 at 11:24:02AM -0800, Matt Roper wrote: Aside from the hardware-managed PG0, Display13 has power wells 1-2 and A-D. These power wells should be enabled/disabled according to the following dependency tree (enable top to bottom, disable bottom to top): PG0

Re: [Intel-gfx] [PATCH 08/18] drm/i915/display13: Handle LPSP for Display 13

On Thu, Jan 28, 2021 at 11:24:03AM -0800, Matt Roper wrote: From: Uma Shankar Enable LPSP for Display13 and get the proper power well enable check in place. For Display13 it is PW2 which need to check for LPSP. Cc: Anshuman Gupta Cc: Animesh Manna Cc: Matt Roper Suggested-by: Matt Roper Si

Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/gen9_bc: Recognize TGP PCH + CML combos

On Tue, Feb 09, 2021 at 04:28:28PM -0500, Lyude Paul wrote: > Since Intel has introduced the gen9_bc platform, a combination of > Tigerpoint PCHs and CML CPUs, let's recognize such platforms as valid and > avoid WARNing on them. > > Changes since v4: > * Split this into it's own patch - vsyrjala >

Re: [Intel-gfx] [PATCH v5 3/4] drm/i915/gen9_bc: Introduce HPD pin mappings for TGP PCH + CML combos

On Tue, Feb 09, 2021 at 04:28:30PM -0500, Lyude Paul wrote: > Next, let's start introducing the HPD pin mappings for Intel's new gen9_bc > platform in order to make hotplugging display connectors work. Since > gen9_bc is just a TGP PCH along with a CML CPU, except with the same HPD > mappings as IC

Re: [Intel-gfx] [PATCH v5 4/4] drm/i915/gen9_bc: Add W/A for missing STRAP config on TGP PCH + CML combos

On Tue, Feb 09, 2021 at 04:28:31PM -0500, Lyude Paul wrote: > Apparently the new gen9_bc platforms that Intel has introduced don't > provide us with a STRAP config register to read from for initializing DDI > B, C, and D detection. So, workaround this by hard-coding our strap config > in intel_setu

Re: [Intel-gfx] [PATCH v5 2/4] drm/i915/gen9_bc: Introduce TGP PCH DDC pin mappings

On Tue, Feb 09, 2021 at 04:28:29PM -0500, Lyude Paul wrote: > With the introduction of gen9_bc, where Intel combines Cometlake CPUs with > a Tigerpoint PCH, we'll need to introduce new DDC pin mappings for this > platform in order to make all of the display connectors work. So, let's do > that. >

Re: [Intel-gfx] [RFC v4 09/11] drm/i915/dpcd_bl: Print return codes for VESA backlight failures

On Mon, Feb 08, 2021 at 06:38:59PM -0500, Lyude Paul wrote: > Also, stop printing the DPCD register that failed, and just describe it > instead. Saves us from having to look up each register offset when reading > through kernel logs (plus, DPCD dumping with drm.debug |= 0x100 will give > us that an

Re: [Intel-gfx] [RFC v4 08/11] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT

On Mon, Feb 08, 2021 at 06:38:58PM -0500, Lyude Paul wrote: > If we can't read DP_EDP_PWMGEN_BIT_COUNT in > intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency > defined in the VBT, we'll keep going in the function until we inevitably > fail on reading DP_EDP_PWMGEN_BIT_COUNT_C

Re: [Intel-gfx] [RFC v4 05/11] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit

On Mon, Feb 08, 2021 at 06:38:55PM -0500, Lyude Paul wrote: > Get rid of the extraneous switch case in here, and just open code > edp_backlight_mode as we only ever use it once. > > v4: > * Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not > DP_EDP_BACKLIGHT_CONTROL_MODE_MASK

Re: [Intel-gfx] [RFC v4 10/11] drm/dp: Extract i915's eDP backlight code into DRM helpers

On Mon, Feb 08, 2021 at 06:39:00PM -0500, Lyude Paul wrote: > Since we're about to implement eDP backlight support in nouveau using the > standard protocol from VESA, we might as well just take the code that's > already written for this and move it into a set of shared DRM helpers. > > Note that t

Re: [Intel-gfx] [PATCH 1/6] drm/i915/gt: Sanitize GPU during prepare-to-suspend

On Wed, Feb 10, 2021 at 10:19:50PM +, Chris Wilson wrote: > After calling intel_gt_suspend_prepare(), the driver starts to turn off > various subsystems, such as clearing the GGTT, before calling > intel_gt_suspend_late() to relinquish control over the GT. However, if > we still have internal G

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Clear internal GT state on hibernate

On Wed, Feb 10, 2021 at 10:19:51PM +, Chris Wilson wrote: > Call intel_gt_suspend_late() to disable the GT before hibernation. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gem/i

Re: [Intel-gfx] [PATCH] drm/i915/adl_s: Add gmbus pin mapping

Hi Aditya, Thanks for your review comments. -Original Message- From: Aditya Swarup Sent: Wednesday, February 10, 2021 9:54 PM To: Ram Moon, AnandX ; intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Roper, Matthew D ; Auld, Matthew ; Surendrakumar Upadhyay, Tejaskumar

Re: [Intel-gfx] [PATCH] drm/i915/vbt: update DP max link rate table

On Wed, Feb 10, 2021 at 04:51 p.m, Ville Syrjälä wrote: >On Mon, Feb 08, 2021 at 01:31:57PM +, Lee, Shawn C wrote: >> On Fri, Feb 05, 2021, at 8:26 p.m, Ville Syrjälä wrote: >> >On Mon, Feb 01, 2021 at 11:02:28PM +0800, Lee Shawn C wrote: >> >> According to Bspec #20124, max link rate table f

[Intel-gfx] [PATCH v2] drm/i915/debugfs: HDCP capability enc NULL check

DP-MST connector encoder initializes at modeset Adding a connector->encoder NULL check in order to avoid any NULL pointer dereference. intel_hdcp_enable() already handle this but debugfs can also invoke the intel_{hdcp,hdcp2_capable}. Handling it gracefully. v2: - Use necessary lock and NULL check

[Intel-gfx] [PATCH v2 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON

Currently the FRL training mode (Concurrent, Sequential) and training type (Normal, Extended) are not defined properly and are passed as bool values in drm_helpers for pcon configuration for FRL training. This patch: -Add register masks for Sequential and Normal FRL training options. -Fixes the dr

Re: [Intel-gfx] [RFC PATCH 1/2] drm/dp: Make number of AUX retries configurable by display drivers.

On Wed, 2021-02-10 at 13:03 -0500, Lyude Paul wrote: > On Wed, 2021-02-10 at 00:33 -0800, Khaled Almahallawy wrote: > > The number of AUX retries specified in the DP specs is 7. > > Currently, to make > > Dell 4k monitors happier, the number of retries are 32. > > i915 also retries 5 times (intel_d

Re: [Intel-gfx] [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON

On 2/6/2021 1:30 AM, Ville Syrjälä wrote: On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote: Currently the FRL training mode (Concurrent, Sequential) and training type (Normal, Extended) are not defined properly and are passed as bool values in drm_helpers for pcon configuration fo

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/debugfs: HDCP capability enc NULL check (rev2)

== Series Details == Series: drm/i915/debugfs: HDCP capability enc NULL check (rev2) URL : https://patchwork.freedesktop.org/series/86440/ State : success == Summary == CI Bug Log - changes from CI_DRM_9761 -> Patchwork_19657 Summary --

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDMI2.1 PCON Misc Fixes (rev2)

== Series Details == Series: HDMI2.1 PCON Misc Fixes (rev2) URL : https://patchwork.freedesktop.org/series/86677/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../