[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [01/15] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [01/15] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74740/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fenc

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/15] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [01/15] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74740/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16979

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: DisplayID parser fixes

== Series Details == Series: drm/edid: DisplayID parser fixes URL : https://patchwork.freedesktop.org/series/74689/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16968_full Summary --- **FAILUR

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel (rev3)

== Series Details == Series: drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel (rev3) URL : https://patchwork.freedesktop.org/series/57989/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Dynamic EU configuration of Slice/Sub-slice/EU (rev7)

== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev7) URL : https://patchwork.freedesktop.org/series/69980/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compi

Re: [Intel-gfx] [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma

On Fri, Feb 14, 2020 at 7:36 AM Michel Dänzer wrote: > > On 2020-02-14 12:49 p.m., Jani Nikula wrote: > > On Fri, 14 Feb 2020, Chris Wilson wrote: > >> Quoting Jani Nikula (2020-02-14 06:36:15) > >>> On Thu, 13 Feb 2020, Nathan Chancellor wrote: > A recent commit in clang added -Wtautologic

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi cmd mode (rev8)

== Series Details == Series: Add support for mipi dsi cmd mode (rev8) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ dim checkpatch origin/drm-tip 006bc864d36a drm/i915/dsi: Configure transcoder operation for command mode. 01f67de3b52d drm/i915/dsi: Add v

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for mipi dsi cmd mode (rev8)

== Series Details == Series: Add support for mipi dsi cmd mode (rev8) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/dsi: Configure transcoder operation for command mode. Okay! Commit: drm

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for mipi dsi cmd mode (rev8)

== Series Details == Series: Add support for mipi dsi cmd mode (rev8) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./d

Re: [Intel-gfx] [PATCH 3/4] drm/i915/perf: only append status when data is available

On Thu, 12 Mar 2020 16:05:01 -0700, Umesh Nerlige Ramappa wrote: > > From: Lionel Landwerlin > > The only bit of the status register we currently report in the > i915-perf stream is the "report loss" bit. Only report this when we > have some data to report with it. There was a kind of inconsistenc

[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for mipi dsi cmd mode (rev8)

== Series Details == Series: Add support for mipi dsi cmd mode (rev8) URL : https://patchwork.freedesktop.org/series/69290/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16982 Summary --- **SUCCESS*

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/edp: Ignore short pulse when panel powered off (rev2)

== Series Details == Series: drm/i915/edp: Ignore short pulse when panel powered off (rev2) URL : https://patchwork.freedesktop.org/series/74265/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16970_full ===

[Intel-gfx] [PATCH v2 2/3] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs

According to BSpec max BW per slice is calculated using formula Max BW = CDCLK * 64. Currently when calculating min CDCLK we account only per plane requirements, however in order to avoid FIFO underruns we need to estimate accumulated BW consumed by all planes(ddb entries basically) residing on tha

[Intel-gfx] [PATCH] drm/i915/gem: Avoid gem_context->mutex for simple vma lookup

As we store the handle lookup inside a radix tree, we do not need the gem_context->mutex except until we need to insert our lookup into the common radix tree. This takes a small bit of rearranging to ensure that the lut we insert into the tree is ready prior to actually inserting it (as soon as it

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Try allocating va from free space

== Series Details == Series: drm/i915/gem: Try allocating va from free space URL : https://patchwork.freedesktop.org/series/74748/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open f

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v6,1/3] drm/i915/perf: remove generated code

== Series Details == Series: series starting with [v6,1/3] drm/i915/perf: remove generated code URL : https://patchwork.freedesktop.org/series/74702/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16971_full ===

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Check for a closed context when looking up an engine

== Series Details == Series: drm/i915/gem: Check for a closed context when looking up an engine URL : https://patchwork.freedesktop.org/series/74750/ State : warning == Summary == $ dim checkpatch origin/drm-tip a3c39e8196a9 drm/i915/gem: Check for a closed context when looking up an engine -:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Try allocating va from free space

== Series Details == Series: drm/i915/gem: Try allocating va from free space URL : https://patchwork.freedesktop.org/series/74748/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16983 Summary --- **F

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Check for a closed context when looking up an engine

== Series Details == Series: drm/i915/gem: Check for a closed context when looking up an engine URL : https://patchwork.freedesktop.org/series/74750/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c E

Re: [Intel-gfx] [PATCH v1 1/3] drm/i915: Decouple cdclk calculation from modeset checks

On Mon, Mar 16, 2020 at 01:37:42PM +0200, Stanislav Lisovskiy wrote: > We need to calculate cdclk after watermarks/ddb has been calculated > as with recent hw CDCLK needs to be adjusted accordingly to DBuf > requirements, which is not possible with current code organization. > > Setting CDCLK acco

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Check for a closed context when looking up an engine

== Series Details == Series: drm/i915/gem: Check for a closed context when looking up an engine URL : https://patchwork.freedesktop.org/series/74750/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16984 Sum

Re: [Intel-gfx] [PATCH v1 3/3] drm/i915: Remove unneeded hack now for CDCLK

On Mon, Mar 16, 2020 at 01:37:44PM +0200, Stanislav Lisovskiy wrote: > No need to bump up CDCLK now, as it is now correctly > calculated, accounting for DBuf BW as BSpec says. > > Signed-off-by: Stanislav Lisovskiy Logic looks good, Reviewed-by: Manasi Navare Manasi > --- > drivers/gpu/drm/

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: convert to struct drm_device based logging macros.

== Series Details == Series: drm/i915/gt: convert to struct drm_device based logging macros. URL : https://patchwork.freedesktop.org/series/74707/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16973_full ==

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gt: Restore check for invalid vma for fencing

== Series Details == Series: drm/i915/gt: Restore check for invalid vma for fencing URL : https://patchwork.freedesktop.org/series/74758/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot

Re: [Intel-gfx] [PATCH 4/4] drm/i915/perf: add new open param to configure polling of OA buffer

On Thu, 12 Mar 2020 16:05:02 -0700, Umesh Nerlige Ramappa wrote: > > From: Lionel Landwerlin > > This new parameter let's the application choose how often the OA > buffer should be checked on the CPU side for data availability. Longer > polling period tend to reduce CPU overhead if the application

Re: [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register

On Mon, Mar 16, 2020 at 04:07:58PM +0530, Animesh Manna wrote: > DP_COMP_CTL and DP_COMP_PAT register used to program DP > compliance pattern. > > v1: Initial patch. > v2: used pipe instead of port in macro definition. [Manasi] > > Reviewed-by: Manasi Navare > Signed-off-by: Animesh Manna > ---

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Cast remain to unsigned long in eb_relocate_vma (rev2)

== Series Details == Series: drm/i915: Cast remain to unsigned long in eb_relocate_vma (rev2) URL : https://patchwork.freedesktop.org/series/73440/ State : failure == Summary == Applying: drm/i915: Cast remain to unsigned long in eb_relocate_vma error: git diff header lacks filename informatio

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Restore check for invalid vma for fencing

== Series Details == Series: drm/i915/gt: Restore check for invalid vma for fencing URL : https://patchwork.freedesktop.org/series/74758/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16985 Summary ---

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Consider DBuf bandwidth when calculating CDCLK (rev2)

== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev2) URL : https://patchwork.freedesktop.org/series/74739/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot

[Intel-gfx] ✓ Fi.CI.BAT: success for Consider DBuf bandwidth when calculating CDCLK (rev2)

== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev2) URL : https://patchwork.freedesktop.org/series/74739/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138 -> Patchwork_16987 Summary ---

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup

== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup URL : https://patchwork.freedesktop.org/series/74759/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup

== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup URL : https://patchwork.freedesktop.org/series/74759/ State : success == Summary == CI Bug Log - changes from CI_DRM_8139 -> Patchwork_16988 Summary -

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3)

== Series Details == Series: drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3) URL : https://patchwork.freedesktop.org/series/74100/ State : success == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16974_full ==

Re: [Intel-gfx] [PATCH v7 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

Hi Ankit, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip next-20200316] [cannot apply to v5.6-rc6] [if your patch is applied to the wrong git tree, please drop us a note to help improve the

[Intel-gfx] ✗ Fi.CI.IGT: failure for DP Phy compliance auto test (rev7)

== Series Details == Series: DP Phy compliance auto test (rev7) URL : https://patchwork.freedesktop.org/series/71121/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16976_full Summary --- **FAIL

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/

== Series Details == Series: series starting with [CI,1/4] drm/i915: Move GGTT fence registers under gt/ URL : https://patchwork.freedesktop.org/series/74738/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8137_full -> Patchwork_16977_full =

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