On Mon, Mar 16, 2020 at 01:37:44PM +0200, Stanislav Lisovskiy wrote: > No need to bump up CDCLK now, as it is now correctly > calculated, accounting for DBuf BW as BSpec says. > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Logic looks good, Reviewed-by: Manasi Navare <manasi.d.nav...@intel.com> Manasi > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ------------ > 1 file changed, 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index f0dcea4d6357..45469f6833b8 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2055,18 +2055,6 @@ int intel_crtc_compute_min_cdclk(const struct > intel_crtc_state *crtc_state) > /* Account for additional needs from the planes */ > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); > > - /* > - * HACK. Currently for TGL platforms we calculate > - * min_cdclk initially based on pixel_rate divided > - * by 2, accounting for also plane requirements, > - * however in some cases the lowest possible CDCLK > - * doesn't work and causing the underruns. > - * Explicitly stating here that this seems to be currently > - * rather a Hack, than final solution. > - */ > - if (IS_TIGERLAKE(dev_priv)) > - min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > - > /* > * Similar story as with skl_write_plane_wm and intel_enable_sagv > * - in some certain driver parts, we don't have any guarantee that > -- > 2.24.1.485.gad05a3d8e5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
