[Intel-gfx] [PATCH v5 16/16] drm/i915: Add HDCP 1.4 support for MST connectors

From: Sean Paul Now that all the groundwork has been laid, we can turn on HDCP 1.4 over MST. Everything except for toggling the HDCP signalling and HDCP 2.2 support is the same as the DP case, so we'll re-use those callbacks Cc: Juston Li Signed-off-by: Sean Paul Link: https://patchwork.freed

[Intel-gfx] [PATCH v5 12/16] drm/i915: Plumb port through hdcp init

From: Sean Paul This patch plumbs port through hdcp init instead of relying on intel_attached_encoder() to return a non-NULL encoder which won't work for MST connectors. Cc: Ville Syrjälä Signed-off-by: Sean Paul Changes in v5: -Added to the set --- drivers/gpu/drm/i915/display/intel_dp_hdcp

[Intel-gfx] [PATCH v5 14/16] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message

From: Sean Paul Used to query whether an MST stream is encrypted or not. Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-s...@poorly.run #v4 Changes in v4: -Added to the set Changes in v5: -None --- drivers/gpu/drm/drm_dp_mst_topology.c

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Improve the start alignment of bonded pairs

== Series Details == Series: drm/i915: Improve the start alignment of bonded pairs URL : https://patchwork.freedesktop.org/series/74315/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter

[Intel-gfx] [PATCH] drm/i915/tgl: Don't treat unslice registers as masked

The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 registers that we update in a few engine workarounds are not masked registers (i.e., we don't have to write a mask bit in the top 16 bits when updating one of the lower 16 bits). As such, these workarounds should be applied via wa_writ

[Intel-gfx] [PATCH v2] drm/i915: properly sanity check batch_start_offset

Check the edge case where batch_start_offset sits exactly on the batch size. v2: add new range_overflows variant to capture the special case where the size is permitted to be zero, like with batch_len. Testcase: igt/gem_exec_params/invalid-batch-start-offset Fixes: 0b5372727be3 ("drm/i915/cmdpars

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Enable timeslice on partial virtual engine dequeue

== Series Details == Series: drm/i915/execlists: Enable timeslice on partial virtual engine dequeue URL : https://patchwork.freedesktop.org/series/74304/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16833

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve the start alignment of bonded pairs

== Series Details == Series: drm/i915: Improve the start alignment of bonded pairs URL : https://patchwork.freedesktop.org/series/74315/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16835 Summary ---

[Intel-gfx] [PATCH] drm/i915: be more solid in checking the alignment

The alignment is u64, and yet is_power_of_2() assumes unsigned long, which might give different results between 32b and 64b kernel. Signed-off-by: Matthew Auld Cc: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 ++- drivers/gpu/drm/i915/i915_utils.h | 5 +

[Intel-gfx] [PATCH] drm/i915/phys: unconditionally call release_memory_region

From: Abdiel Janulgue The release method will undo what we did at creation, and so we shouldn't care if we have pages or not. Fixes a small leak in the mock_phys selftest. Signed-off-by: Abdiel Janulgue Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 7 --- 1 fi

[Intel-gfx] [PATCH 1/2] drm/i915/buddy: avoid double list_add

Be careful not to mark an already free node as free again. Signed-off-by: Matthew Auld Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_buddy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_buddy.c b/drivers/gpu/drm/i915/i915_buddy.c index 66883a

[Intel-gfx] [PATCH 2/2] drm/i915/selftests: try to rein in alloc_smoke

Depending on RNG we might try to fill an 8G region for every possible order, using the smallest possible chunk size of 4K, which seems to be very slow. Try to remedy the situation by adding an overall timeout for the test, while also selecting each order level in a random fashion. Closes: https://

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Actually emit the await_start

== Series Details == Series: drm/i915: Actually emit the await_start URL : https://patchwork.freedesktop.org/series/74319/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get

[Intel-gfx] [PATCH v2] i915/gem_exec_params: add test_invalid_batch

Sanity check that kernel rejects invalid batch_start_offset and batch_len. Signed-off-by: Matthew Auld Cc: Mika Kuoppala Cc: Chris Wilson --- tests/i915/gem_exec_params.c | 47 1 file changed, 47 insertions(+) diff --git a/tests/i915/gem_exec_params.c b/te

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Actually emit the await_start

== Series Details == Series: drm/i915: Actually emit the await_start URL : https://patchwork.freedesktop.org/series/74319/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16836 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission

== Series Details == Series: series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission URL : https://patchwork.freedesktop.org/series/74331/ State : warning == Summary == $ dim checkpatch origin/drm-tip e0fd0fe40b02 drm/i915: Add mechanism to submit a con

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Don't treat unslice registers as masked

On Thu, Mar 5, 2020 at 12:25 PM Matt Roper wrote: > > The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 registers > that we update in a few engine workarounds are not masked registers > (i.e., we don't have to write a mask bit in the top 16 bits when > updating one of the lower 16 bit

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission

== Series Details == Series: series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission URL : https://patchwork.freedesktop.org/series/74331/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dp

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission

== Series Details == Series: series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission URL : https://patchwork.freedesktop.org/series/74331/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16837 ===

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm: drm_fb_helper cleanup. (rev3)

== Series Details == Series: drm: drm_fb_helper cleanup. (rev3) URL : https://patchwork.freedesktop.org/series/74140/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: drm_fb_helper cleanup. (rev3)

== Series Details == Series: drm: drm_fb_helper cleanup. (rev3) URL : https://patchwork.freedesktop.org/series/74140/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16838 Summary --- **SUCCESS** N

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Return early for await_start on same timeline

== Series Details == Series: drm/i915: Return early for await_start on same timeline URL : https://patchwork.freedesktop.org/series/74338/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function paramete

Re: [Intel-gfx] [PATCH 5/6] drm/i915/uc: Move uC debugfs to its own folder under GT

On 3/5/20 10:02 AM, Andi Shyti wrote: Hi Daniele, On Thu, Feb 27, 2020 at 06:28:42PM -0800, Daniele Ceraolo Spurio wrote: uC is a component of the GT, so it makes sense for the uC debugfs files to be in the GT folder. A subfolder has been used to keep the same structure we have for the code

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: HDCP: fix Ri prime and R0 checks during auth (rev2)

== Series Details == Series: drm/i915: HDCP: fix Ri prime and R0 checks during auth (rev2) URL : https://patchwork.freedesktop.org/series/74271/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function pa

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Return early for await_start on same timeline

== Series Details == Series: drm/i915: Return early for await_start on same timeline URL : https://patchwork.freedesktop.org/series/74338/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16839 Summary --

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Don't treat unslice registers as masked

On Thu, 2020-03-05 at 12:24 -0800, Matt Roper wrote: > The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 > registers > that we update in a few engine workarounds are not masked registers > (i.e., we don't have to write a mask bit in the top 16 bits when > updating one of the lower 16 b

[Intel-gfx] [PATCH] drm/i915/gt: allow setting generic data pointer

When registering debugfs files the intel gt debugfs library forces a 'struct *gt' private data on the caller. There might be different needs, therefore make it generic by adding one more argument to the "debugfs_register_files()" function which gets the generic void private data as argument. Stil

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/execlists: Show the "switch priority hint" in dumps

== Series Details == Series: drm/i915/execlists: Show the "switch priority hint" in dumps URL : https://patchwork.freedesktop.org/series/74340/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function par

[Intel-gfx] [CI 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

From: Mika Kuoppala This patch adds framework to submit an arbitrary batchbuffer on each context switch to clear residual state for render engine on Gen7/7.5 devices. The idea of always emitting the context and vm setup around each request is primary to make reset recovery easy, and not require

[Intel-gfx] [CI 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

From: Prathap Kumar Valsan On gen7 and gen7.5 devices, there could be leftover data residuals in EU/L3 from the retiring context. This patch introduces workaround to clear that residual contexts, by submitting a batch buffer with dedicated HW context to the GPU with ring allocation for each conte

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Show the "switch priority hint" in dumps

== Series Details == Series: drm/i915/execlists: Show the "switch priority hint" in dumps URL : https://patchwork.freedesktop.org/series/74340/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16841 Summary -

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Deactive FBC in fastsets when disabled by parameter

On Wed, 2020-02-19 at 20:52 +0200, Ville Syrjälä wrote: > On Wed, Feb 19, 2020 at 06:37:27PM +, Souza, Jose wrote: > > On Wed, 2020-02-19 at 15:37 +0200, Ville Syrjälä wrote: > > > On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza > > > wrote: > > > > Most of the kms_frontbuffer_t

Re: [Intel-gfx] [PATCH] drm/i915/gt: allow setting generic data pointer

On 3/5/20 3:59 PM, Andi Shyti wrote: When registering debugfs files the intel gt debugfs library forces a 'struct *gt' private data on the caller. There might be different needs, therefore make it generic by adding one more argument to the "debugfs_register_files()" function which gets the ge

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Limit struct_mutex to eb_reserve (rev2)

== Series Details == Series: drm/i915/gem: Limit struct_mutex to eb_reserve (rev2) URL : https://patchwork.freedesktop.org/series/74291/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter

Re: [Intel-gfx] [PATCH] drm/i915/gt: allow setting generic data pointer

Hi Daniele, > > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c > > b/drivers/gpu/drm/i915/gt/debugfs_gt.c > > index 75255aaacaed..9112a8585caf 100644 > > --- a/drivers/gpu/drm/i915/gt/debugfs_gt.c > > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c > > @@ -26,15 +26,14 @@ void debugfs_gt_register(s

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Limit struct_mutex to eb_reserve (rev2)

== Series Details == Series: drm/i915/gem: Limit struct_mutex to eb_reserve (rev2) URL : https://patchwork.freedesktop.org/series/74291/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8071 -> Patchwork_16842 Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: properly sanity check batch_start_offset

== Series Details == Series: drm/i915: properly sanity check batch_start_offset URL : https://patchwork.freedesktop.org/series/74287/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8068_full -> Patchwork_16826_full Summary -

Re: [Intel-gfx] [PATCH] drm/i915/gt: allow setting generic data pointer

On 3/5/20 5:15 PM, Andi Shyti wrote: Hi Daniele, diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c b/drivers/gpu/drm/i915/gt/debugfs_gt.c index 75255aaacaed..9112a8585caf 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c @@ -26,15 +26,14 @@ void de

Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+

On Thu, 2020-02-20 at 19:26 +0200, Ville Syrjälä wrote: > On Tue, Feb 18, 2020 at 05:42:30PM -0800, José Roberto de Souza > wrote: > > dGFX have local memory so it do not have aperture and do not > > support > > CPU fences but even for iGFX it have a small number of fences. > > > > As replacement

[Intel-gfx] [PATCH v4 2/2] drm/dp: Add function to parse EDID descriptors for adaptive sync limits

Adaptive Sync is a VESA feature so add a DRM core helper to parse the EDID's detailed descritors to obtain the adaptive sync monitor range. Store this info as part fo drm_display_info so it can be used across all drivers. This part of the code is stripped out of amdgpu's function amdgpu_dm_update_f

[Intel-gfx] [PATCH v4 1/2] drm/edid: Name the detailed monitor range flags

This patch adds defines for the detailed monitor range flags as per the EDID specification. Suggested-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Harry Wentland Cc: Clinton A Taylor Cc: Kazlauskas Nicholas Signed-off-by: Manasi Navare --- include/drm/drm_edid.h | 5 + 1 file changed, 5 inse

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/1] Revert "drm/i915/tgl: Add extra hdc flush workaround"

== Series Details == Series: series starting with [1/1] Revert "drm/i915/tgl: Add extra hdc flush workaround" URL : https://patchwork.freedesktop.org/series/74293/ State : success == Summary == CI Bug Log - changes from CI_DRM_8068_full -> Patchwork_16829_full

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off

== Series Details == Series: drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off URL : https://patchwork.freedesktop.org/series/74346/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function paramet

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off

== Series Details == Series: drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off URL : https://patchwork.freedesktop.org/series/74346/ State : success == Summary == CI Bug Log - changes from CI_DRM_8073 -> Patchwork_16843 Summary -

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (rev6)

== Series Details == Series: drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (rev6) URL : https://patchwork.freedesktop.org/series/72747/ State : success == Summary == CI Bug Log - changes from CI_DRM_8068_full -> Patchwork_16830_full ==

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/tgl: Make wa_1606700617 permanent (rev2)

== Series Details == Series: drm/i915/tgl: Make wa_1606700617 permanent (rev2) URL : https://patchwork.freedesktop.org/series/74240/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or m

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Make wa_1606700617 permanent (rev2)

== Series Details == Series: drm/i915/tgl: Make wa_1606700617 permanent (rev2) URL : https://patchwork.freedesktop.org/series/74240/ State : success == Summary == CI Bug Log - changes from CI_DRM_8073 -> Patchwork_16844 Summary --- *

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for HDCP 1.4 over MST connectors (rev5)

== Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev5) URL : https://patchwork.freedesktop.org/series/70393/ State : warning == Summary == $ dim checkpatch origin/drm-tip f3d9bb7dc10f drm/i915: Fix sha_text population code -:63: WARNING:LINE_SPACING: Missing

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Add support for HDCP 1.4 over MST connectors (rev5)

== Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev5) URL : https://patchwork.freedesktop.org/series/70393/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function pa

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Don't treat unslice registers as masked

== Series Details == Series: drm/i915/tgl: Don't treat unslice registers as masked URL : https://patchwork.freedesktop.org/series/74351/ State : failure == Summary == Applying: drm/i915/tgl: Don't treat unslice registers as masked error: sha1 information is lacking or useless (drivers/gpu/drm

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add support for HDCP 1.4 over MST connectors (rev5)

== Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev5) URL : https://patchwork.freedesktop.org/series/70393/ State : success == Summary == CI Bug Log - changes from CI_DRM_8073 -> Patchwork_16845 Summary

Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Add support for integrated privacy screens

Hi Jani, Thank you for the comments. Please see my responses inline. On Thu, Mar 5, 2020 at 2:02 AM Jani Nikula wrote: > > On Wed, 04 Mar 2020, Rajat Jain wrote: > > Certain laptops now come with panels that have integrated privacy > > screens on them. This patch adds support for such panels by

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: properly sanity check batch_start_offset (rev2)

== Series Details == Series: drm/i915: properly sanity check batch_start_offset (rev2) URL : https://patchwork.freedesktop.org/series/74287/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parame

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: properly sanity check batch_start_offset (rev2)

== Series Details == Series: drm/i915: properly sanity check batch_start_offset (rev2) URL : https://patchwork.freedesktop.org/series/74287/ State : success == Summary == CI Bug Log - changes from CI_DRM_8073 -> Patchwork_16847 Summary

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: be more solid in checking the alignment

== Series Details == Series: drm/i915: be more solid in checking the alignment URL : https://patchwork.freedesktop.org/series/74353/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or m

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: be more solid in checking the alignment

== Series Details == Series: drm/i915: be more solid in checking the alignment URL : https://patchwork.freedesktop.org/series/74353/ State : success == Summary == CI Bug Log - changes from CI_DRM_8074 -> Patchwork_16848 Summary --- *

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/phys: unconditionally call release_memory_region

== Series Details == Series: drm/i915/phys: unconditionally call release_memory_region URL : https://patchwork.freedesktop.org/series/74354/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parame

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/phys: unconditionally call release_memory_region

== Series Details == Series: drm/i915/phys: unconditionally call release_memory_region URL : https://patchwork.freedesktop.org/series/74354/ State : success == Summary == CI Bug Log - changes from CI_DRM_8074 -> Patchwork_16849 Summary

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/buddy: avoid double list_add

== Series Details == Series: series starting with [1/2] drm/i915/buddy: avoid double list_add URL : https://patchwork.freedesktop.org/series/74355/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function

[Intel-gfx] ✗ Fi.CI.BUILD: failure for i915/gem_exec_params: add test_invalid_batch

== Series Details == Series: i915/gem_exec_params: add test_invalid_batch URL : https://patchwork.freedesktop.org/series/74356/ State : failure == Summary == Applying: i915/gem_exec_params: add test_invalid_batch error: sha1 information is lacking or useless (tests/i915/gem_exec_params.c). err

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: allow setting generic data pointer

== Series Details == Series: drm/i915/gt: allow setting generic data pointer URL : https://patchwork.freedesktop.org/series/74360/ State : warning == Summary == $ dim checkpatch origin/drm-tip b5c27a068592 drm/i915/gt: allow setting generic data pointer -:72: CHECK:MACRO_ARG_REUSE: Macro argum

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/buddy: avoid double list_add

== Series Details == Series: series starting with [1/2] drm/i915/buddy: avoid double list_add URL : https://patchwork.freedesktop.org/series/74355/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8074 -> Patchwork_16850 Summa

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gt: allow setting generic data pointer

== Series Details == Series: drm/i915/gt: allow setting generic data pointer URL : https://patchwork.freedesktop.org/series/74360/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or mem

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: allow setting generic data pointer

== Series Details == Series: drm/i915/gt: allow setting generic data pointer URL : https://patchwork.freedesktop.org/series/74360/ State : success == Summary == CI Bug Log - changes from CI_DRM_8074 -> Patchwork_16852 Summary --- **S

[Intel-gfx] [PATCH 3/3] drm/i915/gem: Limit struct_mutex to eb_reserve

We only need to serialise the multiple pinning during the eb_reserve phase. Ideally this would be using the vm->mutex as an outer lock, or using a composite global mutex (ww_mutex), but at the moment we are using struct_mutex for the group. Fixes: 003d8b9143a6 ("drm/i915/gem: Only call eb_lookup_v

[Intel-gfx] [PATCH 2/3] drm/i915: Always propagate the invocation to i915_schedule

We only call i915_schedule() when we know we have changed the priority on a request and so require to propagate any change in priority to its signalers (for PI). By unconditionally checking all of our signalers, we avoid skipping changes made prior to construction of the request (as the request may

[Intel-gfx] [PATCH 1/3] drm/i915: Assert requests within a context are submitted in order

Check the flow of requests into the hardware to verify that are submitted in order along their timeline. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 drivers/gpu/drm/i915/i915_request.c | 4 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission

== Series Details == Series: series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission URL : https://patchwork.freedesktop.org/series/74363/ State : warning == Summary == $ dim checkpatch origin/drm-tip c0358b495597 drm/i915: Add mechanism to submit a con

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