On 2019-10-10 at 17:51:25 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The .read_2_2() hooks is never called for any of the message
> types with a zero timeout. So it's all just dead weight which
> we can chuck.
>
> text data bss dec hex filename
> - 34701
On 2019-10-10 at 17:51:26 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The only reason for the timeout2 value in the array is the
> HDCP_2_2_AKE_SEND_HPRIME message. But that one still needs
> special casing inside the loop, and so just ends up making
> the code harder to read. Let's jus
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for
comparing with whitelisted registers
URL : https://patchwork.freedesktop.org/series/68130/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7114 -> Patchwork_14850
===
On 2019-10-10 at 17:51:27 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> All the timeout values fit in u16, so let's shrink the structure
> a bit.
>
> This ends up actually increasing the .text size a bit due to
> some changes in instructions (constant imul+small jmps replaced
> with mov+
From: Lionel Landwerlin
We want this so we can preempt performance queries and keep the system
responsive even when long running queries are ongoing. We avoid doing
it for all contexts.
v2: use LRI to modify context control (Chris)
v3: use MASKED_FIELD to program just the masked bits (Chris)
Si
From: Lionel Landwerlin
The design of the OA unit has been split into several units. We now
have a global unit (OAG) and a render specific unit (OAR). This leads
to some changes on how we program things. Some details :
OAR:
- has its own set of counter registers, they are per-context
saved
Add helper macros for range and equality comparisons and use them to
check with whitelisted registers in oa configurations.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 54 +---
1 file changed, 28 insertions(+), 26 deletions(-)
diff --g
On Thu, Oct 17, 2019 at 07:30:18AM +0100, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2019-10-17 07:11:06)
+static int gen12_emit_oar_config(struct intel_context *ce, bool enable)
+{
+ struct i915_request *rq;
+ u32 *cs;
+ int err = 0;
+
+ rq = i915_request_create(
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for
comparing with whitelisted registers
URL : https://patchwork.freedesktop.org/series/68131/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
159038bf586d drm/i915/perf: Add helper macro
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for
comparing with whitelisted registers
URL : https://patchwork.freedesktop.org/series/68131/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/perf: Ad
On 17/10/2019 10:20, Umesh Nerlige Ramappa wrote:
Add helper macros for range and equality comparisons and use them to
check with whitelisted registers in oa configurations.
Signed-off-by: Umesh Nerlige Ramappa
Looks good :
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_p
On 17/10/2019 10:20, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
We want this so we can preempt performance queries and keep the system
responsive even when long running queries are ongoing. We avoid doing
it for all contexts.
v2: use LRI to modify context control (Chris)
v3: use MASK
On 17/10/2019 10:20, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
Also put yourself as the author ;)
And finally put that patch before the other so that we once perf support
is enabled, all the features are there.
Cheers,
-Lionel
We want this so we can preempt performance q
On 2019-10-10 at 17:51:23 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make the ways/sets arrays static cosnt u8 to shrink things a bit.
>
> text data bss dec hex filename
> - 23935 629 128 246926074 i915_drv.o
> + 23818 629 128
Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.
Sig
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for
comparing with whitelisted registers
URL : https://patchwork.freedesktop.org/series/68131/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7114 -> Patchwork_14851
===
On Wed, 2019-10-16 at 16:41 -0700, Matt Roper wrote:
> On Wed, Oct 09, 2019 at 10:39:08AM +0300, Stanislav Lisovskiy wrote:
> > Also implemented algorithm for choosing DBuf slice configuration
> > based on active pipes, pipe ratio as stated in BSpec 12716.
> >
> > Now pipe allocation still stays p
On 2019/10/16 下午12:57, Parav Pandit wrote:
+static struct mdev_class_id id_table[] = {
static const
+ { MDEV_ID_VFIO },
I guess you don't need extra braces for each entry.
Since this enum represents MDEV class id, it better to name it as
MDEV_CLASS_ID_VFIO.
(Similar to PCI_VENDOR_ID,
On 2019/10/17 上午12:53, Alex Williamson wrote:
On Wed, 16 Oct 2019 15:31:25 +
Parav Pandit wrote:
-Original Message-
From: Cornelia Huck
Sent: Wednesday, October 16, 2019 3:53 AM
To: Parav Pandit
Cc: Alex Williamson ; Jason Wang
; k...@vger.kernel.org; linux-s...@vger.kernel.org;
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers
URL : https://patchwork.freedesktop.org/series/68135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e5fad9967a15 drm/i915/selftests: Add coverage of mocs registers
-:28: WARNING:FILE_PATH_CHANGES: a
On 22/08/2019 13:09, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-22 13:05:06)
Hi,
On 8/21/2019 11:41 PM, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-21 07:32:22)
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
Only this (currently) still requires struct
Normally, we try and skip submission if ELSP[1] is filled. However, we
may desire to enable timeslicing due to the queue priority, even if
ELSP[1] itself does not require timeslicing. That is the queue is equal
priority to ELSP[0] and higher priority then ELSP[1]. Previously, we
would wait until th
The locks (active.lock and rq->lock) need to be taken with disabled
interrupts. This is done in i915_request_retire() by disabling the
interrupts independently of the locks itself.
While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla
it does not on PREEMPT_RT.
Chris Wilson confir
Quoting Sebastian Andrzej Siewior (2019-10-17 09:40:01)
> The locks (active.lock and rq->lock) need to be taken with disabled
> interrupts. This is done in i915_request_retire() by disabling the
> interrupts independently of the locks itself.
> While local_irq_disable()+spin_lock() equals spin_lock
On Thu, 17 Oct 2019 16:30:43 +0800
Jason Wang wrote:
> On 2019/10/17 上午12:53, Alex Williamson wrote:
> >>> Yet another suggestion: have the class id derive from the function
> >>> you use to set up the ops.
> >>>
> >>> void mdev_set_vfio_ops(struct mdev_device *mdev, const struct
> >>> vfio_mdev
On 2019/10/17 下午4:45, Cornelia Huck wrote:
On Thu, 17 Oct 2019 16:30:43 +0800
Jason Wang wrote:
On 2019/10/17 上午12:53, Alex Williamson wrote:
Yet another suggestion: have the class id derive from the function
you use to set up the ops.
void mdev_set_vfio_ops(struct mdev_device *mdev, const
== Series Details ==
Series: drm/i915/execlists: Don't merely skip submission if maybe timeslicing
(rev3)
URL : https://patchwork.freedesktop.org/series/68122/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
30772681eb3d drm/i915/execlists: Don't merely skip submission if maybe
Am 16.10.19 um 16:23 schrieb Daniel Vetter:
> On Wed, Oct 16, 2019 at 3:46 PM Koenig, Christian
> wrote:
>> Am 08.10.19 um 10:55 schrieb Daniel Vetter:
>>> On Wed, Oct 02, 2019 at 08:37:50AM +, Koenig, Christian wrote:
Hi Daniel,
once more a ping on this. Any more comments or ca
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers
URL : https://patchwork.freedesktop.org/series/68135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7114 -> Patchwork_14852
Summary
---
Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.
Sig
== Series Details ==
Series: drm/i915/execlists: Don't merely skip submission if maybe timeslicing
(rev3)
URL : https://patchwork.freedesktop.org/series/68122/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7114 -> Patchwork_14853
==
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
This next step is to eliminate usage of i915->engines[] from the
for_each_engine_m
From: Tvrtko Ursulin
Where the function, or code segment, operates on intel_gt, we need to
start passing it instead of i915 to for_each_engine(_masked).
This is another partial step in migration of i915->engines[] to
gt->engines[].
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/g
Normally, we try and skip submission if ELSP[1] is filled. However, we
may desire to enable timeslicing due to the queue priority, even if
ELSP[1] itself does not require timeslicing. That is the queue is equal
priority to ELSP[0] and higher priority then ELSP[1]. Previously, we
would wait until th
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
This next step is to eliminate usage of i915->engines[] from the
for_each_engine_m
Quoting Tvrtko Ursulin (2019-10-17 10:44:59)
> From: Tvrtko Ursulin
>
> Medium term goal is to eliminate the i915->engine[] array and to get there
> we have recently introduced equivalent array in intel_gt. Now we need to
> migrate the code further towards this state.
>
> This next step is to el
Quoting Tvrtko Ursulin (2019-10-17 10:45:00)
> From: Tvrtko Ursulin
>
> Where the function, or code segment, operates on intel_gt, we need to
> start passing it instead of i915 to for_each_engine(_masked).
>
> This is another partial step in migration of i915->engines[] to
> gt->engines[].
>
>
== Series Details ==
Series: drm/i915/selftests: Teach requests to use all available engines
URL : https://patchwork.freedesktop.org/series/68100/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7109_full -> Patchwork_14837_full
==
Now you're making me looks silly and reply to myself. :))
On 17/10/2019 10:57, Chris Wilson wrote:
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further
Hi all:
There are hardwares that can do virtio datapath offloading while
having its own control path. This path tries to implement a mdev based
unified API to support using kernel virtio driver to drive those
devices. This is done by introducing a new mdev transport for virtio
(virtio_mdev) and re
Mdev bus only supports vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
the first driver could be virtio-mdev. This means we need to add
device class id support in bus match method to pair the mdev device
and mdev driver correctly.
Currently, except for the create and remove, the rest of
mdev_parent_ops is designed for vfio-mdev driver only and may not help
for kernel mdev driver. With the help of class id, this patch
introduces device specific callbacks inside mdev_device
structure. This allows different set of callback to b
Add support to parse mdev class id table.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/vfio_mdev.c | 2 ++
scripts/mod/devicetable-offsets.c | 3 +++
scripts/mod/file2alias.c | 10 ++
3 files changed, 15 insertions(+)
diff --git a/drivers/vfio/mdev/vfio_mdev.c b/driver
This patch introduces a new mdev transport for virtio. This is used to
use kernel virtio driver to drive the mediated device that is capable
of populating virtqueue directly.
A new virtio-mdev driver will be registered to the mdev bus, when a
new virtio-mdev device is probed, it will register the
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c | 12 +++
include/linux/mdev.h | 4 +
include/linux/virtio_mdev.h | 151 ++
3 fil
This sample driver creates mdev device that simulate virtio net device
over virtio mdev transport. The device is implemented through vringh
and workqueue. A device specific dma ops is to make sure HVA is used
directly as the IOVA. This should be sufficient for kernel virtio
driver to work.
Only 'v
On Wed, Oct 16, 2019 at 02:59:45PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjala
> >Sent: Wednesday, October 16, 2019 12:36 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Mun, Gwan-gyeong ; Shankar, Uma
> >
> >Subject: [PATCH] drm/i915: Fix MST oops due to
On 10/17/2019 2:05 PM, Tvrtko Ursulin wrote:
On 22/08/2019 13:09, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-22 13:05:06)
Hi,
On 8/21/2019 11:41 PM, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-21 07:32:22)
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
PIN_MAPPABL
On Thu, Oct 17, 2019 at 01:28:29PM +0530, Ramalingam C wrote:
> On 2019-10-10 at 17:51:23 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make the ways/sets arrays static cosnt u8 to shrink things a bit.
> >
> > text data bss dec hex filename
> > - 23935
On 17/10/2019 13:52, Animesh Manna wrote:
On 10/17/2019 2:05 PM, Tvrtko Ursulin wrote:
On 22/08/2019 13:09, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-22 13:05:06)
Hi,
On 8/21/2019 11:41 PM, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-21 07:32:22)
+ vma = i915_gem_obje
Instead of unconditionally verifying the cursor plane, handle it in the
same way as any other plane, and use our existing api to verify.
While at it, ensure that on gen9+ we verify active_planes mask as well.
This should give the correct results for planar YUV planes too, as we
update active_plane
Use this in all the places where we try to acquire planes after the planes
atomic_check().
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
but seems like it will be in the future. To add some paranoia, add all planes
rather than active planes, because of bigjoiner and
intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.
intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.
intel_atomic_check() defi
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 --
drivers/gpu/dr
Split up plane_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:
@@
struct intel_plane_state *T;
identifier x;
@@
-T->base.x
+T->uapi.x
@@
struct intel_plane_state *T;
@@
-T->base
+T->uapi
Signed-off-by: Maarten Lankhors
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead.
Changes since v1:
- Move to before uapi/hw split.
- Add hunks for intel_pm.c as well.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16
.
Splitting plane state is easier than splitting crtc_state,
before plane check we copy the drm properties to hw so we can
do the same in bigjoiner later on.
We copy the state after we did all the modeset handling, but fortunately
i915 seems to be split correctly and nothing during modeset looks
at
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
@@
struct intel_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x
@@
struct drm_crtc_state *T;
identifier x =~
"^(active|enable|degam
Now that we split plane_state which I didn't want to do yet, we can
program the slave plane without requiring the master plane.
This is useful for programming bigjoiner slave planes as well. We
will no longer need the master's plane_state.
Changes since v1:
- set src/dst rectangles after copy_uap
get_crtc_from_states() is called before plane_state is copied to uapi,
so use the uapi state there.
intel_legacy_cursor_update() could probably get away with looking at
the hw state, but for clarity look at the uapi state always
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/
Split up plane_state->base to hw. This is done using the following patch:
@@
struct intel_plane_state *T;
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
@@
-T->base.x
+T->hw.x
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_ato
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Changes since v1:
- Copy all blobs immediate
On 2019-10-17 at 15:54:46 +0300, Ville Syrjälä wrote:
> On Thu, Oct 17, 2019 at 01:28:29PM +0530, Ramalingam C wrote:
> > On 2019-10-10 at 17:51:23 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Make the ways/sets arrays static cosnt u8 to shrink things a bit.
> > >
> > >
On Thu, Oct 17, 2019 at 03:20:52PM +0200, Maarten Lankhorst wrote:
> Instead of unconditionally verifying the cursor plane, handle it in the
> same way as any other plane, and use our existing api to verify.
>
> While at it, ensure that on gen9+ we verify active_planes mask as well.
> This should
On 16/10/2019 19:56, Chris Wilson wrote:
Since the GGTT fault will overlap with the pwrite access, there is no
implicit moment at which the kernel will automagically flush the backing
store. Userspace has to be explicit in its domain control, or do itself.
Bugzilla: https://bugs.freedesktop.org
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
This next step is to eliminate usage of i915->engines[] from the
for_each_engine_m
Quoting Tvrtko Ursulin (2019-10-17 14:45:31)
> From: Tvrtko Ursulin
>
> Medium term goal is to eliminate the i915->engine[] array and to get there
> we have recently introduced equivalent array in intel_gt. Now we need to
> migrate the code further towards this state.
>
> This next step is to el
On 10/17/2019 6:39 PM, Tvrtko Ursulin wrote:
On 17/10/2019 13:52, Animesh Manna wrote:
On 10/17/2019 2:05 PM, Tvrtko Ursulin wrote:
On 22/08/2019 13:09, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-22 13:05:06)
Hi,
On 8/21/2019 11:41 PM, Chris Wilson wrote:
Quoting Animesh Manna (
Hi Dave and Daniel,
Here goes drm-intel-fixes-2019-10-17:
- Display fix on handling VBT information.
- Important circular locking fix
- Fix for preemption vs resubmission on virtual requests
- and a prep patch to make this last one to apply cleanly
Thanks,
Rodrigo.
The following changes since
Op 17-10-2019 om 15:37 schreef Ville Syrjälä:
> On Thu, Oct 17, 2019 at 03:20:52PM +0200, Maarten Lankhorst wrote:
>> Instead of unconditionally verifying the cursor plane, handle it in the
>> same way as any other plane, and use our existing api to verify.
>>
>> While at it, ensure that on gen9+ w
Dynamic subtests!
Signed-off-by: Chris Wilson
---
lib/i915/gem_context.c| 40 +
lib/i915/gem_context.h| 2 +
tests/Makefile.sources| 1 +
tests/i915/sysfs_preemption_timeout.c | 203 ++
tests/meson.build
On 17/10/2019 14:53, Animesh Manna wrote:
On 10/17/2019 6:39 PM, Tvrtko Ursulin wrote:
On 17/10/2019 13:52, Animesh Manna wrote:
On 10/17/2019 2:05 PM, Tvrtko Ursulin wrote:
On 22/08/2019 13:09, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-22 13:05:06)
Hi,
On 8/21/2019 11:41 PM, Chr
== Series Details ==
Series: drm/i915: Don't disable interrupts independently of the lock (rev3)
URL : https://patchwork.freedesktop.org/series/59289/
State : failure
== Summary ==
Applying: drm/i915: Don't disable interrupts independently of the lock
Using index info to reconstruct a base tre
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev2)
URL : https://patchwork.freedesktop.org/series/68135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
716eba73b16f drm/i915/selftests: Add coverage of mocs registers
-:28: WARNING:FILE_PATH_CHA
On Thu, 17 Oct 2019 18:48:33 +0800
Jason Wang wrote:
> Currently, except for the create and remove, the rest of
> mdev_parent_ops is designed for vfio-mdev driver only and may not help
> for kernel mdev driver. With the help of class id, this patch
> introduces device specific callbacks inside md
== Series Details ==
Series: drm/i915/execlists: Don't merely skip submission if maybe timeslicing
(rev4)
URL : https://patchwork.freedesktop.org/series/68122/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
169736609c98 drm/i915/execlists: Don't merely skip submission if maybe
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev2)
URL : https://patchwork.freedesktop.org/series/68135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7120 -> Patchwork_14855
Summary
Normally, we try and skip submission if ELSP[1] is filled. However, we
may desire to enable timeslicing due to the queue priority, even if
ELSP[1] itself does not require timeslicing. That is the queue is equal
priority to ELSP[0] and higher priority then ELSP[1]. Previously, we
would wait until th
From: Sebastian Andrzej Siewior
The locks (active.lock and rq->lock) need to be taken with disabled
interrupts. This is done in i915_request_retire() by disabling the
interrupts independently of the locks itself.
While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla
it does not
On Thu, Oct 17, 2019 at 01:35:20AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Correct the PCH type in irq postinstall
> URL : https://patchwork.freedesktop.org/series/68116/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7114 -> Patchwork_148
From: Tvrtko Ursulin
It sounds like the hardware only needs the DSB object to be in global GTT
and not in the mappable region.
Signed-off-by: Tvrtko Ursulin
Cc: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drive
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: torstai 17. lokakuuta 2019 18.47
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Correct the PCH
> type in irq
> postinstall
>
> On Thu, Oct 17, 2019 at 01:35:2
The locks (active.lock and rq->lock) need to be taken with disabled
interrupts. This is done in i915_request_retire() by disabling the
interrupts independently of the locks itself.
While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla
it does not on PREEMPT_RT.
Chris Wilson confir
On Thu, Oct 17, 2019 at 09:03:20AM -0700, Saarinen, Jani wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Matt
> > Roper
> > Sent: torstai 17. lokakuuta 2019 18.47
> > To: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: C
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
This next step is to eliminate usage of i915->engines[] from the
for_each_engine_m
== Series Details ==
Series: drm/i915/execlists: Don't merely skip submission if maybe timeslicing
(rev4)
URL : https://patchwork.freedesktop.org/series/68122/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7120 -> Patchwork_14856
==
Normally, we try and skip submission if ELSP[1] is filled. However, we
may desire to enable timeslicing due to the queue priority, even if
ELSP[1] itself does not require timeslicing. That is the queue is equal
priority to ELSP[0] and higher priority then ELSP[1]. Previously, we
would wait until th
On 16/10/2019 13:52, Chris Wilson wrote:
The request selftests straddle the boundary between checking the driver
and the hardware. They are subject to the quirks of the underlying HW,
but operate on top of the backend abstractions. The tests focus on the
scheduler elements and so should check fo
On 10/14/19 3:04 PM, Patchwork wrote:
== Series Details ==
Series: series starting with [v3,1/3] drm/i915: Add microcontrollers
documentation section
URL : https://patchwork.freedesktop.org/series/67986/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7090 -> Patchwork_1479
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 65 +++---
drivers/gpu/drm/i915/gem/i
Convert shmem to an intel_memory_region.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 7 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 74 ++-
From: Abdiel Janulgue
Exposes available regions for the platform. Needed in later patches.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 insertions(+)
diff --
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 56 ---
drivers/gpu/drm/i915/intel_memor
== Series Details ==
Series: mdev based hardware virtio offloading support (rev5)
URL : https://patchwork.freedesktop.org/series/66989/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2d2711d83299 mdev: class id support
335f12f84dd7 modpost: add support for mdev class id
1c27243b
On Thu, 17 Oct 2019 17:07:55 +0200
Cornelia Huck wrote:
> On Thu, 17 Oct 2019 18:48:33 +0800
> Jason Wang wrote:
>
> > Currently, except for the create and remove, the rest of
> > mdev_parent_ops is designed for vfio-mdev driver only and may not help
> > for kernel mdev driver. With the help of
On Thu, 17 Oct 2019 18:48:34 +0800
Jason Wang wrote:
> This patch implements basic support for mdev driver that supports
> virtio transport for kernel virtio driver.
>
> Signed-off-by: Jason Wang
> ---
> drivers/vfio/mdev/mdev_core.c | 12 +++
> include/linux/mdev.h | 4 +
> includ
== Series Details ==
Series: series starting with [01/14] drm/i915: Rework watermark readout to use
plane api
URL : https://patchwork.freedesktop.org/series/68154/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aaabe4f7c23f drm/i915: Rework watermark readout to use plane api
4a
== Series Details ==
Series: mdev based hardware virtio offloading support (rev5)
URL : https://patchwork.freedesktop.org/series/66989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14857
Summary
---
== Series Details ==
Series: series starting with [01/14] drm/i915: Rework watermark readout to use
plane api
URL : https://patchwork.freedesktop.org/series/68154/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14858
==
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