Copy across the engine->uncore shortcut to the virtual_engine from its
first physical engine, similar to the handling of the engine->gt
backpointer.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/int
Set up the engine->uncore shortcut on mock_engine creation.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/mock_engine.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index 5d43cbc3f345..3d88397c0dbb 10
On Mon, Oct 07, 2019 at 06:37:48PM +, Patchwork wrote:
> == Series Details ==
>
> Series: DC3CO Support for TGL test with DC3CO IGT (rev2)
> URL : https://patchwork.freedesktop.org/series/67525/
> State : failure
Thanks for the patches merged to -dinq. For the failure see below.
>
> == Su
== Series Details ==
Series: drm/i915/execlists: Assign virtual_engine->uncore from first sibling
URL : https://patchwork.freedesktop.org/series/67719/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7030 -> Patchwork_14698
S
Thanks Imre for merging the patches 😊
-Original Message-
From: Imre Deak
Sent: Tuesday, October 8, 2019 1:59 PM
To: intel-gfx@lists.freedesktop.org; Gupta, Anshuman
; Vudum, Lakshminarayana
Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for DC3CO Support for TGL test
with DC3CO IGT (
CI bug log filter is updated for Bug 108686 to associate dmesg-fail as well.
Lakshmi.
-Original Message-
From: Gupta, Anshuman
Sent: Tuesday, October 8, 2019 11:40 AM
To: Deak, Imre ; intel-gfx@lists.freedesktop.org; Vudum,
Lakshminarayana
Subject: RE: [Intel-gfx] ✗ Fi.CI.IGT: failure
On Thu, Aug 29, 2019 at 04:29:14PM +0200, Christian König wrote:
> This patch is a stripped down version of the locking changes
> necessary to support dynamic DMA-buf handling.
>
> For compatibility we cache the DMA-buf mapping as soon as
> exporter/importer disagree on the dynamic handling.
Nee
== Series Details ==
Series: drm/i915/selftests: Assign the engine->uncore shortcut
URL : https://patchwork.freedesktop.org/series/67720/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7030 -> Patchwork_14699
Summary
---
On Wed, Oct 02, 2019 at 08:37:50AM +, Koenig, Christian wrote:
> Hi Daniel,
>
> once more a ping on this. Any more comments or can we get it comitted?
Sorry got a bit smashed past weeks, but should be resurrected now back
from xdc.
-Daniel
>
> Thanks,
> Christian.
>
> Am 24.09.19 um 11:50 s
Quoting Matthew Auld (2019-10-04 18:04:33)
> +int
> +i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
> +{
> + struct intel_memory_region *mem = obj->mm.region;
> + struct list_head *blocks = &obj->mm.blocks;
> + unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
> +
Quoting Matthew Auld (2019-10-04 18:04:34)
> @@ -98,10 +103,12 @@ i915_gem_object_get_pages_buddy(struct
> drm_i915_gem_object *obj)
> }
>
> void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
> - struct intel_memory_region *mem)
> +
Quoting Matthew Auld (2019-10-04 18:04:35)
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h
> b/drivers/gpu/drm/i915/intel_memory_region.h
> index 29b86ca17dd9..323270a1ef67 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -
Quoting Matthew Auld (2019-10-04 18:04:36)
> From: Abdiel Janulgue
>
> Exposes available regions for the platform. Shared memory will
> always be available.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/
On 08/10/2019 08:11, Chris Wilson wrote:
Set up the engine->uncore shortcut on mock_engine creation.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/mock_engine.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/moc
On 08/10/2019 08:03, Chris Wilson wrote:
Copy across the engine->uncore shortcut to the virtual_engine from its
first physical engine, similar to the handling of the engine->gt
backpointer.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
1 file changed, 1 insertio
On Mon, 07 Oct 2019, Adam Jackson wrote:
> On Mon, 2019-10-07 at 12:08 +0300, Jani Nikula wrote:
>
>> The problem with the EDID quirks is that exposing the quirks sticks out
>> like a sore thumb. Thus far all of it has been contained in drm_edid.c
>> and they affect how the EDID gets parsed, for a
On Thu, Aug 29, 2019 at 04:29:15PM +0200, Christian König wrote:
> This way we can even pipeline imported BO evictions.
>
> v2: Limit this to only cases when the parent object uses a separate
> reservation object as well. This fixes another OOM problem.
>
> Signed-off-by: Christian König
Si
Add description of wakeref member of intel_shared_dpll
structure to documentation.
Cc: Lucas De Marchi
Cc: Vivek Kasireddy
Signed-off-by: Anna Karas
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpl
On Wed, Oct 02, 2019 at 06:14:19PM +0200, Thierry Reding wrote:
> On Mon, Sep 23, 2019 at 04:52:02PM +0200, Thierry Reding wrote:
> > On Mon, Sep 23, 2019 at 04:52:50PM +0300, Jani Nikula wrote:
> > > On Fri, 20 Sep 2019, Thierry Reding wrote:
> > > > On Mon, Sep 02, 2019 at 01:31:00PM +0200, Thie
== Series Details ==
Series: drm/i915: Describe structure member in documentation (rev2)
URL : https://patchwork.freedesktop.org/series/67102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7032 -> Patchwork_14700
Summary
--
== Series Details ==
Series: drm/i915/execlists: Assign virtual_engine->uncore from first sibling
URL : https://patchwork.freedesktop.org/series/67719/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7030_full -> Patchwork_14698_full
=
A common bane of ours is arbitrary delays in ksoftirqd processing our
submission tasklet. Give the submission tasklet a kick before we wait to
avoid those delays eating into a tight timeout.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 +-
drivers/gpu/drm/i915
Since we time how long it takes for the waiter to be woken upon
injecting the hang, we want to avoid as much distractions as possible
along the critical path.
Signed-off-by: Chris Wilson
---
tests/i915/gem_eio.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a
On Fri, Oct 04, 2019 at 03:14:48PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, move the variable to dev_priv, and extract the
> setting to an initial setup function. While we're at it, update the if
> ladder to follow the
On 08/10/2019 09:59, Chris Wilson wrote:
Quoting Matthew Auld (2019-10-04 18:04:33)
+int
+i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ struct list_head *blocks = &obj->mm.blocks;
+ unsigned int flags =
Quoting Matthew Auld (2019-10-08 12:57:50)
> On 08/10/2019 09:59, Chris Wilson wrote:
> > Quoting Matthew Auld (2019-10-04 18:04:33)
> >> +int
> >> +i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
> >> +{
> >> + struct intel_memory_region *mem = obj->mm.region;
> >> + s
On Mon, 07 Oct 2019, Jani Nikula wrote:
> Move intel_power_domains_init_hw() call one level higher, to be on the
> same level as all the other intel_power_domains_*() calls in the
> probe/remove paths.
>
> This also moves the power domain hw init earlier in the sequence, along
> with the dependent
== Series Details ==
Series: drm/i915/gt: Flush submission tasklet before waiting/retiring
URL : https://patchwork.freedesktop.org/series/67732/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7032 -> Patchwork_14701
Summary
== Series Details ==
Series: drm/i915/selftests: Assign the engine->uncore shortcut
URL : https://patchwork.freedesktop.org/series/67720/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7030_full -> Patchwork_14699_full
Summa
From: Lionel Landwerlin
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
a
On 08/10/2019 17:01, Chris Wilson wrote:
From: Lionel Landwerlin
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no
== Series Details ==
Series: drm/i915/perf: drop list of streams
URL : https://patchwork.freedesktop.org/series/67734/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/perf: drop list of streams
+drivers/gpu/drm/i915/i915_perf.c:1408:15: warning
Couple up our mock_uncore to know about the fake global device and its
runtime powermanagement.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/mock_engine.c| 1 +
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_u
On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> A common bane of ours is arbitrary delays in ksoftirqd processing our
> submission tasklet. Give the submission tasklet a kick before we wait
> to
> avoid those delays eating into a tight timeout.
>
> Signed-off-by: Chris Wilson
> ---
> dr
On Mon, Oct 07, 2019 at 03:12:00PM -0700, dbasehore . wrote:
> On Mon, Oct 7, 2019 at 9:38 AM Sean Paul wrote:
> >
> > On Wed, Sep 25, 2019 at 03:58:30PM -0700, Derek Basehore wrote:
> > > This adds a helper function for reading the rotation (panel
> > > orientation) from the device tree.
> > >
>
Quoting Summers, Stuart (2019-10-08 15:52:15)
> On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> > A common bane of ours is arbitrary delays in ksoftirqd processing our
> > submission tasklet. Give the submission tasklet a kick before we wait
> > to
> > avoid those delays eating into a tigh
Quoting Summers, Stuart (2019-10-08 15:52:15)
> On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> > A common bane of ours is arbitrary delays in ksoftirqd processing our
> > submission tasklet. Give the submission tasklet a kick before we wait
> > to
> > avoid those delays eating into a tigh
/snip
> > > > > diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> > > > > index d16158deacdc..f3587a54b8ac 100644
> > > > > --- a/include/drm/drm_panel.h
> > > > > +++ b/include/drm/drm_panel.h
> > > > > @@ -141,6 +141,56 @@ struct drm_panel {
> > > > >*/
> > > > > con
== Series Details ==
Series: drm/i915: Describe structure member in documentation (rev2)
URL : https://patchwork.freedesktop.org/series/67102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7032_full -> Patchwork_14700_full
On Tue, 2019-10-08 at 15:56 +0100, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-10-08 15:52:15)
> > On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> > > A common bane of ours is arbitrary delays in ksoftirqd processing
> > > our
> > > submission tasklet. Give the submission tasklet a
== Series Details ==
Series: drm/i915/perf: drop list of streams
URL : https://patchwork.freedesktop.org/series/67734/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7033 -> Patchwork_14702
Summary
---
**FAILURE**
On Tue, 8 Oct 2019 at 15:50, Chris Wilson wrote:
>
> Couple up our mock_uncore to know about the fake global device and its
> runtime powermanagement.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
Thanks,
Reviewed-by: Matthew Auld
___
Intel-gfx
On Tue, 2019-10-01 at 14:54 +0100, Chris Wilson wrote:
> CI is still unstable whenever we enable more than one engine, and we
> have not yet found a better hack than restricting it to using just
> rcs0.
>
> However, to allow testing to continue on the other engines by
> developers, we allow the av
On Tue, 2019-10-01 at 14:54 +0100, Chris Wilson wrote:
> Allow the user to restrict the available set of engines via a module
> parameter.
>
> Signed-off-by: Chris Wilson
> Cc: Stuart Summers
> Cc: Andi Shyti
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Martin Peres
== Series Details ==
Series: drm/i915/selftests: Assign the intel_runtime_pm pointer for mock_uncore
URL : https://patchwork.freedesktop.org/series/67736/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7033 -> Patchwork_14703
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of
Some kernel internal objects may need to be allocated as a contiguous
block, also thinking ahead the various kernel io_mapping interfaces seem
to expect it, although this is purely a limitation in the kernel
API...so perhaps something to be improved.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtine
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded. This is limited to kernel
internal objects.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Reviewed-by: Chris Wilson
---
drivers/gpu/d
First block of patches from the 'LMEM basics' series.
Matthew Auld (3):
drm/i915: introduce intel_memory_region
drm/i915/region: support contiguous allocations
drm/i915/region: support volatile objects
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem
Quoting Matthew Auld (2019-10-08 17:01:14)
> +static void close_objects(struct intel_memory_region *mem,
> + struct list_head *objects)
> +{
> + struct drm_i915_private *i915 = mem->i915;
> + struct drm_i915_gem_object *obj, *on;
> +
> + list_for_each_entry
Quoting Matthew Auld (2019-10-08 17:01:15)
> Some kernel internal objects may need to be allocated as a contiguous
> block, also thinking ahead the various kernel io_mapping interfaces seem
> to expect it, although this is purely a limitation in the kernel
> API...so perhaps something to be improve
This slightly simplifies the EHL DPLL4 handling and also gives us more
flexibility in the future in case we need to skip the use of specific
PLL's (e.g., due to hardware workarounds and such).
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 42 +
From: Ville Syrjälä
VLV/CHV sprite planes also support the C8 format. Let's expose that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i9
From: Ville Syrjälä
The spec says that color keying and HDR mode are mutually exclusive.
So let's not enable HDR mode when color keying is active.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +
drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
ICL+ again supports alpha blending with 10bpc pixel formats.
Expose them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i9
From: Ville Syrjälä
Lots of redundant assignments inside intel_primary_plane_create().
Get rid of them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 43 +++-
1 file changed, 14 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/
From: Ville Syrjälä
Let's try to keep the pixel format arrays somewhat sorted:
1. RGB before YUV
2. smaller bpp before larger bpp
3. X before A
4. RGB before BGR
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c
From: Ville Syrjälä
SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose
them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/driver
From: Ville Syrjälä
Currently we expose VLV/CHV alpha blending only on the sprite
planes, but the primary planes can do it as well. Let's flip
it on.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 57 +++-
drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
On VLV and CHV pipe A/C these are only supported by the the primary
plane. Add the require bits to expose the new formats.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 33
From: Ville Syrjälä
According to the spec color keying is not supported with
fp16 pixel formats on skl+. Reject that combo.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/
On Tue, Oct 08, 2019 at 09:12:52AM -0700, Matt Roper wrote:
This slightly simplifies the EHL DPLL4 handling and also gives us more
flexibility in the future in case we need to skip the use of specific
PLL's (e.g., due to hardware workarounds and such).
Cc: Lucas De Marchi
Signed-off-by: Matt Ro
On Tue, Oct 08, 2019 at 09:12:52AM -0700, Matt Roper wrote:
> This slightly simplifies the EHL DPLL4 handling and also gives us more
> flexibility in the future in case we need to skip the use of specific
> PLL's (e.g., due to hardware workarounds and such).
>
> Cc: Lucas De Marchi
> Signed-off-b
On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> in __lock_release"), @nested is no longer used in lock_release(), so
> remove it from all lock_release() calls and friends.
>
> Signed-off-by: Qian Cai
Ack on the
On Tue, Oct 08, 2019 at 07:28:45PM +0300, Ville Syrjälä wrote:
On Tue, Oct 08, 2019 at 09:12:52AM -0700, Matt Roper wrote:
This slightly simplifies the EHL DPLL4 handling and also gives us more
flexibility in the future in case we need to skip the use of specific
PLL's (e.g., due to hardware wor
== Series Details ==
Series: drm/i915/gt: Flush submission tasklet before waiting/retiring
URL : https://patchwork.freedesktop.org/series/67732/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7032_full -> Patchwork_14701_full
On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
> Use this in all the places where we try to acquire planes after the planes
> atomic_check().
>
> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
> but seems like it will be in the future. To add some
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified ge
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Rev
This slightly simplifies the EHL DPLL4 handling and also gives us more
flexibility in the future in case we need to skip the use of specific
PLL's (e.g., due to hardware workarounds and such).
v2:
- Replace GENMASK() with or'd BIT()'s to make the specific DPLLs more
explicit. (Ville)
- s/uns
== Series Details ==
Series: intel_memory_region bits
URL : https://patchwork.freedesktop.org/series/67738/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
46562367c0c6 drm/i915: introduce intel_memory_region
-:60: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
On Fri, Oct 04, 2019 at 01:35:02PM +0200, Maarten Lankhorst wrote:
> Splitting plane state is easier than splitting crtc_state,
> before plane check we copy the drm properties to hw so we can
> do the same in bigjoiner later on.
>
> We copy the state after we did all the modeset handling, but fort
On Fri, Oct 04, 2019 at 01:35:04PM +0200, Maarten Lankhorst wrote:
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> eDP does not support bigjoiner, so do not expose bigjoiner only
> modes on
== Series Details ==
Series: intel_memory_region bits
URL : https://patchwork.freedesktop.org/series/67738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14704
Summary
---
**SUCCESS**
No regressi
== Series Details ==
Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on
SNB-BDW sprites
URL : https://patchwork.freedesktop.org/series/67741/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14705
==
== Series Details ==
Series: series starting with [CI,v3,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67743/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b44bcf0ca073 drm/i915: Move SAGV block time to dev_priv
-:61: WARNING:UN
Assign a separate lockclass to the perma-pinned timelines of the
kernel_context, such that we can use them from within the user timelines
should we ever need to inject GPU operations to fixup faults during
request construction.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Auld
---
== Series Details ==
Series: series starting with [CI,v3,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67743/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14706
===
== Series Details ==
Series: drm/i915: Select DPLL's via mask (rev2)
URL : https://patchwork.freedesktop.org/series/67740/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14707
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/selftests: Assign the intel_runtime_pm pointer for mock_uncore
URL : https://patchwork.freedesktop.org/series/67736/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7033_full -> Patchwork_14703_full
==
On Fri, Oct 04, 2019 at 01:35:05PM +0200, Maarten Lankhorst wrote:
> When the clock is higher than the dotclock, try with 2 pipes enabled.
> If we can enable 2, then we will go into big joiner mode, and steal
> the adjacent crtc.
>
> This only links the crtc's in software, no hardware or plane
> p
On Tue, Oct 08, 2019 at 06:33:51PM +0200, Daniel Vetter wrote:
> On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> > Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> > in __lock_release"), @nested is no longer used in lock_release(), so
> > remove it from all lock
== Series Details ==
Series: drm/i915/gt: Give engine->kernel_context distinct timeline lock classes
URL : https://patchwork.freedesktop.org/series/67748/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14708
== Series Details ==
Series: drm/i915: Select DPLL's via mask (rev3)
URL : https://patchwork.freedesktop.org/series/67740/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14709
Summary
---
**SUCCESS**
On Tue, 8 Oct 2019 at 19:59, Chris Wilson wrote:
>
> Assign a separate lockclass to the perma-pinned timelines of the
> kernel_context, such that we can use them from within the user timelines
> should we ever need to inject GPU operations to fixup faults during
> request construction.
>
> Signed-
Gen11+ has more hardware planes than gen9 so we need to test additional
pipe interrupt register bits to recognize any GTT faults that happen on
these extra planes.
Bspec: 50335
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 4 +++-
drivers/gpu/drm/i915/i915_reg.h | 8
2
Quoting Patchwork (2019-10-08 19:17:44)
> == Series Details ==
>
> Series: intel_memory_region bits
> URL : https://patchwork.freedesktop.org/series/67738/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14704
> ===
This is Lionel's work to enable OA for Vulkan, greatly bastardised on
top of the struct_mutex removal. It claims to be doing the right
thing...
-Chris
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From: Lionel Landwerlin
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content throu
From: Lionel Landwerlin
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buff
From: Lionel Landwerlin
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace
From: Lionel Landwerlin
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be
From: Lionel Landwerlin
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as def
From: Lionel Landwerlin
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
driv
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 29 +++---
drivers/gpu/drm/i915/i915_perf_types.h |
From: Lionel Landwerlin
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. T
From: Lionel Landwerlin
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-
In TGL there we are missing the initialization of port G.
Do the same as for other ports.
Signed-off-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_bios.c | 4
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
drivers/gpu/drm/i915/display/intel_display.h | 1 +
d
== Series Details ==
Series: drm/i915: Catch GTT fault errors for gen11+ planes
URL : https://patchwork.freedesktop.org/series/67752/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7036 -> Patchwork_14710
Summary
---
== Series Details ==
Series: series starting with [1/9] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67754/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f9a4f9fef858 drm/i915/perf: store the associated engine of a strea
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