Hi Alastair,
Thanks for your patch!
On Wed, May 8, 2019 at 9:04 AM Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> Some buffers may only be partially filled with useful data, while the rest
> is padded (typically with 0x00 or 0xff).
>
> This patch introduces a flag to allow the supression
"ret" is uninitialized on this path but it should be -EINVAL.
Fixes: 930c8dfea4b8 ("drm/i915/gvt: Check if get_next_pt_type() always returns
a valid value")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/i915/gvt/gtt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/dri
On Mon, May 13, 2019 at 11:02 AM Paul Kocialkowski
wrote:
>
> Hi,
>
> On Fri, 2019-05-10 at 16:54 +0200, Daniel Vetter wrote:
> > On Fri, May 10, 2019 at 2:12 PM Paul Kocialkowski
> > wrote:
> > > Hi,
> > >
> > > On Tue, 2019-05-07 at 21:57 +0530, Ramalingam C wrote:
> > > > DRM API for generatin
Hi,
On Fri, 2019-05-10 at 16:54 +0200, Daniel Vetter wrote:
> On Fri, May 10, 2019 at 2:12 PM Paul Kocialkowski
> wrote:
> > Hi,
> >
> > On Tue, 2019-05-07 at 21:57 +0530, Ramalingam C wrote:
> > > DRM API for generating uevent for a status changes of connector's
> > > property.
> > >
> > > Thi
== Series Details ==
Series: drm/i915/gvt: Fix an error code in ppgtt_populate_spt_by_guest_entry()
URL : https://patchwork.freedesktop.org/series/60572/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6073 -> Patchwork_13005
On Mon, 2019-05-13 at 11:34 +0200, Daniel Vetter wrote:
> On Mon, May 13, 2019 at 11:02 AM Paul Kocialkowski
> wrote:
> > Hi,
> >
> > On Fri, 2019-05-10 at 16:54 +0200, Daniel Vetter wrote:
> > > On Fri, May 10, 2019 at 2:12 PM Paul Kocialkowski
> > > wrote:
> > > > Hi,
> > > >
> > > > On Tue,
Op 03-05-2019 om 21:08 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> ICL has so many planes that it can easily exceed the maximum
> effective memory bandwidth of the system. We must therefore check
> that we don't exceed that limit.
>
> The algorithm is very magic number heavy and lacks suffici
== Series Details ==
Series: drm/i915/gvt: Fix an error code in ppgtt_populate_spt_by_guest_entry()
URL : https://patchwork.freedesktop.org/series/60572/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6073_full -> Patchwork_13005_full
===
In all likelihood, the priority and node are already in the CPU cache
and by checking them first, we can avoid having to chase the
*request->hwsp for the current breadcrumb.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_scheduler.c | 4
To avoid pulling in a forward declaration in the next patch, move the
i915_sched_node handling to after the main dfs of the scheduler.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_scheduler.c | 210 +-
1 file changed, 105 insertio
To simplify the next patch, update bump_priority and schedule to accept
the internal i915_sched_ndoe directly and not expect a request pointer.
add/remove: 0/0 grow/shrink: 2/1 up/down: 8/-15 (-7)
Function old new delta
i915_schedule_bump_priority
On 10/05/2019 13:33, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:38)
From: Tvrtko Ursulin
After the removal of engine global seqnos and the corresponding
intel_engine_notify tracepoints the script needs to be adjusted to cope
with the new state of things.
To keep working it
On 10/05/2019 13:52, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:40)
From: Tvrtko Ursulin
Add virtual/queue timelines to both stdout and HTML output.
A new timeline is created for each queue/virtual engine to display
associated requests in queued and runnable states. Once re
On 10/05/2019 13:55, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:41)
From: Tvrtko Ursulin
Use the 'completed?' tracepoint field to detect more robustly when a
request has been preempted and remove it from the engine database if so.
Otherwise the script can hit a scenario whe
On 10/05/2019 14:14, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:42)
From: Tvrtko Ursulin
Support i915 virtual engine from gem_wsim (-b i915) and media-bench.pl
Signed-off-by: Tvrtko Ursulin
---
+ /*
+* Create and configure contexts.
+*/
+ for (i
This fixes the issue on my ICL-Y.
On Fri, 2019-05-10 at 17:02 +0300, Imre Deak wrote:
> Add another ICL-Y PCIID that proved to have only 5 ports to the
> corresponding PCIID list.
>
> Meanwhile I'm trying to get a complete list of all PCIIDs with less
> than
> 6 ports and/or get a VBT fix to mark
Quoting Tvrtko Ursulin (2019-05-13 13:41:47)
>
> On 10/05/2019 14:14, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-05-08 13:10:42)
> >> From: Tvrtko Ursulin
> >>
> >> Support i915 virtual engine from gem_wsim (-b i915) and media-bench.pl
> >>
> >> Signed-off-by: Tvrtko Ursulin
> >> ---
>
On 10/05/2019 14:20, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:47)
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/benchmarks/gem_wsim.c
On 10/05/2019 14:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:48)
From: Tvrtko Ursulin
Support new i915 uAPI for configuring contexts with engine maps.
Please refer to the README file for more detailed explanation.
Signed-off-by: Tvrtko Ursulin
---
+static int parse_eng
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Rearrange i915_scheduler.c
URL : https://patchwork.freedesktop.org/series/60577/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6075 -> Patchwork_13006
Sum
On 10/05/2019 14:29, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:50)
From: Tvrtko Ursulin
Parsing an integer workload descriptor field is a common pattern which we
can extract to a helper macro and by doing so further improve the
readability of the main parsing loop.
Signed-
On 10/05/2019 14:36, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:52)
From: Tvrtko Ursulin
Engine bonds are an i915 uAPI applicable to load balanced contexts with
engine map. They allow expression rules of engine selection between two
contexts when submissions are also tied wi
Quoting Tvrtko Ursulin (2019-05-13 14:18:59)
>
> On 10/05/2019 14:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-05-08 13:10:48)
> >> From: Tvrtko Ursulin
> >>
> >> Support new i915 uAPI for configuring contexts with engine maps.
> >>
> >> Please refer to the README file for more detail
Below Sparsh warnings are fixed.
Commit: drm: revocation check at drm subsystem
+drivers/gpu/drm/drm_hdcp.c:235:6: warning: symbol
'drm_hdcp_request_srm' was not declared. Should it be static?
+drivers/gpu/drm/drm_hdcp.c:27:3: warning: symbol 'srm_data' was not
declared. Should it be static?
+driv
From: Ville Syrjälä
When the first C8 plane gets enabled, or the last one gets disabled we
may need to enable/disable the pipe gamma for the other active planes.
Check for that and run through the normal intel_color_check() path.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_disp
From: Ville Syrjälä
Fix toggling between no C8 planes vs. at least one C8 plane.
Test-with: 20190510171900.29593-1-ville.syrj...@linux.intel.com
Ville Syrjälä (2):
drm/i915: Update pipe gamma enable bits when C8 planes are getting
enabled/disabled
drm/i915: Add debugs for the C8 vs. leg
From: Ville Syrjälä
Leave a hint in dmesg when we reject a configuration attempting
to use C8 planes without the legacy LUT loaded.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/in
On 13/05/2019 14:29, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-13 14:18:59)
On 10/05/2019 14:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:48)
From: Tvrtko Ursulin
Support new i915 uAPI for configuring contexts with engine maps.
Please refer to the README file
On Fri, 10 May 2019, Imre Deak wrote:
> Add another ICL-Y PCIID that proved to have only 5 ports to the
> corresponding PCIID list.
>
> Meanwhile I'm trying to get a complete list of all PCIIDs with less than
> 6 ports and/or get a VBT fix to mark these ports non-existant, but until
> then the onl
On 10/05/2019 14:48, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-08 13:10:54)
From: Tvrtko Ursulin
For simulating frame split workloads it is useful to express a batch which
ends at the same time as the parallel submission on the respective bonded
engine. For this we add support for i
On Mon, May 13, 2019 at 04:56:25PM +0300, Jani Nikula wrote:
> On Fri, 10 May 2019, Imre Deak wrote:
> > Add another ICL-Y PCIID that proved to have only 5 ports to the
> > corresponding PCIID list.
> >
> > Meanwhile I'm trying to get a complete list of all PCIIDs with less than
> > 6 ports and/or
Quoting Tvrtko Ursulin (2019-05-13 14:59:01)
>
> On 10/05/2019 14:48, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-05-08 13:10:54)
> > So preemption check interval is given by batch_start - mmap_start.
> > Which is limited to a max of 64 bytes. That might be a bit excessive on
> > the freq
On Fri, May 10, 2019 at 05:42:09PM -0700, Matt Roper wrote:
> On Fri, May 03, 2019 at 10:08:31PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > ICL has so many planes that it can easily exceed the maximum
> > effective memory bandwidth of the system. We must therefore check
> > that
On Wed, May 08, 2019 at 09:05:06PM +, Sripada, Radhakrishna wrote:
> On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > ICL has so many planes that it can easily exceed the maximum
> > effective memory bandwidth of the system. We must therefore check
> > t
On Sat, May 11, 2019 at 3:12 PM Laurent Pinchart
wrote:
>
> Hi Sean,
>
> Thank you for the patch.
>
Hey Laurent,
Thanks for looking!
> On Thu, May 02, 2019 at 03:49:46PM -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > Everyone who implements connector_helper_funcs->atomic_check reaches
> >
On Sat, May 11, 2019 at 10:12:02PM +0300, Laurent Pinchart wrote:
> Hi Sean,
>
> Thank you for the patch.
>
> On Thu, May 02, 2019 at 03:49:46PM -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > Everyone who implements connector_helper_funcs->atomic_check reaches
> > into the connector state
== Series Details ==
Series: drm/hdcp: drm_hdcp_request_srm() as static
URL : https://patchwork.freedesktop.org/series/60580/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/hdcp: drm_hdcp_request_srm() as static
-O:drivers/gpu/drm/drm_hdcp.c:238:6:
On Mon, May 13, 2019 at 10:11:01AM +, Ser, Simon wrote:
> On Mon, 2019-05-13 at 11:34 +0200, Daniel Vetter wrote:
> > On Mon, May 13, 2019 at 11:02 AM Paul Kocialkowski
> > wrote:
> > > Hi,
> > >
> > > On Fri, 2019-05-10 at 16:54 +0200, Daniel Vetter wrote:
> > > > On Fri, May 10, 2019 at 2:1
== Series Details ==
Series: drm/hdcp: drm_hdcp_request_srm() as static
URL : https://patchwork.freedesktop.org/series/60580/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6076 -> Patchwork_13007
Summary
---
**SUCCES
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Jonas
>Karlman
>Sent: Monday, May 13, 2019 1:42 AM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: dcasta...@chromium.org; emil.l.veli...@gmail.
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Rearrange i915_scheduler.c
URL : https://patchwork.freedesktop.org/series/60577/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6075_full -> Patchwork_13006_full
===
== Series Details ==
Series: drm/i915: C8 fix
URL : https://patchwork.freedesktop.org/series/60583/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6077 -> Patchwork_13008
Summary
---
**SUCCESS**
No regressions foun
Hey,
Le lundi 13 mai 2019 à 11:34 +0200, Daniel Vetter a écrit :
> On Mon, May 13, 2019 at 11:02 AM Paul Kocialkowski
> wrote:
> > Hi,
> >
> > On Fri, 2019-05-10 at 16:54 +0200, Daniel Vetter wrote:
> > > On Fri, May 10, 2019 at 2:12 PM Paul Kocialkowski
> > > wrote:
> > > > Hi,
> > > >
> > >
On Thu, May 09, 2019 at 12:08:43AM +0530, Uma Shankar wrote:
> HDR metadata block is introduced in CEA-861.3 spec.
> Parsing the same to get the panel's HDR metadata.
>
> v2: Rebase and added Ville's POC changes to the patch.
>
> v3: No Change
>
> v4: Addressed Shashank's review comments
>
> v5
By disabling a power domain asynchronously we can restrict holding a
reference on that power domain to the actual code sequence that
requires the power to be on for the HW access it's doing, by also
avoiding unneeded on-off-on togglings of the power domain (since the
disabling happens with a delay)
== Series Details ==
Series: drm/hdcp: drm_hdcp_request_srm() as static
URL : https://patchwork.freedesktop.org/series/60580/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6076_full -> Patchwork_13007_full
Summary
---
On Thu, May 09, 2019 at 12:08:46AM +0530, Uma Shankar wrote:
> Enable writing of HDR metadata infoframe to panel.
> The data will be provid by usersapace compositors, based
> on blending policies and passsed to driver through a blob
> property.
>
> v2: Rebase
>
> v3: Fixed a warning message
>
>
== Series Details ==
Series: drm/i915: Add support for asynchronous display power disabling (rev5)
URL : https://patchwork.freedesktop.org/series/60242/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7638893cffd3 drm/i915: Add support for tracking wakerefs w/o power-on guarantee
From: John Harrison
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself must be engine
agnostic - any direct register writes must be relative to the engi
On Thu, May 09, 2019 at 12:08:50AM +0530, Uma Shankar wrote:
> HDR metadata requires a infoframe to be set. Due to fastset,
> full modeset is not performed hence adding it to update_pipe
> to handle that.
>
> Signed-off-by: Uma Shankar
> Reviewed-by: Shashank Sharma
> ---
> drivers/gpu/drm/i915
On Thu, May 09, 2019 at 12:08:48AM +0530, Uma Shankar wrote:
> From: Ville Syrjälä
>
> This patch enables infoframes on GLK+ to be
> used to send HDR metadata to HDMI sink.
>
> v2: Addressed Shashank's review comment.
>
> v3: Addressed Shashank's review comment.
>
> v4: Added Shashank's RB.
>
== Series Details ==
Series: drm/i915: Add support for asynchronous display power disabling (rev5)
URL : https://patchwork.freedesktop.org/series/60242/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add support for tracking wakerefs w/o powe
On Thu, May 09, 2019 at 12:08:52AM +0530, Uma Shankar wrote:
> Added unpack function for DRM infoframe for dynamic
> range and mastering infoframe readout.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Uma Shankar
> ---
> drivers/video/hdmi.c | 54
> +
On Thu, May 09, 2019 at 12:08:53AM +0530, Uma Shankar wrote:
> Added state readout for DRM infoframe and enabled
> state validation for DRM infoframe.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4
> drivers/gpu/drm/i915/intel_display.c | 1 +
> drivers/gpu
== Series Details ==
Series: drm/i915: Add support for asynchronous display power disabling (rev5)
URL : https://patchwork.freedesktop.org/series/60242/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6077 -> Patchwork_13009
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev5)
URL : https://patchwork.freedesktop.org/series/57117/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR d
On Mon, May 13, 2019 at 07:05:04PM +0530, Ramalingam C wrote:
> Below Sparsh warnings are fixed.
>
> Commit: drm: revocation check at drm subsystem
> +drivers/gpu/drm/drm_hdcp.c:235:6: warning: symbol
> 'drm_hdcp_request_srm' was not declared. Should it be static?
> +drivers/gpu/drm/drm_hdcp.c:27:
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice i
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
v3: add intel_* prefix to sseu_subslices_per_slice
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
--
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
v2: add const to sseu_dev_info variable
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file chan
This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
slice * subslice stride + subslice
Move functions to intel_sseu.h and remove inline qualifier.
Additionally, ensure these are all prefixed with intel_sseu_*
to match the convention of other functions in i915.
v2: fix spacing from checkpatch warning
v3: squash helper function changes into a single patch
break 80 character line t
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
v2: update headers in intel_sseu.h
v3: use GEN_SSEU_STRIDE for stride calculations in intel_sseu.h
apply s/bits/max_entries/ to GEN_SSEU_STRIDE parameter
Cc:
From: John Harrison
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself must be engine
agnostic - any direct register writes must be relative to the engi
Doh. Ignore this patch. Forgot to actually squash the self-test fix
down. Will repost the corrected patch.
John.
On 5/13/2019 13:03, Patchwork wrote:
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev5)
URL : https://patchwork.freedesktop.org/series/57117/
State : failure
==
Hi-just wanted to give some general thoughts here.
First off I'm 100% behind the epoch idea, that was one of the ideas I had been
thinking of proposing here in the first place but probably forgot at some
point down the road.
A couple of other things:
* I think it would also probably be good to h
== Series Details ==
Series: Refactor to expand subslice mask (rev9)
URL : https://patchwork.freedesktop.org/series/59742/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4475a01ca163 drm/i915: Use local variable for SSEU info in GETPARAM ioctl
5bdea443d9df drm/i915: Add macro fo
== Series Details ==
Series: Refactor to expand subslice mask (rev9)
URL : https://patchwork.freedesktop.org/series/59742/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Use local variable for SSEU info in GETPARAM ioctl
Okay!
Commit: drm/i9
== Series Details ==
Series: drm/i915: C8 fix
URL : https://patchwork.freedesktop.org/series/60583/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6077_full -> Patchwork_13008_full
Summary
---
**FAILURE**
Serious u
== Series Details ==
Series: Refactor to expand subslice mask (rev9)
URL : https://patchwork.freedesktop.org/series/59742/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6077 -> Patchwork_13011
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev6)
URL : https://patchwork.freedesktop.org/series/57117/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1d0e020ea850 drm/i915: Engine relative MMIO
-:90: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#90
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev6)
URL : https://patchwork.freedesktop.org/series/57117/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6077 -> Patchwork_13012
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Add support for asynchronous display power disabling (rev5)
URL : https://patchwork.freedesktop.org/series/60242/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6077_full -> Patchwork_13009_full
== Series Details ==
Series: Refactor to expand subslice mask (rev9)
URL : https://patchwork.freedesktop.org/series/59742/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6077_full -> Patchwork_13011_full
Summary
---
*
On Mon, 2019-05-13 at 17:16 +0300, Ville Syrjälä wrote:
> On Wed, May 08, 2019 at 09:05:06PM +, Sripada, Radhakrishna
> wrote:
> > On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > ICL has so many planes that it can easily exceed the maximum
> > > e
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev6)
URL : https://patchwork.freedesktop.org/series/57117/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6077_full -> Patchwork_13012_full
Summary
---
**S
On Mon, 2019-05-13 at 17:04 +0200, Daniel Vetter wrote:
> On Mon, May 13, 2019 at 10:11:01AM +, Ser, Simon wrote:
> > On Mon, 2019-05-13 at 11:34 +0200, Daniel Vetter wrote:
> > > On Mon, May 13, 2019 at 11:02 AM Paul Kocialkowski
> > > wrote:
> > > > Hi,
> > > >
> > > > On Fri, 2019-05-10 at
On 2019.05.13 12:22:44 +0300, Dan Carpenter wrote:
> "ret" is uninitialized on this path but it should be -EINVAL.
>
> Fixes: 930c8dfea4b8 ("drm/i915/gvt: Check if get_next_pt_type() always
> returns a valid value")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 4 +++-
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