On 11/04/2019 11:44, Michal Wajdeczko wrote:
> Due to the upcoming changes to the GuC ABI interface, we must
> disable GuC submission mode until final ABI will be available
> on all GuC firmwares.
If I understand correctly, you are disabling command submission by
returning -EIO, which leads to the
On Sat 2019-04-13 09:22:05, Alastair D'Silva wrote:
> > -Original Message-
> > From: Petr Mladek
> > Sent: Friday, 12 April 2019 11:48 PM
> > To: Alastair D'Silva
> > Cc: alast...@d-silva.org; Jani Nikula ;
> Joonas
> > Lahtinen ; Rodrigo Vivi
> > ; David Airlie ; Daniel Vetter
> > ; Kars
On Sat 2019-04-13 09:28:03, Alastair D'Silva wrote:
> > -Original Message-
> > From: Petr Mladek
> > Sent: Saturday, 13 April 2019 12:04 AM
> > To: Alastair D'Silva
> > Cc: alast...@d-silva.org; Jani Nikula ;
> Joonas
> > Lahtinen ; Rodrigo Vivi
> > ; David Airlie ; Daniel Vetter
> > ; Ka
On Sat 2019-04-13 09:31:27, Alastair D'Silva wrote:
> > -Original Message-
> > From: Petr Mladek
> > Sent: Saturday, 13 April 2019 12:12 AM
> > To: Alastair D'Silva
> > Cc: alast...@d-silva.org; Jani Nikula ;
> Joonas
> > Lahtinen ; Rodrigo Vivi
> > ; David Airlie ; Daniel Vetter
> > ; Ka
On Fri, Apr 05, 2019 at 08:41:16AM +0100, Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2019-04-05 08:26:57)
> > From: Janusz Krzysztofik
> >
> > The driver does not currently support unbinding from a device which is
> > in use. Since open file descriptors may still be pointing into kernel
>
On Fri, Apr 05, 2019 at 03:02:34PM +0200, Janusz Krzysztofik wrote:
> From: Janusz Krzysztofik
>
> The driver does not currently support unbinding from a device which is
> in use. Since open file descriptors may still be pointing into kernel
> memory where the device structures used to be, entir
On 4/15/19 5:14 AM, Zhenyu Wang wrote:
On 2019.04.14 17:44:10 +0300, Uri Lublin wrote:
We started looking at the kvmgt driver code when we noticed
the 'size' calculation in qemu-kvm is wrong.
The first fix we had is now already committed upstream
(7f1a93b1f1d1d2603a49a9e4226259db9272f305).
From: Alastair D'Silva
> Sent: 15 April 2019 11:07
...
> In the above example the author only wants the hex output, while in other
> situations, both hex & ASCII output is desirable. If you just want ASCII
> output, the caller should just use a printk or one of it's wrappers.
Hexdump will 'sanitis
Thanks to Jani N, Matt and Ville for the review comments. Hopefully
I have addressed all the current review comments and ready to receive more :)
In this patch series, added state checker to validate gamma_lut values. This
reads hardware state, and compares the originally requested
state to the st
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 51 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c206e8..8f2ae8a 100
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 49e5d8c..6ccb76f 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 6ccb76f..74f000e 100644
--- a/drivers/gpu/drm/i915/intel_color.c
v3: Rebase
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 7 +++
drivers/gpu/drm/i915/intel_color.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 39 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f2ae8a..c9ae61e 100
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f29a348..0fc9dab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 49 +-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d057
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 39 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9ae61e..1d0575f 100
v3: Rebase
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 49
drivers/gpu/drm/i915/intel_color.h | 6 +
drivers/gpu/drm/i915/intel_display.c | 10
3 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/i915/int
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 42 --
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 38d6
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 50 --
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 74f000e..77b6f17 100644
--- a/drivers/gpu/d
On 13/04/2019 13:58, Chris Wilson wrote:
Read the engine workarounds back using the GPU after loading the initial
context state to verify that we are setting them correctly, and bail if
it fails.
Aren't the context wa/ ones we expect to see saved in the context? As
such, what difference do yo
On 13/04/2019 13:58, Chris Wilson wrote:
If the driver is wedged, we can not issue the requests to exercise the
timelines or the system across suspend, so skip the tests. live_hangcheck
is there to fail if we cannot recover.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915
Quoting Tvrtko Ursulin (2019-04-15 11:41:43)
>
> On 13/04/2019 13:58, Chris Wilson wrote:
> > Read the engine workarounds back using the GPU after loading the initial
> > context state to verify that we are setting them correctly, and bail if
> > it fails.
>
> Aren't the context wa/ ones we expec
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev4)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
37affd023b33 drm/i915: Introduce vfunc intel_get_color_config to create hw lut
2c1fbf49d4d
Quoting Chris Wilson (2019-04-15 11:45:47)
> Quoting Tvrtko Ursulin (2019-04-15 11:41:43)
> >
> > On 13/04/2019 13:58, Chris Wilson wrote:
> > > Read the engine workarounds back using the GPU after loading the initial
> > > context state to verify that we are setting them correctly, and bail if
>
fre 2019-04-12 klockan 15:51 +0530 skrev Uma Shankar:
> Introduced a client cap for advance cap mode
> capability. Userspace should set this to get
> to be able to use the new gamma_mode property.
>
> If this is not set, driver will work in legacy
> mode.
>
> Suggested-by: Ville Syrjälä
> Signed
On 12/04/2019 15:58, Chris Wilson wrote:
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
multiple instances of the same engine within the GEM context, defeating
our use of the engine as a key to looking up the HW
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev4)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Introduce vfunc intel_get_color_config to create hw l
I managed two parallel replies to the same message... one comment below:
On 15/04/2019 12:00, Tvrtko Ursulin wrote:
On 12/04/2019 15:58, Chris Wilson wrote:
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
mult
From: Alastair D'Silva
> Sent: 15 April 2019 11:29
...
> I do, and I believe the choice of the output length should be in the hands
> of the caller.
>
> On further thought, it would make more sense to remove the hardcoded list of
> sizes and just enforce a power of 2. The function shouldn't dictat
From: Alastair D'Silva
> Sent: 15 April 2019 11:45
...
> > Although I think you'd want a 'no hex' flag to suppress the hex.
> >
> > Probably more useful flags are ones to suppress the address column.
>
> This is already supported by the prefix_type parameter - are you proposing
> that we eliminat
On 12/04/2019 09:53, Chris Wilson wrote:
We no longer need to track the active intel_contexts within each engine,
allowing us to drop a tricky mutex_lock from inside unpin (which may
occur inside fs_reclaim).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_context.c |
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev4)
URL : https://patchwork.freedesktop.org/series/58039/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5933 -> Patchwork_12795
Summary
---
From: Tvrtko Ursulin
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.
Whitelist the register to allow media re-configuring it to their liking.
Signed-off-by: Tvrtko Ursulin
Cc: kevin...@intel.com
Cc: xiaogan
Quoting Tvrtko Ursulin (2019-04-15 12:43:07)
> From: Tvrtko Ursulin
>
> WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
> to benefit 3d workloads but media has different requirements.
>
> Whitelist the register to allow media re-configuring it to their liking.
>
> Sign
On Fri, Apr 12, 2019 at 09:53:21AM +0100, Chris Wilson wrote:
> SSEU reprogramming of the context introduced the notion of engine class
> and instance for a forwards compatible method of describing any engine
> beyond the old execbuf interface. We wish to adopt this class:instance
> description for
== Series Details ==
Series: drm: Add detection of changing of edid on between suspend and resume
(rev4)
URL : https://patchwork.freedesktop.org/series/59352/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12796
===
On Fri, Apr 12, 2019 at 02:22:32PM -0700, Manasi Navare wrote:
> This is one of the patches to start replacing drm pointers
> and use the intel_atomic_state and intel_crtc to derive
> the necessary intel state variables required for the intel
> modeset functions.
>
> v2:
> * Flip the function argu
On 12/04/2019 09:53, Chris Wilson wrote:
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance)
On Sat, Apr 13, 2019 at 02:27:57PM +0100, Chris Wilson wrote:
> We have to control the cache domains, especially important before first
> writing into the object.
>
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_mmap_gtt.c | 26 --
> 1 file changed, 16 insertions(+)
On 15/04/2019 12:45, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-15 12:43:07)
From: Tvrtko Ursulin
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.
Whitelist the register to allow media re-configur
Quoting Tvrtko Ursulin (2019-04-15 13:19:45)
> > + set.engines->i915 = ctx->i915;
> > + for (n = 0; n < num_engines; n++) {
> > + struct i915_engine_class_instance ci;
> > + struct intel_engine_cs *engine;
> > +
> > + if (copy_from_user(&ci, &user->engine
== Series Details ==
Series: drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
URL : https://patchwork.freedesktop.org/series/59494/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12797
Summary
---
On 2019-04-05 at 14:32:00 +0200, Greg Kroah-Hartman wrote:
> On Fri, Apr 05, 2019 at 04:06:22PM +0530, Ramalingam C wrote:
> > On 2019-04-05 at 11:23:00 +0200, Greg Kroah-Hartman wrote:
> > > On Fri, Apr 05, 2019 at 02:12:54PM +0530, Ramalingam C wrote:
> > > > Functions to create and remove the bi
Quoting Tvrtko Ursulin (2019-04-15 12:10:17)
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 58956b49f392..6c6bd50d87c9 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -34,6 +34,7 @@
On Mon, Apr 15, 2019 at 10:57:52AM +, Lankhorst, Maarten wrote:
> fre 2019-04-12 klockan 15:51 +0530 skrev Uma Shankar:
> > Introduced a client cap for advance cap mode
> > capability. Userspace should set this to get
> > to be able to use the new gamma_mode property.
> >
> > If this is not se
commit 21635d7311734d2d1b177f8a95e2f9386174b76d upstream.
Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast
and narrow") started to optize the eDP 1.4+ link config, both per spec
and as preparation for display stream compression support.
Sadly, we again face panels that flat o
On 12/04/2019 09:53, Chris Wilson wrote:
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy
On 15/04/2019 13:42, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-15 12:10:17)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 58956b49f392..6c6bd50d87c9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs
Quoting Ville Syrjälä (2019-04-15 13:23:54)
> On Sat, Apr 13, 2019 at 02:27:57PM +0100, Chris Wilson wrote:
> > We have to control the cache domains, especially important before first
> > writing into the object.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > tests/i915/gem_mmap_gtt.c | 26
On Mon, Apr 15, 2019 at 02:18:28PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2019-04-15 13:23:54)
> > On Sat, Apr 13, 2019 at 02:27:57PM +0100, Chris Wilson wrote:
> > > We have to control the cache domains, especially important before first
> > > writing into the object.
> > >
> > > Sig
== Series Details ==
Series: drm: Add detection of changing of edid on between suspend and resume
(rev4)
URL : https://patchwork.freedesktop.org/series/59352/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934_full -> Patchwork_12796_full
=
== Series Details ==
Series: drm/i915/dp: revert back to max link rate and lane count on eDP (rev3)
URL : https://patchwork.freedesktop.org/series/59039/
State : failure
== Summary ==
Applying: drm/i915/dp: revert back to max link rate and lane count on eDP
Using index info to reconstruct a ba
> -Original Message-
> From: Lankhorst, Maarten
> Sent: Monday, April 15, 2019 4:28 PM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
> dri-
> de...@lists.freedesktop.org
> Cc: Syrjala, Ville ; emil.l.veli...@gmail.com;
> s...@ravnborg.org; Roper, Matthew D ;
> seanp...@chromium.o
mån 2019-04-15 klockan 19:26 +0530 skrev Sharma, Shashank:
> > -Original Message-
> > From: Lankhorst, Maarten
> > Sent: Monday, April 15, 2019 4:28 PM
> > To: Shankar, Uma ; intel-gfx@lists.freedeskt
> > op.org; dri-
> > de...@lists.freedesktop.org
> > Cc: Syrjala, Ville ; emil.l.velikov@g
From: Ville Syrjälä
Since SKL the eLLC has been sitting on the far side of the system
agent, meaning the display engine can utilize it. Let's enable that.
I chose WB for the caching mode, because my numbers are indicating
that WT might actually be WB and WC might actually be UC. I'm not
100% sur
Set chicken bits to workaround a possible pixel shader
dispatch hang.
Bspec: 14091, ID#0651
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_workarounds.c | 9 +
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/
Quoting Mika Kuoppala (2019-04-15 15:21:22)
> Set chicken bits to workaround a possible pixel shader
> dispatch hang.
>
> Bspec: 14091, ID#0651
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4
> drivers/gpu/drm/i915/intel_workarounds.c | 9 +
> 2
== Series Details ==
Series: drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
URL : https://patchwork.freedesktop.org/series/59494/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934_full -> Patchwork_12797_full
Summa
On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote:
> Set chicken bits to workaround a possible pixel shader
> dispatch hang.
>
> Bspec: 14091, ID#0651
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4
> drivers/gpu/drm/i915/intel_workarounds.c
On 4/15/2019 7:42 PM, Lankhorst, Maarten wrote:
mån 2019-04-15 klockan 19:26 +0530 skrev Sharma, Shashank:
-Original Message-
From: Lankhorst, Maarten
Sent: Monday, April 15, 2019 4:28 PM
To: Shankar, Uma ; intel-gfx@lists.freedeskt
op.org; dri-
de...@lists.freedesktop.org
Cc: Syrjala,
Quoting Ville Syrjälä (2019-04-15 15:25:11)
> On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > b/drivers/gpu/drm/i915/intel_workarounds.c
> > index ccaf63679435..4f1a7500ca07 100644
> > --- a/drivers/gpu/drm/i915/intel_wor
Chris Wilson writes:
> Quoting Ville Syrjälä (2019-04-15 15:25:11)
>> On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote:
>> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
>> > b/drivers/gpu/drm/i915/intel_workarounds.c
>> > index ccaf63679435..4f1a7500ca07 100644
>> > --- a/
Set chicken bits to workaround a possible pixel shader
dispatch hang.
v2: no need to filter out preprod skl (Ville, Chris)
Bspec: 14091, ID#0651
Cc: Chris Wilson
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_wo
On Mon, Apr 15, 2019 at 03:58:37PM +0300, Jani Nikula wrote:
> commit 21635d7311734d2d1b177f8a95e2f9386174b76d upstream.
>
> Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast
> and narrow") started to optize the eDP 1.4+ link config, both per spec
> and as preparation for displ
Set chicken bits to workaround a possible pixel shader
dispatch hang.
v2: no need to filter out preprod skl (Ville, Chris)
v3: formatting
Bspec: 14091, ID#0651
Cc: Chris Wilson
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/dr
On Mon, Apr 15, 2019 at 06:11:13PM +0530, Ramalingam C wrote:
> On 2019-04-05 at 14:32:00 +0200, Greg Kroah-Hartman wrote:
> > On Fri, Apr 05, 2019 at 04:06:22PM +0530, Ramalingam C wrote:
> > > On 2019-04-05 at 11:23:00 +0200, Greg Kroah-Hartman wrote:
> > > > On Fri, Apr 05, 2019 at 02:12:54PM +0
This is a note to let you know that I've just added the patch titled
drm/i915/dp: revert back to max link rate and lane count on eDP
to the 5.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch i
== Series Details ==
Series: drm/i915: Enable eLLC caching of display buffers for SKL+
URL : https://patchwork.freedesktop.org/series/59502/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f13e05007cae drm/i915: Enable eLLC caching of display buffers for SKL+
-:63: WARNING:LONG_L
== Series Details ==
Series: drm/i915: Enable eLLC caching of display buffers for SKL+
URL : https://patchwork.freedesktop.org/series/59502/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Enable eLLC caching of display buffers for SKL+
-drive
== Series Details ==
Series: drm/i915: Enable eLLC caching of display buffers for SKL+
URL : https://patchwork.freedesktop.org/series/59502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12799
Summary
== Series Details ==
Series: Patch "drm/i915/dp: revert back to max link rate and lane count on eDP"
has been added to the 5.0-stable tree
URL : https://patchwork.freedesktop.org/series/59507/
State : failure
== Summary ==
Applying: Patch "drm/i915/dp: revert back to max link rate and lane co
== Series Details ==
Series: drm/i915: Enable workaround for pixel shader dispatch hang (rev3)
URL : https://patchwork.freedesktop.org/series/59504/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12800
Summ
From: Ville Syrjälä
Reduce the clutter a bit by introducing gen8_de_pipe_fault_mask().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i91
From: Ville Syrjälä
The proper way to process interrupts is to first acknowledge them
all, and later process them. Start down that path for pch interrupts
by collecting the relevant register values into a struct so that
we can carry them from the ack part to the handler part.
Signed-off-by: Vill
From: Ville Syrjälä
I never finished the irq ack+handler split for ilk+. Let's try to do
that now since people seem keen on cleaning up stuff in there. One
thing I didn't dare touch is gen11_gt_irq_handler() as that thing
looks a bit nuts.
A bit of a downside:
Total: Before=39303, After=40393, c
From: Ville Syrjälä
All the older platforms already follow the ack+handler apporoach
for interrupts. Convert ilk+ as well. As the number of registers
involved is rather large we'll introduce a few more structs to
carry the register values around.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/dr
From: Ville Syrjälä
Collect the hpd related register values into a struct for
so that it's more convenient to pass them around.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 241 ++--
1 file changed, 137 insertions(+), 104 deletions(-)
diff --g
Quoting Ville Syrjala (2019-04-15 16:49:00)
> From: Ville Syrjälä
>
> I never finished the irq ack+handler split for ilk+. Let's try to do
> that now since people seem keen on cleaning up stuff in there. One
> thing I didn't dare touch is gen11_gt_irq_handler() as that thing
> looks a bit nuts.
>
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that those registers we do add
are (a) then writa
Immediately after writing the workaround, verify that it stuck in the
register.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 32 +---
1 file changed, 18 insertion
Read the engine workarounds back using the GPU after loading the initial
context state to verify that we are setting them correctly, and bail if
it fails.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 6 +
drivers/gpu/drm/i915/intel_workaro
Sometimes the HW doesn't even play fair, and completely forgets about
register writes. Skip verifying known troublemakers.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 40 ++
Quoting Patchwork (2019-04-15 16:21:30)
> == Series Details ==
>
> Series: drm/i915: Enable eLLC caching of display buffers for SKL+
> URL : https://patchwork.freedesktop.org/series/59502/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12799
> ==
On Wed, Apr 10, 2019 at 09:49:33PM -0400, Rob Clark wrote:
> On Tue, Apr 9, 2019 at 8:27 AM Eric Engestrom
> wrote:
> >
> > On Tuesday, 2019-04-09 12:59:13 +0100, Eric Engestrom wrote:
> > > On Tuesday, 2019-04-09 11:35:14 +, Ayan Halder wrote:
> > > > Generated using make headers_install fro
> -Original Message-
> From: David Laight
> Sent: Monday, 15 April 2019 9:04 PM
> To: 'Alastair D'Silva' ; 'Petr Mladek'
>
> Cc: 'Alastair D'Silva' ; 'Jani Nikula'
> ; 'Joonas Lahtinen'
> ; 'Rodrigo Vivi' ;
> 'David Airlie' ; 'Daniel Vetter' ; 'Karsten
> Keil' ; 'Jassi Brar' ; 'Tom
> Lend
Package: linux-image-4.19.0-0.bpo.4-amd64
Version: 4.19.28-2~bpo9+1
X-Debbugs-CC: ibm-a...@hmh.eng.br, ibm-acpi-de...@lists.sourceforge.net,
platform-driver-...@vger.kernel.org, intel-gfx@lists.freedesktop.org
Dear Maintainer,
I have a Lenovo ThinkPad T480s with Intel GFX and a Lenovo ThinkPad U
> > > On Wed 2019-04-10 13:17:18, Alastair D'Silva wrote:
> > > > From: Alastair D'Silva
> > > >
> > > > Some buffers may only be partially filled with useful data, while
> > > > the rest is padded (typically with 0x00 or 0xff).
> > > >
> > > > This patch introduces flags which allow lines of padd
Hi,
On Mon, Apr 15, 2019 at 11:13 AM Alexei Starovoitov
wrote:
>
> On Sun, Apr 14, 2019 at 2:15 AM Shyam Saini
> wrote:
> >
> > Currently, there are 3 different macros, namely sizeof_field, SIZEOF_FIELD
> > and FIELD_SIZEOF which are used to calculate the size of a member of
> > structure, so to
> -Original Message-
> From: Petr Mladek
> Sent: Saturday, 13 April 2019 12:04 AM
> To: Alastair D'Silva
> Cc: alast...@d-silva.org; Jani Nikula ;
Joonas
> Lahtinen ; Rodrigo Vivi
> ; David Airlie ; Daniel Vetter
> ; Karsten Keil ; Jassi Brar
> ; Tom Lendacky ;
> David S. Miller ; Jose Ab
On Sun, Apr 14, 2019 at 2:15 AM Shyam Saini
wrote:
>
> Currently, there are 3 different macros, namely sizeof_field, SIZEOF_FIELD
> and FIELD_SIZEOF which are used to calculate the size of a member of
> structure, so to bring uniformity in entire kernel source tree lets use
> FIELD_SIZEOF and repl
> -Original Message-
> From: Petr Mladek
> Sent: Friday, 12 April 2019 11:48 PM
> To: Alastair D'Silva
> Cc: alast...@d-silva.org; Jani Nikula ;
Joonas
> Lahtinen ; Rodrigo Vivi
> ; David Airlie ; Daniel Vetter
> ; Karsten Keil ; Jassi Brar
> ; Tom Lendacky ;
> David S. Miller ; Jose Abre
> -Original Message-
> From: Petr Mladek
> Sent: Saturday, 13 April 2019 12:12 AM
> To: Alastair D'Silva
> Cc: alast...@d-silva.org; Jani Nikula ;
Joonas
> Lahtinen ; Rodrigo Vivi
> ; David Airlie ; Daniel Vetter
> ; Karsten Keil ; Jassi Brar
> ; Tom Lendacky ;
> David S. Miller ; Jose Ab
> On Apr 14, 2019, at 3:14 AM, Shyam Saini
> wrote:
>
> Currently, there are 3 different macros, namely sizeof_field, SIZEOF_FIELD
> and FIELD_SIZEOF which are used to calculate the size of a member of
> structure, so to bring uniformity in entire kernel source tree lets use
> FIELD_SIZEOF and
> -Original Message-
> From: David Laight
> Sent: Monday, 15 April 2019 8:21 PM
> To: 'Alastair D'Silva' ; 'Petr Mladek'
>
> Cc: 'Alastair D'Silva' ; 'Jani Nikula'
> ; 'Joonas Lahtinen'
> ; 'Rodrigo Vivi' ;
> 'David Airlie' ; 'Daniel Vetter' ; 'Karsten
> Keil' ; 'Jassi Brar' ; 'Tom
> Lend
Currently, there are 3 different macros, namely sizeof_field, SIZEOF_FIELD
and FIELD_SIZEOF which are used to calculate the size of a member of
structure, so to bring uniformity in entire kernel source tree lets use
FIELD_SIZEOF and replace all occurrences of other two macros with this.
For this p
> > > On Wed 2019-04-10 13:17:17, Alastair D'Silva wrote:
> > > > From: Alastair D'Silva
> > > >
> > > > With modern high resolution screens, we can display more data,
> > > > which makes life a bit easier when debugging.
> > >
> > > I have quite some doubts about this feature.
> > >
> > > We are
> From: Alastair D'Silva
> > Sent: 15 April 2019 11:29
> ...
> > I do, and I believe the choice of the output length should be in the
> > hands of the caller.
> >
> > On further thought, it would make more sense to remove the hardcoded
> > list of sizes and just enforce a power of 2. The function s
In favour of FIELD_SIZEOF, lets deprecate other two similar macros
sizeof_field and SIZEOF_FIELD, and remove them completely.
Signed-off-by: Shyam Saini
---
arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 7 ---
include/linux/stddef.h | 8
tools/testing/
> -Original Message-
> From: Petr Mladek
> Sent: Monday, 15 April 2019 7:24 PM
> To: Alastair D'Silva
> Cc: 'Alastair D'Silva' ; 'Jani Nikula'
> ; 'Joonas Lahtinen'
> ; 'Rodrigo Vivi'
;
> 'David Airlie' ; 'Daniel Vetter' ;
'Karsten
> Keil' ; 'Jassi Brar' ; 'Tom
> Lendacky' ; 'David S. Mil
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