Quoting Tvrtko Ursulin (2019-04-15 12:43:07) > From: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > > WaEnableStateCacheRedirectToCS context workaround configures the L3 cache > to benefit 3d workloads but media has different requirements. > > Whitelist the register to allow media re-configuring it to their liking. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > Cc: kevin...@intel.com > Cc: xiaogang...@intel.com > --- > drivers/gpu/drm/i915/intel_workarounds.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c > b/drivers/gpu/drm/i915/intel_workarounds.c > index ccaf63679435..6458d161204f 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -1050,6 +1050,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > /* WaAllowUMDToModifySamplerMode:icl */ > whitelist_reg(w, GEN10_SAMPLER_MODE); > + > + /* WaEnableStateCacheRedirectToCS:icl */ > + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
Have we checked this is context saved? -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
