On Sat, Mar 30, 2019 at 10:07:58PM +0100, Noralf Trønnes wrote:
>
>
> Den 28.03.2019 09.17, skrev Daniel Vetter:
> > On Tue, Mar 26, 2019 at 06:55:43PM +0100, Noralf Trønnes wrote:
> >> drm_fb_helper_is_bound() is used to check if DRM userspace is in control.
> >> This is done by looking at the f
On Sat, Mar 30, 2019 at 11:54:48PM +, Chris Wilson wrote:
> Replace the convoluted raising of SIGALRM from the child with an
> interruptible sleep in the parent with the equivalent and far more
> natural igt_waitchildren_timeout().
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103
Quoting Daniel Vetter (2019-04-01 08:32:27)
> On Sat, Mar 30, 2019 at 11:54:48PM +, Chris Wilson wrote:
> > Replace the convoluted raising of SIGALRM from the child with an
> > interruptible sleep in the parent with the equivalent and far more
> > natural igt_waitchildren_timeout().
> >
> > Bu
On 29/03/2019 09:54, Chris Wilson wrote:
We may use HW semaphores to schedule nearly-ready work such that they
are already spinning on the GPU waiting for the completion on another
engine. However, we don't want for that spinning task to actually block
any real work should it be scheduled.
v2:
On 30/03/2019 10:29, Chris Wilson wrote:
Exercise basic creation and swapping between new address spaces.
v2: Check isolation that the same vm_id on different fd are indeed
different VM.
v3: Cross-over check with CREATE_EXT_SETPARAM
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
lib/M
On 31/03/2019 22:09, Chris Wilson wrote:
Before trying to measure the busyness reporting for the idle state, make
sure the gpu is actually idle and not still running any backgound system
task.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 1 +
1 file changed, 1 inse
This is to test if sagv affects rotation test failures.
---
drivers/gpu/drm/i915/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f..c073b91 100644
--- a/drivers/gpu/drm
This patch is to test if sagv affect rotation tests. Trybot didn't
seem to honor test with tag.
Test-with: 1554056300-23473-1-git-send-email-juhapekka.heikk...@gmail.com
Juha-Pekka Heikkila (1):
drm/i915: Test. Disable sagv for testing on icl
drivers/gpu/drm/i915/intel_display.c | 5 +++--
1
== Series Details ==
Series: drm/i915: ignore. Disable sagv for testing
URL : https://patchwork.freedesktop.org/series/58809/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4e4f84d75b80 drm/i915: ignore. Disable sagv for testing
-:9: WARNING:COMMIT_MESSAGE: Missing commit descri
Quoting Tvrtko Ursulin (2019-04-01 09:15:18)
>
> On 31/03/2019 22:09, Chris Wilson wrote:
> > Before trying to measure the busyness reporting for the idle state, make
> > sure the gpu is actually idle and not still running any backgound system
> > task.
> >
> > Signed-off-by: Chris Wilson
> > Cc
Quoting Tvrtko Ursulin (2019-04-01 09:12:08)
>
>
> On 30/03/2019 10:29, Chris Wilson wrote:
> > + /* Verify the trick with the assumed target works */
> > + write_to_address(i915, ctx[0], obj[0].offset, i915);
> > + gem_read(i915, obj[0].handle, 0, &result, sizeof(result));
> > +
On 01/04/2019 09:52, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-01 09:12:08)
On 30/03/2019 10:29, Chris Wilson wrote:
+ /* Verify the trick with the assumed target works */
+ write_to_address(i915, ctx[0], obj[0].offset, i915);
+ gem_read(i915, obj[0].handle, 0, &result,
Quoting Tvrtko Ursulin (2019-04-01 09:59:53)
>
> On 01/04/2019 09:52, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-04-01 09:12:08)
> >>
> >>
> >> On 30/03/2019 10:29, Chris Wilson wrote:
> >>> + /* Verify the trick with the assumed target works */
> >>> + write_to_address(i915, ctx
== Series Details ==
Series: drm/i915: ignore. Disable sagv for testing
URL : https://patchwork.freedesktop.org/series/58809/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5847 -> Patchwork_12645
Summary
---
**FAILUR
On Sun, 31 Mar 2019, Aditya Swarup wrote:
> From: Clinton Taylor
>
> Changing settings from 8 bit to 10/12 bit deep color(& vice versa)
> doesn't work correctly using xrandr max bpc property. Fix the
> driver for applying correct settings.
Please describe *why* there is a problem, and *why* the
On Sun, 31 Mar 2019, Aditya Swarup wrote:
> Adding N & CTS values for 10/12 bit deep color from Appendix C
> table in HDMI 2.0 spec. The correct values for N is not chosen
> automatically by hardware for deep color modes.
>
> Signed-off-by: Aditya Swarup
> Cc: Clint Taylor
> Cc: Ville Syrjälä
>
== Series Details ==
Series: drm/i915: ignore. Disable sagv for testing (rev2)
URL : https://patchwork.freedesktop.org/series/58809/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
72ab28224547 drm/i915: ignore. Disable sagv for testing
-:9: WARNING:COMMIT_MESSAGE: Missing commit
== Series Details ==
Series: drm/i915: ignore. Disable sagv for testing (rev2)
URL : https://patchwork.freedesktop.org/series/58809/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5850 -> Patchwork_12646
Summary
---
*
If we caused a fault on a GEM buffer while in the middle of trying to
write/read into that buffer, we could conceivably deadlock (e.g.
recursing on struct_mutex if we are not careful). Exercise these cases
by supplying a fresh mmap to pread/pwrite in both non-overlapping and
overlapping copies.
Si
If we caused a fault on a GEM buffer while in the middle of trying to
write/read into that buffer, we could conceivably deadlock (e.g.
recursing on struct_mutex if we are not careful). Exercise these cases
by supplying a fresh mmap to pread/pwrite in both non-overlapping and
overlapping copies.
Si
Den 01.04.2019 09.12, skrev Daniel Vetter:
> On Sat, Mar 30, 2019 at 10:07:58PM +0100, Noralf Trønnes wrote:
>>
>>
>> Den 28.03.2019 09.17, skrev Daniel Vetter:
>>> On Tue, Mar 26, 2019 at 06:55:43PM +0100, Noralf Trønnes wrote:
drm_fb_helper_is_bound() is used to check if DRM userspace is i
If the user passes in a pointer to a GGTT mmaping of the same buffer
being written to, we can hit a deadlock in acquiring the shmemfs page
(once as the write destination and then as the read source).
[<0>] io_schedule+0xd/0x30
[<0>] __lock_page+0x105/0x1b0
[<0>] find_lock_entry+0x55/0x90
[<0>] shm
Ideally we only need one semaphore per ring to accommodate waiting on
multiple engines in parallel. However, since we do not know which fences
we will finally be waiting on, we emit a semaphore for every fence. It
turns out to be quite easy to trick ourselves into exhausting our
ringbuffer causing
The MIPS architecture doesn't provide the hardware atomics that are
required for the "create-clear" sub-test such as
__sync_add_and_fetch(). As a simple and pragmatic solution, disable
this sub-test when building for MIPS. A better approach would be to
add a fallback implementation for these oper
On 25/03/2019 09:03, Chris Wilson wrote:
Split out the powermanagement portion (GT wakeref, suspend/resume) of
GEM from i915_gem.c into its own file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/i915_gem.c | 335 +-
Quoting Chris Wilson (2019-04-01 15:18:38)
> Ideally we only need one semaphore per ring to accommodate waiting on
> multiple engines in parallel. However, since we do not know which fences
> we will finally be waiting on, we emit a semaphore for every fence. It
> turns out to be quite easy to tric
On 25/03/2019 09:03, Chris Wilson wrote:
If we introduce a new mutex for the exclusive use of GEM's runtime power
management, we can remove its requirement of holding the struct_mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 +--
drivers/gpu/drm/i9
On 25/03/2019 09:03, Chris Wilson wrote:
Transition from calling the lower level intel_runtime_pm functions to
using the GEM runtime_pm functions (i915_gem_unpark, i915_gem_park) now
that they are decoupled from struct_mutex. This has the small advantage
of reducing our overhead for request emis
Quoting Tvrtko Ursulin (2019-04-01 16:22:55)
>
> On 25/03/2019 09:03, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 11803d485275..7c7afe99986c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i91
On Mon, Mar 25, 2019 at 2:06 AM Chris Wilson wrote:
>
> Split out the powermanagement portion (GT wakeref, suspend/resume) of
> GEM from i915_gem.c into its own file.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/Makefile | 2 +
> drivers/gpu/drm/i915/i915_gem.c
Quoting Tvrtko Ursulin (2019-04-01 16:34:11)
>
> On 25/03/2019 09:03, Chris Wilson wrote:
> > Transition from calling the lower level intel_runtime_pm functions to
> > using the GEM runtime_pm functions (i915_gem_unpark, i915_gem_park) now
> > that they are decoupled from struct_mutex. This has th
Quoting Lucas De Marchi (2019-04-01 16:39:29)
> On Mon, Mar 25, 2019 at 2:06 AM Chris Wilson wrote:
> I really like the use of small headers like this. We could do more on
> other areas, too. One thing to consider is if we should settle on
> intel_ or i915_ prefix. On display area we tend to use i
On 01/04/2019 16:37, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-01 16:22:55)
On 25/03/2019 09:03, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11803d485275..7c7afe99986c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/dri
We want to use intel_engine_mask_t inside i915_request.h, which means
extracting it from the general header file mess and placing it inside a
types.h. A knock on effect is that the compiler wants to warn about
type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare
for the worst.
v2:
Ideally we only need one semaphore per ring to accommodate waiting on
multiple engines in parallel. However, since we do not know which fences
we will finally be waiting on, we emit a semaphore for every fence. It
turns out to be quite easy to trick ourselves into exhausting our
ringbuffer causing
On 27/03/2019 18:38, Patchwork wrote:
== Series Details ==
Series: Device id consolidation (rev2)
URL : https://patchwork.freedesktop.org/series/58561/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5827 -> Patchwork_12616
Ideally we only need one semaphore per ring to accommodate waiting on
multiple engines in parallel. However, since we do not know which fences
we will finally be waiting on, we emit a semaphore for every fence. It
turns out to be quite easy to trick ourselves into exhausting our
ringbuffer causing
We want to use intel_engine_mask_t inside i915_request.h, which means
extracting it from the general header file mess and placing it inside a
types.h. A knock on effect is that the compiler wants to warn about
type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare
for the worst.
v2:
For more intel_engine_mask_t detangling. This time so that we can use
intel_engine_mask_t inside the scheduling structs.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_priolist_types.h| 43 +++
drivers/gpu/drm/i
From: Kiran Kumar S
As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.
In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to properly
recognize the final seg
Quoting Tvrtko Ursulin (2019-04-01 16:54:53)
>
> On 01/04/2019 16:37, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-04-01 16:22:55)
> >>
> >> On 25/03/2019 09:03, Chris Wilson wrote:
> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >>> b/drivers/gpu/drm/i915/i915_drv.h
> >>> index 1180
On Thu, Mar 28, 2019 at 04:12:10PM +0200, Laurent Pinchart wrote:
> Hi Jagadeesh,
>
> On Thu, Mar 28, 2019 at 09:32:06PM +0530, Jagadeesh Pagadala wrote:
> > On Thu, Mar 28, 2019 at 08:51:24AM +0200, Laurent Pinchart wrote:
> > > On Thu, Mar 28, 2019 at 02:41:56AM +0530, jagdsh.li...@gmail.com wro
From: Jagadeesh Pagadala
Remove duplicate headers which are included twice.
Signed-off-by: Jagadeesh Pagadala
---
drivers/gpu/drm/bridge/panel.c | 1 -
drivers/gpu/drm/i915/intel_display.c | 7 ---
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers
On 3/28/2019 2:41 AM, jagdsh.li...@gmail.com wrote:
From: Jagadeesh Pagadala
Remove duplicate headers which are included twice.
Signed-off-by: Jagadeesh Pagadala
Reviewed-by: Mukesh Ojha
-Mukesh
---
drivers/gpu/drm/bridge/panel.c | 1 -
drivers/gpu/drm/i915/intel_display.c |
On 3/29/2019 12:32 AM, Jagadeesh Pagadala wrote:
On Thu, Mar 28, 2019 at 04:12:10PM +0200, Laurent Pinchart wrote:
Hi Jagadeesh,
On Thu, Mar 28, 2019 at 09:32:06PM +0530, Jagadeesh Pagadala wrote:
On Thu, Mar 28, 2019 at 08:51:24AM +0200, Laurent Pinchart wrote:
On Thu, Mar 28, 2019 at 02:41
From: Ville Syrjälä
Add a gamma mode capability property to enable various kind of
gamma modes supported by platforms like: Interpolated, Split,
Multi Segmented etc. Userspace can get this property and
should be able to get the platform capabilties wrt various
gamma modes possible and the possibl
This series adds support for programmable gamma modes and
exposes a property interface for the same. Also added,
support for multi segment gamma mode introduced in ICL+
It creates 2 property interfaces :
1. GAMMA_MODE_CAPS: This is immutable property and exposes
the various gamma modes supported a
From: Ville Syrjälä
This defines the color lut ranges for 10bit and multi
segmented gamma range for ICL.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 301 -
1 file changed, 297 insertions(+), 4 deletions(-
Add Gamma Mode property to set the gamma mode
(Interploated, Split, Multi Segmented etc) from the
list obtained through the gamma mode caps property.
Create the blob and send to driver for programming
the luts to the appropriate registers and setting
the chosen gamma mode.
Signed-off-by: Uma Shan
Add macros to define multi segmented gamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 341f03e..f95f82f 100644
--- a/drivers
Gen11 introduced a new gamma mode i.e, multi segmented
gamma mode. Added support for the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 161 -
include/drm/drm_crtc.h | 3 +
2 files changed, 161 insertions(+), 3 deletion
Attach the gamma mode property to allow userspace
set the gamma mode and provide the luts for the
same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/
Create the gamma mode caps property and attach
to crtc.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 2 ++
drivers/gpu/drm/i915/intel_display.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.
On Sun, Mar 24, 2019 at 03:40:58PM +0100, Borislav Petkov wrote:
> On Fri, Mar 15, 2019 at 12:19:38PM -0700, Rodrigo Vivi wrote:
> > Let's reserve EHL stolen memory for graphics.
> >
> > ElkhartLake is a gen11 platform which is compatible with
> > ICL changes.
> >
> > Cc: Thomas Gleixner
> > Cc:
Hi Uma.
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 58ad983..cdfda90 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -249,6 +249,13 @@ struct drm_crtc_state {
> struct drm_property_blob *mode_blob;
>
> /**
> + * @gamma_mode:
>
Hi Uma.
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -256,6 +256,13 @@ struct drm_crtc_state {
> struct drm_property_blob *gamma_mode_caps;
>
> /**
> + * @gamma_mode:
> + *
> + * FIXME
> + */
> + struct drm_property_blob *gamma_mode;
HEr
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: 093a2914c367de18bbf8d07d0b15ce63c43e5f9e
commit: 4e0795386a907989f92082c9f1af3c70dec46969 [4/8] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: sparc64-allyesconfig (attached as .config)
compiler: sparc64-
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: 093a2914c367de18bbf8d07d0b15ce63c43e5f9e
commit: 4e0795386a907989f92082c9f1af3c70dec46969 [4/8] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: xtensa-allyesconfig (attached as .config)
compiler: xtensa-li
From: Ville Syrjälä
Extract a helper to calculate the ILK+ 10bit gamma LUT entry.
It's already duplicated twice, and soon we'll have more.
v2: s/it/bit/ (Matt)
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 27 +++
From: Ville Syrjälä
Using the split gamma mode when we don't have to has the annoying
requirement of loading a linear LUT to the unused half. Instead
let's make life simpler by switching to the 10bit gamma mode
and duplicating each entry.
This also allows us to load the software gamma LUT into t
From: Ville Syrjälä
Reuse the bdw+ code to get split/10bit gamma for
ivb/hsw. The hardware is nearly identical. The
only slight snag is that on ivb/hsw the precision
palette auto increment mode does not work. So we
must increment the index manually. We'll probably
want to stick to the auto increm
From: Ville Syrjälä
Plop in support for 10bit LUT on ilk/snb.
There is no split gamma mode on these platforms, so we have
to choose between degamma and gamma. That could be a runtime choice
but for now let's just advertize the gamma as having 1024 entries.
We'll also keep the ctm hidden for now.
From: Ville Syrjälä
On ivb+ we can select between the regular 10bit LUT mode with
1024 entries, and the split mode where the LUT is split into
seprate degamma and gamma halves (each with 512 entries). Currently
we expose the split gamma size of 512 as the GAMMA/DEGAMMA_LUT_SIZE.
When using only
From: Ville Syrjälä
Rebased due to Uma's EXT_GC_MAX fix, and I added Matt's proposed
behavioural change (expose 1024 entry LUTs in split gamma mode
and just discard half the entries) as an extra patch on top.
Everything is reviewed except patches 2 and 7.
Ville Syrjälä (7):
drm/i915: Extract
From: Ville Syrjälä
i965+ have an interpolate 10bit LUT mode. Let's expose that so
that we can actually enjoy real 10bpc.
v2: Don't use I915_WRITE_FW() yet
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c| 6 +++
drivers/gpu/drm/i915/i915_r
From: Ville Syrjälä
Just so we don't leave gen2/3 out in the cold let's advertize the
legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props. Without the
GAMMA_LUT prop we can't actually load a LUT using the atomic ioctl
(in preparation for the day of 100% atomic driver).
Supposedly some gen2/3 platf
Now that all the uncore management is hidden under the uncore struct,
move the lock initialization under the uncore_init as well for better
encapsulation.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
drivers/gpu/drm/i915
Quoting Daniele Ceraolo Spurio (2019-04-01 21:14:11)
> Now that all the uncore management is hidden under the uncore struct,
> move the lock initialization under the uncore_init as well for better
> encapsulation.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Paulo Zanoni
> Cc: Chris Wilson
>
On 3/30/2019 00:59, Chris Wilson wrote:
Quoting john.c.harri...@intel.com (2019-03-30 00:10:45)
From: John Harrison
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that t
On 4/1/19 1:24 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-04-01 21:14:11)
Now that all the uncore management is hidden under the uncore struct,
move the lock initialization under the uncore_init as well for better
encapsulation.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Pau
Quoting John Harrison (2019-04-01 22:02:07)
> On 3/30/2019 00:59, Chris Wilson wrote:
> > Quoting john.c.harri...@intel.com (2019-03-30 00:10:45)
> >> From: John Harrison
> >>
> >> With virtual engines, it is no longer possible to know which specific
> >> physical engine a given request will be ex
Quoting Daniele Ceraolo Spurio (2019-04-01 22:06:00)
>
>
> On 4/1/19 1:24 PM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-04-01 21:14:11)
> >> Now that all the uncore management is hidden under the uncore struct,
> >> move the lock initialization under the uncore_init as well for
Encapsulate the uncore early init and be consistent with the
"_early" naming.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.c | 3 ++-
drivers/gpu/drm/i915/intel_uncore.c | 4
drivers/gpu/drm/i915/intel_uncore.h | 1 +
3 file
Add "_mmio" postfix to be consistent from the init/fini phase they're
called from.
Signed-off-by: Daniele Ceraolo Spurio
Suggested-by: Chris Wilson
Cc: Chris Wilson
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.c | 8
drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
drivers/g
Hi all,
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
In file included from include/linux/kernel.h:7,
from include/asm-generic/bug.h:18,
from arch/x86/include/asm/bug.h:83,
from include/linux/bu
On Sat, 2019-03-30 at 09:01 +, Chris Wilson wrote:
> Quoting Carlos Santa (2019-03-22 23:41:16)
> > From: Michel Thierry
> >
> > Emit the required commands into the ring buffer for starting and
> > stopping the watchdog timer before/after batch buffer start during
> > batch buffer submission.
Thanks, patch is:
Reviewed-by: Qiang Yu
Regards,
Qiang
On Tue, Apr 2, 2019 at 7:50 AM Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> In file included from include/linux/kernel.h:7,
>
Quoting Daniele Ceraolo Spurio (2019-04-01 22:59:24)
> Encapsulate the uncore early init and be consistent with the
> "_early" naming.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Paulo Zanoni
Reviewed-by: Chris Wilson
-Chris
__
Quoting Daniele Ceraolo Spurio (2019-04-01 22:59:25)
> Add "_mmio" postfix to be consistent from the init/fini phase they're
> called from.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Suggested-by: Chris Wilson
> Cc: Chris Wilson
> Cc: Paulo Zanoni
Reviewed-by: Chris Wilson
-Chris
___
79 matches
Mail list logo
