== Series Details ==
Series: series starting with [1/2] drm/i915/dp: deconflate PPS unlock from
divisor register (rev2)
URL : https://patchwork.freedesktop.org/series/57579/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12389
MI_STORE_DWORD_IMM wants to write into a dword-aligned (4B) address, we
mistakenly cleared bit2 and not bits 0 and 1.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/selftests/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field
with PSR2 TP2/3 wakeup time
URL : https://patchwork.freedesktop.org/series/57615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12384_full
=
On Wed, 06 Mar 2019 01:30:11 +0100, Sujaritha Sundaresan
wrote:
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
s/pci/CI ?
picking this up as a warning during fault injection testing.
v2: change the final return code in i915_pc
Quoting Michal Wajdeczko (2019-03-06 08:41:20)
> On Wed, 06 Mar 2019 01:30:11 +0100, Sujaritha Sundaresan
> wrote:
>
> > Replacing the -E2BIG error code return for WOPCM
> > initialization with -ENODEV. This will prevent the pci from
>
> s/pci/CI ?
>
> > picking this up as a warning during fa
Instead of passing the gem_context and engine to find the instance of
the intel_context to use, pass around the intel_context instead. This is
useful for the next few patches, where the intel_context is no longer a
direct lookup.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drive
On Tue, 05 Mar 2019, Aditya Swarup wrote:
> Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows
> to passthrough FB pixels unmodified across pipe. This fixes the failures
> for DP link layer compliance tests 4.4.1.1, 4.4.1.2 & 4.4.1.3.
> (Lineage #1605353570)
>
> Cc: Clint Taylor
On Wed, 06 Mar 2019 09:45:17 +0100, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-03-06 08:41:20)
On Wed, 06 Mar 2019 01:30:11 +0100, Sujaritha Sundaresan
wrote:
> Replacing the -E2BIG error code return for WOPCM
> initialization with -ENODEV. This will prevent the pci from
s/pci/CI
== Series Details ==
Series: series starting with [v2] drm/i915/guc: Fixing error code for WOPCM
initialization (rev2)
URL : https://patchwork.freedesktop.org/series/57551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12385_full
===
== Series Details ==
Series: drm/i915/icl: split pll functions
URL : https://patchwork.freedesktop.org/series/57618/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12386_full
Summary
---
**SUCCE
On 05/03/2019 21:06, Chris Wilson wrote:
Rather than manually add every new global into each hook, use
i915_global_register() function and keep a list of registered globals to
invoke instead.
However, I haven't found a way for random drivers to add an .init table
to avoid having to manually add
== Series Details ==
Series: drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
URL : https://patchwork.freedesktop.org/series/57619/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12387_full
Quoting Michal Wajdeczko (2019-03-06 09:01:09)
> On Wed, 06 Mar 2019 09:45:17 +0100, Chris Wilson
> > Now doing an if (i915_error_injected() && !err) err = -EINVAL; makes
> > sense to catch places where we've eaten that error and so breaking the
> > test.
>
> This will not work today, as at leas
Quoting Ville Syrjala (2019-03-05 19:29:05)
> From: Ville Syrjälä
>
> At some point people have started to assume that
> pipe_offsets[] & co. are only populated for pipes and whatnot
> that actually exist. That is in fact not currently true, but
> we can easily make it so.
Any benefits of knock
== Series Details ==
Series: drm/i915/selftests: Fix MI_STORE_DWORD_IMM alignment
URL : https://patchwork.freedesktop.org/series/57633/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12390
Summary
---
On 01/03/2019 14:03, Chris Wilson wrote:
Introduce a mutex to start locking the HW contexts independently of
struct_mutex, with a view to reducing the coarse struct_mutex. The
intel_context.pin_mutex is used to guard the transition to and from being
pinned on the gpu, and so is required before s
== Series Details ==
Series: drm/i915: Pass around the intel_context
URL : https://patchwork.freedesktop.org/series/57635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12391
Summary
---
**SUCCESS**
Quoting Tvrtko Ursulin (2019-03-06 09:45:27)
>
> On 01/03/2019 14:03, Chris Wilson wrote:
> > Introduce a mutex to start locking the HW contexts independently of
> > struct_mutex, with a view to reducing the coarse struct_mutex. The
> > intel_context.pin_mutex is used to guard the transition to an
== Series Details ==
Series: series starting with [v5,1/9] drm/i915/psr: Remove PSR2 FIXME
URL : https://patchwork.freedesktop.org/series/57628/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12388_full
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: deconflate PPS unlock from
divisor register (rev3)
URL : https://patchwork.freedesktop.org/series/57579/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12392
Hi Dave, Daniel,
A few extra patches for the 5.1 merge window.
Thanks!
Maxime
drm-misc-next-fixes-2019-03-06:
- Properly mark the ptr_to_compat argument with the __user tag
- Merge __drm_atomic_helper_disable_all into drm_atomic_helper_disable_all
The following changes since commit 6649a95d35d8
On Wed, 6 Mar 2019 at 08:25, Chris Wilson wrote:
>
> MI_STORE_DWORD_IMM wants to write into a dword-aligned (4B) address, we
> mistakenly cleared bit2 and not bits 0 and 1.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
> Cc: Mika Kuoppala
Reviewed-by: Matthew Auld
Quoting Chris Wilson (2019-03-05 21:10:42)
> Quoting Rafael Antognolli (2019-03-05 17:30:00)
> > On Tue, Mar 05, 2019 at 01:48:26PM +0100, Michał Winiarski wrote:
> > > We assumed that the default preemption granularity is fine for ICL.
> > > Unfortunately, it turns out that some drivers don't supp
Op 04-03-2019 om 16:32 schreef Rodrigo Siqueira:
> The function fb_is_bound() mix integer value with booleans for handling
> the return value. This commit standardizes the return value of
> fb_is_bound() for using only booleans.
>
> Signed-off-by: Rodrigo Siqueira
> ---
> tests/kms_flip.c | 5 ++-
On 01/03/2019 14:03, Chris Wilson wrote:
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
On 01/03/2019 14:04, Chris Wilson wrote:
Check that we have setup on preemption for the engine before testing,
instead warn if it is not enabled on supported HW.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_lrc.c | 18 ++
1 file changed, 18 insertions
Quoting Tvrtko Ursulin (2019-03-06 11:27:37)
>
> On 01/03/2019 14:03, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index 91926a407548..8c35b6019f0d 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/
On 05/03/2019 15:16, Patchwork wrote:
== Series Details ==
Series: drm/i915/selftests: Upgrade printing test/subtest name to pr_info
URL : https://patchwork.freedesktop.org/series/57582/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5703 -> Patchwork_12371
=
On 05/03/2019 11:47, Patchwork wrote:
== Series Details ==
Series: drm/i915: Relax mmap VMA check
URL : https://patchwork.freedesktop.org/series/57573/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5703 -> Patchwork_12366
On 17/02/2019 14:35, Chris Wilson wrote:
basic-allocations was written to demonstrate a flaw in our continual
reallocation of cmdparser shadow bo, largely fixed by keeping a small
cache of bo of different lengths (to speed up the search for the correct
sized bo). We only care enough to exercise
This patch series enable PC8+ residency test, earlier these tests
were only enabled for Haswell and Broadwell.
Since Gen9 onwards PC8+ residency does't require display to be turned off,
this patch series tests PC8 residency with all screens on.
Tested on Gen9, unable to test on ICL, because silico
Enabled has_pc8 global for ICL and Gen9.
Added PC8+ residency test for display enabled case as well.
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_rpm.c | 75 +++-
1 file changed, 68 insertions(+), 7 deletions(-)
diff --git a/tests/i915/i915_pm
Introduced pc8_needs_screen_off flag in order to differentiate
between HASWELL/BROADWEEL and AT_LEAST_GEN9. GEN9 onwards
PC8+ residency does't require display to be turned on.
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_rpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
== Series Details ==
Series: drm/i915/selftests: Fix MI_STORE_DWORD_IMM alignment
URL : https://patchwork.freedesktop.org/series/57633/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12390_full
Summary
On Tue, Mar 05, 2019 at 01:07:34PM -0800, Lucas De Marchi wrote:
> On Tue, Mar 05, 2019 at 03:23:48PM +0200, Jani Nikula wrote:
> >On Mon, 04 Mar 2019, Jani Nikula wrote:
> >> On Mon, 04 Mar 2019, Ville Syrjälä wrote:
> >>> On Fri, Mar 01, 2019 at 05:14:05PM -0800, Lucas De Marchi wrote:
> T
For igt_vm_isolation, we write into the whole 48b address space, and not
just our usual low 4G of global GTT. For these MI operations, play safe
and ensure we use the canonical address form.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_execbu
Preparation changes to adapt some of the GEM locking in preparation for
async-pages. Feedback on the GEM changes appreciated.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Use the per-object local lock to control the cache domain of the
individual GEM objects, not struct_mutex. This is a huge leap forward
for us in terms of object-level synchronisation; execbuffers are
coordinated using the ww_mutex and pread/pwrite is finally fully
serialised again.
Signed-off-by:
Currently the code for manipulating the pages on an object is still
residing in i915_gem.c, move it to i915_gem_object.c
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/{ => gem}/i915_gem_object.c | 3 +-
.../gpu/dr
An idea for extending uABI inspired by Vulkan's extension chains.
Instead of expanding the data struct for each ioctl every time we need
to add a new feature, define an extension chain instead. As we add
optional interfaces to control the ioctl, we define a new extension
struct that can be linked i
Continuing the decluttering of i915_gem.c by moving the client self
throttling into its own file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 74
drivers/gpu/drm/i915/i915_drv.h
Use i915_gem_object_lock() to guard the LUT and active reference to
allow us to break free of struct_mutex for handling GEM_CLOSE.
Testcase: igt/gem_close_race
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +++---
.../gpu/drm/i915/gem/i915_gem_context_types.h
Declutter i915_gem.h by moving the ioctl API into its own header.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 52 +++
.../gem/test_i915_gem_ioctls_standalone.c | 7 +++
drivers/gpu/drm/
Continuing the decluttering of i915_gem.c by moving the object wait
decomposition into its own file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 8 +
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 276 ++
Continuing the decluttering of i915_gem.c by moving the object busy
checking into its own file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 137 +++
drivers/gpu/drm/i915/i915_gem.c | 127
Continuing the decluttering of i915_gem.c
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 764 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 29 +
drivers/gpu/drm/i915/gvt/cmd_parser.c
Split the plain old shmem object into its own file to start decluttering
i915_gem.c
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.c| 300 ++-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 39 +
drivers/g
An old optimisation to reduce the number of atomics per batch sadly
relies on struct_mutex for coordination. In order to remove struct_mutex
from serialising object/context closing, always taking and releasing an
active reference on first use / last use greatly simplifies the locking.
Signed-off-b
Out scatterlist utility routines can be pulled out of i915_gem.h for a
bit more decluttering.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 1 +
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 1 +
drive
Continuing the decluttering of i915_gem.c
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 514
drivers/gpu/drm/i915/gem/i915_gem_object.c| 56 ++
drivers/gpu/drm/i915/gem/i915_gem_object.
Continuing the theme of separating out the GEM clutter.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 25 ++-
.../gpu/drm/i915/{ => gem}/i915_gem_clflush.c | 27 +++
drivers/gpu/drm/i915/gem/i915_gem_clflush.h | 20 +
.../gpu/drm/i915/{
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute load.
Introduce a mutex to start locking the HW contexts independently of
struct_mutex, with a view to reducing the coarse struct_mutex. The
intel_context.pin_mutex is used to guard the transition to and from being
pinned on the gpu, and so is required before starting to build any
request. The intel_cont
In the next patch, we will want to configure the slave request
depending on which physical engine the master request is executed on.
For this, we introduce a callback from the execute fence to convey this
information.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 84 +
In preparation for an ever growing number of engines and so ever
increasing static array of HW contexts within the GEM context, move the
array over to an rbtree, allocated upon first use.
Unfortunately, this imposes an rbtree lookup at a few frequent callsites,
but we should be able to mitigate th
Each engine acquires a pin on the kernel contexts (normal and preempt)
so that the logical state is always available on demand. Keep track of
each engines pin by storing the returned pointer on the engine for quick
access.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c
Some users require that when a master batch is executed on one particular
engine, a companion batch is run simultaneously on a specific slave
engine. For this purpose, we introduce virtual engine bonding, allowing
maps of master:slaves to be constructed to constrain which physical
engines a virtual
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy across, but it would much more
convenient i
For convenience in avoiding inline spaghetti, keep the type definition
as a separate header.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 285 +
.../test_i915_gem_object_types_standalone.c
Push the intel_context pin callback down from intel_engine_cs onto the
context itself by virtue of having a central caller for
intel_context_pin() being able to lookup the intel_context itself.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_context.c
It can be useful to have a single ioctl to create a context with all
the initial parameters instead of a series of create + setparam + setparam
ioctls. This extension to create context allows any of the parameters
to be passed in as a linked list to be applied to the newly constructed
context.
v2:
For igt_vm_isolation, we write into the whole 48b address space, and not
just our usual low 4G of global GTT. For these MI operations, play safe
and ensure we use the canonical address form.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_execbu
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance) tuples to identify a
specific engine, with a
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
local context barrier (Tvrtko)
v3: serialise
Currently we assume that we know the order in which requests run and so
can determine if we need to reissue a switch-to-kernel-context prior to
idling. That assumption does not hold for the future, so instead of
tracking which barriers have been used, simply determine if we have ever
switched away
When the system idles, we switch to the kernel context as a defensive
measure (no users are harmed if the kernel context is lost). Currently,
we issue a switch to kernel context and then come back later to see if
the kernel context is still current and the system is idle. However,
if we are no long
We load a context (the kernel context) on both module load and resume in
order to initialise some logical state onto the GPU. We can use the same
routine for both operations, which will become more useful as we
refactor rc6/rps enabling.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on virtual engines that
are local to the context
If resubmitting the active context, simply skip the submission as
performing the submission from the interrupt handler has higher
throughput than continually provoking lite-restores. If however, we find
ourselves with a new client, we check whether or not we can dequeue into
the second port or to r
Continuing the decluttering of i915_gem.c
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 482 +
We can reduce the switch-to-kernel-context selftest to operate as a loop
and so trivially test another state transition (that of idle->busy).
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 80 ---
1 file changed, 35 insertions(+), 45 deletions(-)
In the next patch, we will want to update live state within a context.
As this state may be in use by the GPU and we haven't been explicitly
tracking its activity, we instead attach it to a request we send down
the context setup with its new state and on retiring that request
cleanup the old state
Check that we have setup on preemption for the engine before testing,
instead warn if it is not enabled on supported HW.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_lrc.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftes
This complex struct pulling in half the driver deserves its own
isolation in preparation for intel_context becoming an outright
complicated class of its own.
In order to split this beast into its own header also requests splitting
several of its dependent types and their dependencies into their ow
Previously, our view has been always to run the engines independently
within a context. (Multiple engines happened before we had contexts and
timelines, so they always operated independently and that behaviour
persisted into contexts.) However, at the user level the context often
represents a singl
For use in the next patch, if we track which engines have been used by
the HW, we can reduce the work required to flush our state off the HW to
those engines.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 +--
drivers/
To facilitate the next patch to allow preemptible kernels not to incur
the wrath of hangcheck, we need to ensure that we can still suspend and
shutdown. That is we will not be able to rely on hangcheck to terminate
a blocking kernel and instead must manually do so ourselves. The
advantage is that w
If we place a pointer to the engine specific intel_context_ops in the
engine itself, we can assign the ops pointer on initialising the
context, and then rely on it being set. This simplifies the code in
later patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c |
We can no longer assume execution ordering, and in particular we cannot
assume which context will execute last. One side-effect of this is that
we cannot determine if the kernel-context is resident on the GPU, so
remove the routines that claimed to do so.
Signed-off-by: Chris Wilson
---
drivers/
Chris Wilson writes:
> Quoting Tvrtko Ursulin (2019-03-05 18:13:34)
>>
>> intel_engine.h in 3...2...1.. ;)
>
> As soon as we have a good name for the legacy submission method. At the
> moment, my favorites are:
> gen2_submission.c / legacy_submission.c (actually that's winning again)
> gen8_subm
On 06/03/2019 14:24, Chris Wilson wrote:
If we place a pointer to the engine specific intel_context_ops in the
engine itself, we can assign the ops pointer on initialising the
context, and then rely on it being set. This simplifies the code in
later patches.
Signed-off-by: Chris Wilson
---
d
On 06/03/2019 14:24, Chris Wilson wrote:
In preparation for an ever growing number of engines and so ever
increasing static array of HW contexts within the GEM context, move the
array over to an rbtree, allocated upon first use.
Unfortunately, this imposes an rbtree lookup at a few frequent cal
Chris Wilson writes:
> For igt_vm_isolation, we write into the whole 48b address space, and not
> just our usual low 4G of global GTT. For these MI operations, play safe
> and ensure we use the canonical address form.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
> Cc: Mika Kuoppala
> ---
On 06/03/2019 14:24, Chris Wilson wrote:
Introduce a mutex to start locking the HW contexts independently of
struct_mutex, with a view to reducing the coarse struct_mutex. The
intel_context.pin_mutex is used to guard the transition to and from being
pinned on the gpu, and so is required before s
There is a desire to split a task onto two engines and have them run at
the same time, e.g. scanline interleaving to spread the workload evenly.
Through the use of the out-fence from the first execbuf, we can
coordinate secondary execbuf to only become ready simultaneously with
the first, so that w
Quoting Tvrtko Ursulin (2019-03-06 14:43:13)
>
> On 06/03/2019 14:24, Chris Wilson wrote:
> > Introduce a mutex to start locking the HW contexts independently of
> > struct_mutex, with a view to reducing the coarse struct_mutex. The
> > intel_context.pin_mutex is used to guard the transition to an
On Wed, Mar 06, 2019 at 09:31:48AM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-03-05 19:29:05)
> > From: Ville Syrjälä
> >
> > At some point people have started to assume that
> > pipe_offsets[] & co. are only populated for pipes and whatnot
> > that actually exist. That is in fact n
Quoting Ville Syrjälä (2019-03-06 14:52:11)
> On Wed, Mar 06, 2019 at 09:31:48AM +, Chris Wilson wrote:
> > Quoting Ville Syrjala (2019-03-05 19:29:05)
> > > From: Ville Syrjälä
> > >
> > > At some point people have started to assume that
> > > pipe_offsets[] & co. are only populated for pipe
== Series Details ==
Series: drm/i915: Pass around the intel_context
URL : https://patchwork.freedesktop.org/series/57635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12391_full
Summary
---
*
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: deconflate PPS unlock from
divisor register (rev3)
URL : https://patchwork.freedesktop.org/series/57579/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12392_full
==
== Series Details ==
Series: series starting with [01/43] drm/i915/selftests: Canonicalise gen8
addresses
URL : https://patchwork.freedesktop.org/series/57646/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
38853354b213 drm/i915/selftests: Canonicalise gen8 addresses
9afdcdabf8
On Wed, Mar 06, 2019 at 02:55:58PM +, Chris Wilson wrote:
> Quoting Ville Syrjälä (2019-03-06 14:52:11)
> > On Wed, Mar 06, 2019 at 09:31:48AM +, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2019-03-05 19:29:05)
> > > > From: Ville Syrjälä
> > > >
> > > > At some point people have sta
== Series Details ==
Series: series starting with [01/43] drm/i915/selftests: Canonicalise gen8
addresses
URL : https://patchwork.freedesktop.org/series/57646/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/selftests: Canonicalise gen8 addres
On Tue, Mar 05, 2019 at 09:13:39PM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/2] drm/i915: Do not temporarily disable
> the DPLL on i830
> URL : https://patchwork.freedesktop.org/series/57598/
> State : failure
>
> == Summary ==
>
> CI Bug Log - chan
Iterate over child devices instead of ports in parse_ddi_ports() to
initialize dri_port_info. We'll eventually need to decide some stuff
based on the child device order, which may be different from the port
order.
As a bonus, this allows better abstractions for e.g. dvo port mapping.
There's a su
Some prep work for future changes which will be easier with ddi port info being
initialized in child device order instead of port order.
BR,
Jani.
Jani Nikula (3):
drm/i915/bios: iterate over child devices to initialize ddi_port_info
drm/i915/bios: parse dsi devices in parse_ddi_ports()
dr
The main benefit is improved debug logging of the ports also on VLV.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_bios.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 9beff569b010..0
For the time being this is only for completeness and better debug
logging of DSI ports.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 14 --
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i
== Series Details ==
Series: drm/i915/selftests: Canonicalise gen8 addresses
URL : https://patchwork.freedesktop.org/series/57645/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5711 -> Patchwork_12393
Summary
---
**F
Quoting Patchwork (2019-03-06 15:42:32)
> == Series Details ==
>
> Series: drm/i915/selftests: Canonicalise gen8 addresses
> URL : https://patchwork.freedesktop.org/series/57645/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5711 -> Patchwork_12393
>
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