== Series Details ==
Series: drm/i915: Implement HDCP2.2 (rev2)
URL : https://patchwork.freedesktop.org/series/56453/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5584_full -> Patchwork_12188_full
Summary
---
**FAIL
== Series Details ==
Series: Add support for Gen 11 pipe color features (rev7)
URL : https://patchwork.freedesktop.org/series/51408/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5584_full -> Patchwork_12189_full
Summary
--
On Fri, Feb 08, 2019 at 03:01:03PM +0100, Noralf Trønnes wrote:
> This makes it possible to use drm_dev_unplug() with the upcoming
> devm_drm_dev_init() which will do drm_dev_put() in its release callback.
>
> Cc: Alex Deucher
> Cc: Christian König
> Cc: David (ChunMing) Zhou
> Cc: Dave Airlie
On Sat, Feb 09, 2019 at 12:42:30PM +0530, Ramalingam C wrote:
> From: Daniel Vetter
>
> Now that component has docs it's worth spending a few words and
> hyperlinks on recommended best practices in drm.
>
> Cc: Russell King - ARM Linux admin
> Signed-off-by: Daniel Vetter
Just a quick reminde
Am Donnerstag, 31. Januar 2019, 01:00:34 CET schrieb Matt Roper:
> CRTC background color kernel patches were written about 2.5 years ago
> and floated on the upstream mailing list, but since no opensource
> userspace materialized, we never actually merged them. However the
> corresponding IGT test
Add support for icl pipe degamma and gamma.
v2: Removed a POSTING_READ and corrected the Bit
Definition as per Maarten's comments.
v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.
v4: Fixed Matt's review comments.
v5: Corrected macro alignment as per Jani Nikula'
GEN11+ onwards an output csc hardware block has been added.
This is after the pipe gamma block and is in addition to the
legacy pipe CSC block. Primary use case for this block is to
convert RGB to YUV in case sink supports YUV.
This patch adds supports for the same.
v2: This is added after splitti
This patch series adds support for Gen11 pipe degamma, CSC
and gamma hardware blocks.
CRC checks are not working for 10bit gamma but works for 8bit
pallete modes which seems to be due to some rounding errors in
pipe. Also there is a corner case where Lut precision is increased
to 3.16, hence its n
Add the degamma and gamma lut sizes to gen11 capability
structure.
Note: Currently this doesn't account for the extended range gamma
entries and this will be addressed with new segmented gamma ABI
in a future patch.
v2: Reorder the patch as per Maarten's suggestion.
v3: Rebase
v4: Updated commi
Fixed the glk degamma lut programming which currently
was hard coding a linear lut all the time, making degamma
block of glk basically a pass through.
Currently degamma lut for glk is assigned as 0 in platform
configuration. Updated the same to 33 as per the hardware
capability. IGT tests for dega
Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.
ToDO: Extend the ABI to accept 32 bit coefficient values
instead of 16bit for future platforms.
v2: Addressed Maarten's review comments.
v3: Addressed Matt's review comments. Removed rmw patterns
On 08/02/2019 13:58, Eero Tamminen wrote:
Hi,
On 8.2.2019 14.03, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Two new output modes are added: listing of text data to standard out (-l
on the command line), and dumping of JSON formatted records (-J), also to
standard out.
The first mode is sele
On 08/02/2019 13:47, Chris Wilson wrote:
If we allocate while iterating the rbtree of active nodes, we may hit
the shrinker and so retire the i915_active reap the rbtree. Modifying
the rbtree as we iterate is not good behaviour, so acquire the
i915_active first to keep the tree intact whenever w
On 06/02/2019 13:03, Chris Wilson wrote:
WAIT is occasionally suppressed by virtue of preempted requests being
promoted to NEWCLIENT if they have not all ready received that boost.
Make this consistent for all WAIT boosts that they are not allowed to
preempt executing contexts and are merely gra
Op 11-02-2019 om 10:26 schreef Uma Shankar:
> Add support for icl pipe degamma and gamma.
>
> v2: Removed a POSTING_READ and corrected the Bit
> Definition as per Maarten's comments.
>
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
>
> v4: Fixed Matt's review c
Op 11-02-2019 om 10:26 schreef Uma Shankar:
> Add the degamma and gamma lut sizes to gen11 capability
> structure.
>
> Note: Currently this doesn't account for the extended range gamma
> entries and this will be addressed with new segmented gamma ABI
> in a future patch.
>
> v2: Reorder the patch a
== Series Details ==
Series: Add support for Gen 11 pipe color features (rev8)
URL : https://patchwork.freedesktop.org/series/51408/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5585_full -> Patchwork_12190_full
Summary
--
On 07/02/2019 18:52, Chris Wilson wrote:
When a request has its priority changed, we traverse the graph of all of
its signalers to raise their priorities to match (priority inheritance).
If the request has already started executing its payload, we know that
all of its signalers must have signale
On 06/02/2019 13:03, Chris Wilson wrote:
As kmem_caches share the same properties (size, allocation/free behaviour)
for all potential devices, we can use global caches. While this
potential has worse fragmentation behaviour (one can argue that
different devices would have different activity life
From: Tvrtko Ursulin
Two new output modes are added: listing of text data to standard out (-l
on the command line), and dumping of JSON formatted records (-J), also to
standard out.
The first mode is selected automatically when non-interactive standard out
is detected.
Example of text output:
From: Tvrtko Ursulin
A new -o command switch enables logging to a file.
v2:
* Support "-o -" for explicit stdout selection. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
References: https://bugs.freedesktop.org/show_bug.cgi?id=108689
Cc: Eero Tamminen
Cc: 3.1...@ukr.net
Cc: Chris Wilson
Revi
Quoting Tvrtko Ursulin (2019-02-11 11:45:22)
> +static enum {
> + INTERACTIVE,
> + STDOUT,
> + JSON
> +} output_mode;
> +
> +struct cnt_item {
> + struct pmu_counter *pmu;
/* "%*.*f", fmt_d, fmt_dd, X */
I tried fmt_d == fmt_width and fmt_dd == fmt_decimals
It's called fi
On 06/02/2019 13:03, Chris Wilson wrote:
Do a pass over all the engines upon starting to determine the global
scheduler capability flags (those that are agreed upon by all).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
drivers/gpu/drm/i915/intel_engine_cs
Quoting Tvrtko Ursulin (2019-02-11 12:24:31)
>
> On 06/02/2019 13:03, Chris Wilson wrote:
> > Do a pass over all the engines upon starting to determine the global
> > scheduler capability flags (those that are agreed upon by all).
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm
On 06/02/2019 13:03, Chris Wilson wrote:
To determine whether an engine has 'stuck', we simply check whether or
not is still on the same seqno for several seconds. To keep this simple
mechanism intact over the loss of a global seqno, we can simply add a
new global heartbeat seqno instead. As we
Quoting Tvrtko Ursulin (2019-02-11 11:43:41)
>
> On 06/02/2019 13:03, Chris Wilson wrote:
> > As kmem_caches share the same properties (size, allocation/free behaviour)
> > for all potential devices, we can use global caches. While this
> > potential has worse fragmentation behaviour (one can argu
Quoting Tvrtko Ursulin (2019-02-11 12:40:07)
>
> On 06/02/2019 13:03, Chris Wilson wrote:
> > To determine whether an engine has 'stuck', we simply check whether or
> > not is still on the same seqno for several seconds. To keep this simple
> > mechanism intact over the loss of a global seqno, we
Quoting Tvrtko Ursulin (2019-02-11 11:13:12)
>
> On 08/02/2019 13:47, Chris Wilson wrote:
> > If we allocate while iterating the rbtree of active nodes, we may hit
> > the shrinker and so retire the i915_active reap the rbtree. Modifying
> > the rbtree as we iterate is not good behaviour, so acqui
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Monday, February 11, 2019 4:51 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [v8 2/5] drm/i915/icl: Add icl pipe deg
While this is mainly only useful for ELSP[0], it is definitely useful to
know the current timeline seqno wrt to the queued set of requests for
that port, as this carries additional information above and beyond the
near-defunct global_seqno and global HWSP.
Signed-off-by: Chris Wilson
---
drivers
Op 11-02-2019 om 14:01 schreef Shankar, Uma:
>
>> -Original Message-
>> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>> Sent: Monday, February 11, 2019 4:51 PM
>> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>> Cc: Syrjala, Ville ; Lankhorst, Maarten
>>
>> Subje
GEN11+ onwards an output csc hardware block has been added.
This is after the pipe gamma block and is in addition to the
legacy pipe CSC block. Primary use case for this block is to
convert RGB to YUV in case sink supports YUV.
This patch adds supports for the same.
v2: This is added after splitti
Add support for icl pipe degamma and gamma.
v2: Removed a POSTING_READ and corrected the Bit
Definition as per Maarten's comments.
v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.
v4: Fixed Matt's review comments.
v5: Corrected macro alignment as per Jani Nikula'
Add the degamma and gamma lut sizes to gen11 capability
structure.
Note: Currently this doesn't account for the extended range gamma
entries and this will be addressed with new segmented gamma ABI
in a future patch.
v2: Reorder the patch as per Maarten's suggestion.
v3: Rebase
v4: Updated commi
Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.
ToDO: Extend the ABI to accept 32 bit coefficient values
instead of 16bit for future platforms.
v2: Addressed Maarten's review comments.
v3: Addressed Matt's review comments. Removed rmw patterns
Fixed the glk degamma lut programming which currently
was hard coding a linear lut all the time, making degamma
block of glk basically a pass through.
Currently degamma lut for glk is assigned as 0 in platform
configuration. Updated the same to 33 as per the hardware
capability. IGT tests for dega
This patch series adds support for Gen11 pipe degamma, CSC
and gamma hardware blocks.
CRC checks are not working for 10bit gamma but works for 8bit
pallete modes which seems to be due to some rounding errors in
pipe. Also there is a corner case where Lut precision is increased
to 3.16, hence its n
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Monday, February 11, 2019 6:54 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [v8 2/5] drm/i915/icl: Add icl pipe deg
We need to flush our srcu protecting resources about to be clobbered
by the reset, inside of our timer failsafe but outside of the
error->wedge_mutex, so that the failsafe can run in case the
synchronize_srcu() takes too long (hits a shrinker deadlock?).
Fixes: 72eb16df010a ("drm/i915: Serialise r
We need to flush our srcu protecting resources about to be clobbered
by the reset, inside of our timer failsafe but outside of the
error->wedge_mutex, so that the failsafe can run in case the
synchronize_srcu() takes too long (hits a shrinker deadlock?).
Fixes: 72eb16df010a ("drm/i915: Serialise r
We impose upon ourselves a strict timeout for resets (to ensure forward
progress by use of a failsafe). Prefer to use the expedited
synchronisation function in this case to reduce the likelihood of a
spurious delay being treated as a deadlock.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
d
== Series Details ==
Series: drm/i915: Include the current timeline seqno for debugging execlists
URL : https://patchwork.freedesktop.org/series/56493/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5588 -> Patchwork_12191
S
basic-allocations was written to demonstrate a flaw in our continual
reallocation of cmdparser shadow bo, largely fixed by keeping a small
cache of bo of different lengths (to speed up the search for the correct
sized bo). We only care enough to exercise the slowdown by submitting
lots of execbufs,
On Wed, 30 Jan 2019 at 20:03, Chris Wilson wrote:
>
> Quoting Matthew Auld (2019-01-30 19:18:25)
> > Break on NULL iter.sgp, rather than dmap == 0, on the off chance that we
> > have some hypothetical selftest or similar in the future that considers
> > dmap = 0 to be perfectly valid.
>
> 0 == DMA
== Series Details ==
Series: Add support for Gen 11 pipe color features (rev9)
URL : https://patchwork.freedesktop.org/series/51408/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5588 -> Patchwork_12192
Summary
---
*
Quoting Matthew Auld (2019-02-11 14:39:38)
> On Wed, 30 Jan 2019 at 20:03, Chris Wilson wrote:
> >
> > Quoting Matthew Auld (2019-01-30 19:18:25)
> > > Break on NULL iter.sgp, rather than dmap == 0, on the off chance that we
> > > have some hypothetical selftest or similar in the future that consi
== Series Details ==
Series: drm/i915: Pull sync_scru for device reset outside of wedge_mutex
URL : https://patchwork.freedesktop.org/series/56495/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5588 -> Patchwork_12193
Summa
Quoting Chris Wilson (2019-02-11 15:45:30)
> If we drop the engine lock, we may run execlists_dequeue which may free
> the priolist. Therefore if we ever drop the execution lock on the
> engine, we have to discard our cache and refetch the priolist to ensure
> we do not use a stale pointer.
>
> [
If we drop the engine lock, we may run execlists_dequeue which may free
the priolist. Therefore if we ever drop the execution lock on the
engine, we have to discard our cache and refetch the priolist to ensure
we do not use a stale pointer.
[ 506.418935] [IGT] gem_exec_whisper: starting subtest c
== Series Details ==
Series: series starting with [1/2] drm/i915: Pull sync_scru for device reset
outside of wedge_mutex
URL : https://patchwork.freedesktop.org/series/56496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5588 -> Patchwork_12194
===
If we drop the engine lock, we may run execlists_dequeue which may free
the priolist. Therefore if we ever drop the execution lock on the
engine, we have to discard our cache and refetch the priolist to ensure
we do not use a stale pointer.
[ 506.418935] [IGT] gem_exec_whisper: starting subtest c
Chris Wilson writes:
> We need to flush our srcu protecting resources about to be clobbered
> by the reset, inside of our timer failsafe but outside of the
> error->wedge_mutex, so that the failsafe can run in case the
> synchronize_srcu() takes too long (hits a shrinker deadlock?).
>
> Fixes: 72
On 11/02/2019 12:44, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-02-11 12:40:07)
On 06/02/2019 13:03, Chris Wilson wrote:
To determine whether an engine has 'stuck', we simply check whether or
not is still on the same seqno for several seconds. To keep this simple
mechanism intact over t
Chris Wilson writes:
> We impose upon ourselves a strict timeout for resets (to ensure forward
> progress by use of a failsafe). Prefer to use the expedited
> synchronisation function in this case to reduce the likelihood of a
> spurious delay being treated as a deadlock.
5 seconds of spurious d
Hi all,
Here's the typed component topic branch.
drm-intel maintainers: Please pull, I need this for the mei hdcp work from Ram.
drm-misc maintainers: Please pull, there's a drm doc patch follow-up
that I want to stuff into drm-misc-next.
Greg: The drm side missed our feature cutoff, so will on
On 11/02/2019 12:21, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-02-11 11:45:22)
+static enum {
+ INTERACTIVE,
+ STDOUT,
+ JSON
+} output_mode;
+
+struct cnt_item {
+ struct pmu_counter *pmu;
/* "%*.*f", fmt_d, fmt_dd, X */
I tried fmt_d == fmt_width and fmt_dd =
Quoting Mika Kuoppala (2019-02-11 15:09:48)
> Chris Wilson writes:
>
> > We need to flush our srcu protecting resources about to be clobbered
> > by the reset, inside of our timer failsafe but outside of the
> > error->wedge_mutex, so that the failsafe can run in case the
> > synchronize_srcu() t
On 11/02/2019 12:40, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-02-11 11:43:41)
On 06/02/2019 13:03, Chris Wilson wrote:
As kmem_caches share the same properties (size, allocation/free behaviour)
for all potential devices, we can use global caches. While this
potential has worse fragmen
On Fri, 08 Feb 2019, Ville Syrjälä wrote:
> On Fri, Feb 08, 2019 at 09:00:59PM +0200, Jani Nikula wrote:
>> On Fri, 08 Feb 2019, Ville Syrjälä wrote:
>> > On Fri, Feb 08, 2019 at 08:42:53PM +0200, Jani Nikula wrote:
>> >> Starting from opregion version 2.1 (roughly corresponding to ICL+) the
>> >
Quoting Mika Kuoppala (2019-02-11 15:13:19)
> Chris Wilson writes:
>
> > We impose upon ourselves a strict timeout for resets (to ensure forward
> > progress by use of a failsafe). Prefer to use the expedited
> > synchronisation function in this case to reduce the likelihood of a
> > spurious del
On 11/02/2019 14:35, Chris Wilson wrote:
basic-allocations was written to demonstrate a flaw in our continual
reallocation of cmdparser shadow bo, largely fixed by keeping a small
cache of bo of different lengths (to speed up the search for the correct
sized bo). We only care enough to exercise
On 11/02/2019 13:10, Chris Wilson wrote:
While this is mainly only useful for ELSP[0], it is definitely useful to
know the current timeline seqno wrt to the queued set of requests for
that port, as this carries additional information above and beyond the
near-defunct global_seqno and global HWSP
== Series Details ==
Series: drm/i915: Include the current timeline seqno for debugging execlists
URL : https://patchwork.freedesktop.org/series/56493/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5588_full -> Patchwork_12191_full
=
Quoting Tvrtko Ursulin (2019-02-11 17:18:02)
>
> On 11/02/2019 14:35, Chris Wilson wrote:
> > basic-allocations was written to demonstrate a flaw in our continual
> > reallocation of cmdparser shadow bo, largely fixed by keeping a small
> > cache of bo of different lengths (to speed up the search
On 11/02/2019 16:09, Chris Wilson wrote:
> If we drop the engine lock, we may run execlists_dequeue which may free
> the priolist. Therefore if we ever drop the execution lock on the
> engine, we have to discard our cache and refetch the priolist to ensure
> we do not use a stale pointer.
On firs
This simplifies adding new query item objects.
v2: Use query_hdr (Tvrtko, Chris).
int instead of u32 in return (Tvrtko)
v3: More naming fixes (Tvrtko)
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_query.c | 39 ---
1 file chang
Quoting Tvrtko Ursulin (2019-02-11 17:33:37)
>
> On 11/02/2019 16:09, Chris Wilson wrote:
> > If we drop the engine lock, we may run execlists_dequeue which may free
> > the priolist. Therefore if we ever drop the execution lock on the
> > engine, we have to discard our cache and refetch the priol
== Series Details ==
Series: Add support for Gen 11 pipe color features (rev9)
URL : https://patchwork.freedesktop.org/series/51408/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5588_full -> Patchwork_12192_full
Summary
--
On 11/02/2019 17:32, Abdiel Janulgue wrote:
This simplifies adding new query item objects.
v2: Use query_hdr (Tvrtko, Chris).
int instead of u32 in return (Tvrtko)
v3: More naming fixes (Tvrtko)
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_query.c |
Take responsibility for the state we create, and in particular remember
to kill our child process (the hang detector) before exiting.
Reported-by: Daniel Vetter
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
---
tests/i915/gem_exec_reuse.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(
On 11/02/2019 17:44, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-02-11 17:33:37)
On 11/02/2019 16:09, Chris Wilson wrote:
If we drop the engine lock, we may run execlists_dequeue which may free
the priolist. Therefore if we ever drop the execution lock on the
engine, we have to discard o
On 06/02/2019 13:03, Chris Wilson wrote:
As time goes by, usage of generic ioctls such as drm_syncobj and
sync_file are on the increase bypassing i915-specific ioctls like
GEM_WAIT. Currently, we only apply waitboosting to our driver ioctls as
we track the file/client and account the waitboostin
>
> Request to ME to verify the M_Prime received from the HDCP sink.
>
> ME FW will calculate the M and compare with M_prime received as part of
> RepeaterAuth_Stream_Ready, which is HDCP2.2 protocol msg.
>
> On successful completion of this stage, downstream propagation of the stream
> managem
On 06/02/2019 13:03, Chris Wilson wrote:
As we no longer have a precise indication of requests queued to an
engine, make no presumptions and just sample the ring registers to see
if the engine is busy.
v2: Report busy while the ring is idling on a semaphore/event.
I was planning to take care
On 06/02/2019 13:03, Chris Wilson wrote:
Stop accessing the HWSP to read the global seqno, and stop tracking the
mirror in the engine's execution timeline -- it is unused.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gpu_error.c | 4 --
drivers/gpu/drm/i915/i915_gpu_er
Hi Daniel.
On Mon, Feb 11, 2019 at 06:15:20PM +0100, Daniel Vetter wrote:
> Hi all,
>
> Here's the typed component topic branch.
>
> drm-intel maintainers: Please pull, I need this for the mei hdcp work from
> Ram.
>
> drm-misc maintainers: Please pull, there's a drm doc patch follow-up
> that
== Series Details ==
Series: drm/i915: Reacquire priolist cache after dropping the engine lock (rev2)
URL : https://patchwork.freedesktop.org/series/56501/
State : failure
== Summary ==
Applying: drm/i915: Reacquire priolist cache after dropping the engine lock
error: patch failed: drivers/gpu
On 11/02/19 09:52, Chris Wilson wrote:
Take responsibility for the state we create, and in particular remember
to kill our child process (the hang detector) before exiting.
Reported-by: Daniel Vetter
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
---
tests/i915/gem_exec_reuse.c | 5 -
On 06/02/2019 13:03, Chris Wilson wrote:
Having weaned the interrupt handling off using a single global execution
queue, we no longer need to emit a global_seqno.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gpu_error.c | 35 ++---
drivers/gpu/drm/i915/i915_gpu_
On Mon, Feb 11, 2019 at 7:25 PM Sam Ravnborg wrote:
>
> Hi Daniel.
>
> On Mon, Feb 11, 2019 at 06:15:20PM +0100, Daniel Vetter wrote:
> > Hi all,
> >
> > Here's the typed component topic branch.
> >
> > drm-intel maintainers: Please pull, I need this for the mei hdcp work from
> > Ram.
> >
> > dr
On 06/02/2019 13:03, Chris Wilson wrote:
In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.
Signed-off-
== Series Details ==
Series: drm/i915/query: Split out query item checks (rev3)
URL : https://patchwork.freedesktop.org/series/54917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5589 -> Patchwork_12197
Summary
---
On Mon, 11 Feb 2019 19:25:12 +0100,
Sam Ravnborg wrote:
>
> Hi Daniel.
>
> On Mon, Feb 11, 2019 at 06:15:20PM +0100, Daniel Vetter wrote:
> > Hi all,
> >
> > Here's the typed component topic branch.
> >
> > drm-intel maintainers: Please pull, I need this for the mei hdcp work from
> > Ram.
> >
== Series Details ==
Series: drm/i915: Pull sync_scru for device reset outside of wedge_mutex
URL : https://patchwork.freedesktop.org/series/56495/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5588_full -> Patchwork_12193_full
=
On 06/02/2019 13:03, Chris Wilson wrote:
An idea for extending uABI inspired by Vulkan's extension chains.
Instead of expanding the data struct for each ioctl every time we need
to add a new feature, define an extension chain instead. As we add
optional interfaces to control the ioctl, we define
On 06/02/2019 13:03, Chris Wilson wrote:
For use in the next patch, if we track which engines have been used by
the HW, we can reduce the work required to flush our state off the HW to
those engines.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
driv
Quoting Chris Wilson (2019-02-11 17:23:57)
> Quoting Tvrtko Ursulin (2019-02-11 17:18:02)
> > I'd prefer if we just let it run and don't involve wedge/unwedge. Well
> > actually... we could modify the submit loop to sync a bit rather than
> > build a queue for 20 seconds? Would sync after each ex
Reviewed-by: Clint Taylor
-Clint
On 2/8/19 12:05, Ville Syrjala wrote:
From: Ville Syrjälä
Currently we're only dumping out the ddb allocation changes, let's do
the same for the watermarks. This should help with debugging underruns
and whatnot.
First I tried one line per plane per wm leve
If we drop the engine lock, we may run execlists_dequeue which may free
the priolist. Therefore if we ever drop the execution lock on the
engine, we have to discard our cache and refetch the priolist to ensure
we do not use a stale pointer.
[ 506.418935] [IGT] gem_exec_whisper: starting subtest c
On Mon, Feb 11, 2019 at 08:18:04PM +0100, Daniel Vetter wrote:
> On Mon, Feb 11, 2019 at 7:57 PM Takashi Iwai wrote:
> >
> > On Mon, 11 Feb 2019 19:25:12 +0100,
> > Sam Ravnborg wrote:
> > >
> > > Hi Daniel.
> > >
> > > On Mon, Feb 11, 2019 at 06:15:20PM +0100, Daniel Vetter wrote:
> > > > Hi all,
== Series Details ==
Series: series starting with [1/2] drm/i915: Pull sync_scru for device reset
outside of wedge_mutex
URL : https://patchwork.freedesktop.org/series/56496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5588_full -> Patchwork_12194_full
=
On Mon, Feb 11, 2019 at 7:57 PM Takashi Iwai wrote:
>
> On Mon, 11 Feb 2019 19:25:12 +0100,
> Sam Ravnborg wrote:
> >
> > Hi Daniel.
> >
> > On Mon, Feb 11, 2019 at 06:15:20PM +0100, Daniel Vetter wrote:
> > > Hi all,
> > >
> > > Here's the typed component topic branch.
> > >
> > > drm-intel maint
Quoting Patchwork (2019-02-11 19:38:40)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Pull sync_scru for device reset
> outside of wedge_mutex
> URL : https://patchwork.freedesktop.org/series/56496/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI
As a debug aide for CI, include the GEM trace up to the point the reset
times out to try and work out where/why it is timing out.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu
== Series Details ==
Series: drm/i915: Reacquire priolist cache after dropping the engine lock (rev3)
URL : https://patchwork.freedesktop.org/series/56501/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5590 -> Patchwork_12198
===
== Series Details ==
Series: drm/i915: Show the GEM trace if reset times out
URL : https://patchwork.freedesktop.org/series/56512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5590 -> Patchwork_12199
Summary
---
**S
== Series Details ==
Series: drm/i915: Reacquire priolist cache after dropping the engine lock (rev3)
URL : https://patchwork.freedesktop.org/series/56501/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5590_full -> Patchwork_12198_full
=
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