Op 11-02-2019 om 14:01 schreef Shankar, Uma:
>
>> -----Original Message-----
>> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>> Sent: Monday, February 11, 2019 4:51 PM
>> To: Shankar, Uma <uma.shan...@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Syrjala, Ville <ville.syrj...@intel.com>; Lankhorst, Maarten
>> <maarten.lankho...@intel.com>
>> Subject: Re: [Intel-gfx] [v8 2/5] drm/i915/icl: Add icl pipe degamma and
>> gamma
>> support
>>
>> Op 11-02-2019 om 10:26 schreef Uma Shankar:
>>> Add support for icl pipe degamma and gamma.
>>>
>>> v2: Removed a POSTING_READ and corrected the Bit Definition as per
>>> Maarten's comments.
>>>
>>> v3: Addressed Matt's review comments. Removed rmw patterns as
>>> suggested by Matt.
>>>
>>> v4: Fixed Matt's review comments.
>>>
>>> v5: Corrected macro alignment as per Jani Nikula's comments.
>>> Addressed Ville and Matt's review comments.
>>>
>>> v6: Merged ICL degamma handling with GLK and dropped ICL degamma
>>> function as per Ville and Matt's comments.
>>>
>>> v7: updated gamma_mode state with pre csc gammma and post gamma
>>> enabling in intel_color_check to align with atomic.
>>>
>>> Signed-off-by: Uma Shankar <uma.shan...@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_reg.h | 12 +++++++-----
>>> drivers/gpu/drm/i915/intel_color.c | 32
>>> ++++++++++++++++++++++++++++++--
>>> 2 files changed, 37 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h index 11bf60d..13a207a 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -7111,11 +7111,13 @@ enum {
>>> #define _GAMMA_MODE_A 0x4a480
>>> #define _GAMMA_MODE_B 0x4ac80
>>> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
>> _GAMMA_MODE_B)
>>> -#define GAMMA_MODE_MODE_MASK (3 << 0)
>>> -#define GAMMA_MODE_MODE_8BIT (0 << 0)
>>> -#define GAMMA_MODE_MODE_10BIT (1 << 0)
>>> -#define GAMMA_MODE_MODE_12BIT (2 << 0)
>>> -#define GAMMA_MODE_MODE_SPLIT (3 << 0)
>>> +#define PRE_CSC_GAMMA_ENABLE (1 << 31)
>>> +#define POST_CSC_GAMMA_ENABLE (1 << 30)
>>> +#define GAMMA_MODE_MODE_MASK (3 << 0)
>>> +#define GAMMA_MODE_MODE_8BIT (0 << 0)
>>> +#define GAMMA_MODE_MODE_10BIT (1 << 0)
>>> +#define GAMMA_MODE_MODE_12BIT (2 << 0)
>>> +#define GAMMA_MODE_MODE_SPLIT (3 << 0)
>>>
>>> /* DMC/CSR */
>>> #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
>>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>>> b/drivers/gpu/drm/i915/intel_color.c
>>> index 4e13286..0fcaae4 100644
>>> --- a/drivers/gpu/drm/i915/intel_color.c
>>> +++ b/drivers/gpu/drm/i915/intel_color.c
>>> @@ -583,6 +583,28 @@ static void glk_load_luts(const struct intel_crtc_state
>> *crtc_state)
>>> }
>>> }
>>>
>>> +static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>>> +{
>>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>> + enum pipe pipe = crtc->pipe;
>>> +
>>> + glk_load_degamma_lut(crtc_state);
>>> +
>>> + if (crtc_state_is_legacy_gamma(crtc_state)) {
>>> + i9xx_load_luts(crtc_state);
>>> + } else {
>>> + /* ToDo: Add support for multi segment gamma LUT */
>>> + bdw_load_gamma_lut(crtc_state, 0);
>>> +
>>> + /*
>>> + * Reset the index, otherwise it prevents the legacy
>>> + * palette to be written properly.
>>> + */
>>> + I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>>> + }
>>> +}
>>> +
>> Perhaps this write should be moved to bdw_load_gamma_lut() ?
>>
>> Seems we might also fix the same missing write in glk_load_luts() then..
> Thanks Maarten for reviewing this series.
>
> Ok Sure, will move this to bdw_load_gamma_lut(). Can I add your RB on this
> patch also with this fix ?
>
> Will send out the next version once you confirm.
Yes. :)
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