On Thu, 2018-11-08 at 19:47 +0200, Ville Syrjälä wrote:
> On Fri, Nov 02, 2018 at 12:06:03PM +0200, Stanislav Lisovskiy wrote:
> > v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV.
> > Added comment about AYUV byte ordering in Gstreamer.
> >
> > v3: Removed sna_composite_op flags related cha
== Series Details ==
Series: drm: Check if primary mst is null (rev2)
URL : https://patchwork.freedesktop.org/series/52174/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5109 -> Patchwork_10786 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://pat
Chris Wilson writes:
> Make the rcu_head known to the system, in particular for debugobjects.
> And having declared it for debugobjects, we need to tidy up afterwards.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108691
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i9
Unfortunately drm_dp_get_mst_branch_device which is called from both
drm_dp_mst_handle_down_rep and drm_dp_mst_handle_up_rep seem to rely
on that mgr->mst_primary is not NULL, which seem to be wrong as it can be
cleared with simultaneous mode set, if probing fails or in other case.
mgr->lock mutex
Quoting Mika Kuoppala (2018-11-09 08:40:56)
> Chris Wilson writes:
>
> > Make the rcu_head known to the system, in particular for debugobjects.
> > And having declared it for debugobjects, we need to tidy up afterwards.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108691
> > Sig
Make the rcu_head known to the system, in particular for debugobjects.
And having declared it for debugobjects, we need to tidy up afterwards.
v2: mark the obj->rcu as being destroy when we reuse its location for
the freed list.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108691
Signed
== Series Details ==
Series: drm/i915/icl: replace check for combo phy
URL : https://patchwork.freedesktop.org/series/52269/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5109 -> Patchwork_10787 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_1078
== Series Details ==
Series: drm: Check if primary mst is null (rev3)
URL : https://patchwork.freedesktop.org/series/52174/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5109 -> Patchwork_10788 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://pat
== Series Details ==
Series: drm/dp_mst: Improve VCPI helpers, use in nouveau (rev5)
URL : https://patchwork.freedesktop.org/series/51412/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5107_full -> Patchwork_10783_full =
== Summary - WARNING ==
Minor unknown changes comi
Introduced new XYUV scan-in format for framebuffer and
added support for it to i915(SkyLake+).
Stanislav Lisovskiy (2):
drm: Introduce new DRM_FORMAT_XYUV
drm/i915: Adding YUV444 packed format support for skl+
drivers/gpu/drm/drm_fourcc.c | 1 +
drivers/gpu/drm/i915/i915_reg.h
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use
== Series Details ==
Series: series starting with drm/i915: Initialise the obj->rcu head (rev2)
URL : https://patchwork.freedesktop.org/series/52215/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5109 -> Patchwork_10789 =
== Summary - WARNING ==
Minor unknown changes com
== Series Details ==
Series: Add XYUV format support (rev10)
URL : https://patchwork.freedesktop.org/series/48007/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6fceb8451e96 drm: Introduce new DRM_FORMAT_XYUV
-:36: WARNING:LONG_LINE: line over 100 characters
#36: FILE: drivers/
== Series Details ==
Series: Add XYUV format support (rev10)
URL : https://patchwork.freedesktop.org/series/48007/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5109 -> Patchwork_10790 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10790 absolute
Chris Wilson writes:
> Make the rcu_head known to the system, in particular for debugobjects.
> And having declared it for debugobjects, we need to tidy up afterwards.
>
> v2: mark the obj->rcu as being destroy when we reuse its location for
> the freed list.
>
> Bugzilla: https://bugs.freedeskto
Quoting Mika Kuoppala (2018-11-09 10:32:30)
> Chris Wilson writes:
>
> > Make the rcu_head known to the system, in particular for debugobjects.
> > And having declared it for debugobjects, we need to tidy up afterwards.
> >
> > v2: mark the obj->rcu as being destroy when we reuse its location for
== Series Details ==
Series: drm/i915/query: fix subslice length
URL : https://patchwork.freedesktop.org/series/52270/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5108_full -> Patchwork_10784_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10
On 09/11/2018 00:40, Daniele Ceraolo Spurio wrote:
We dump the info as an array of u8, so we want to know the length
in number of bytes. Current code is still safe because the
variable we use BITS_PER_TYPE on is a u8.
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spur
Chris Wilson writes:
> While our little rcu worker might be able to be replaced now by the
> dedicated rcu_work, in the meantime we should mark up the rcu_head for
> correct debugobjects tracking.
>
> Signed-off-by: Chris Wilson
I got distracted on looking how the epoch works.
Reviewed-by: Mik
Quoting Tvrtko Ursulin (2018-11-09 07:30:34)
>
> On 08/11/2018 16:48, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-08 16:23:08)
> >>
> >> On 08/11/2018 08:17, Chris Wilson wrote:
> >>> Ignore trying to shrink from i915 if we fail to acquire the struct_mutex
> >>> in the shrinker while p
== Series Details ==
Series: drm: Check if primary mst is null (rev3)
URL : https://patchwork.freedesktop.org/series/52174/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5109_full -> Patchwork_10788_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patch
On Wed, Nov 07, 2018 at 08:39:24PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/ddi: Add more sanity check to the
> encoder HW readout
> URL : https://patchwork.freedesktop.org/series/52187/
> State : failure
>
> == Summary ==
>
> = CI Bug Log
On 09/11/2018 14:40, Deak, Imre wrote:
> On Wed, Nov 07, 2018 at 08:39:24PM +, Patchwork wrote:
>> == Series Details ==
>>
>> Series: series starting with [1/2] drm/i915/ddi: Add more sanity check to
>> the encoder HW readout
>> URL : https://patchwork.freedesktop.org/series/52187/
>> State
On Fri, Nov 09, 2018 at 10:18:50AM +0200, Lisovskiy, Stanislav wrote:
> On Thu, 2018-11-08 at 19:47 +0200, Ville Syrjälä wrote:
> > On Fri, Nov 02, 2018 at 12:06:03PM +0200, Stanislav Lisovskiy wrote:
> > > v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV.
> > > Added comment about AYUV byte
== Series Details ==
Series: series starting with [1/2] drm/i915/ddi: Add more sanity check to the
encoder HW readout
URL : https://patchwork.freedesktop.org/series/52187/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5100 -> Patchwork_10758 =
== Summary - SUCCESS ==
No
On Fri, Nov 09, 2018 at 12:09:40AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/ddi: Add more sanity check to the
> encoder HW readout
> URL : https://patchwork.freedesktop.org/series/52187/
> State : success
>
> == Summary ==
>
> = CI Bug Log
== Series Details ==
Series: drm: Check if primary mst is null (rev2)
URL : https://patchwork.freedesktop.org/series/52174/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5109_full -> Patchwork_10786_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwo
== Series Details ==
Series: drm: Check if primary mst is null (rev3)
URL : https://patchwork.freedesktop.org/series/52174/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5109_full -> Patchwork_10788_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patch
== Series Details ==
Series: series starting with drm/i915: Initialise the obj->rcu head (rev2)
URL : https://patchwork.freedesktop.org/series/52215/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5109_full -> Patchwork_10789_full =
== Summary - WARNING ==
Minor unknown c
On Thu, Nov 08, 2018 at 02:06:52PM -0800, Matt Roper wrote:
> On Thu, Nov 01, 2018 at 05:05:58PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The plane color correction registers are single buffered. So
> > ideally we would write them at the start of vblank just after the
> > doubl
This got duplicated on introducing icl workarounds.
Fix by using the older definition and moving the wa bit
definition there. No functional changes.
Fixes: 908ae0517363 ("drm/i915/icl: WaDisCtxReload")
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 4 +---
drivers/gp
On Thu, Nov 08, 2018 at 03:22:27PM -0800, Matt Roper wrote:
> On Thu, Nov 01, 2018 at 05:06:00PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Keep track which planes need updating during the commit. For now this
> > is just (was_visible || is_visible) but I'll have need to update
>
On Fri, Nov 09, 2018 at 03:44:47PM +0200, Imre Deak wrote:
> On Fri, Nov 09, 2018 at 12:09:40AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/2] drm/i915/ddi: Add more sanity check to
> > the encoder HW readout
> > URL : https://patchwork.freedesktop.o
Quoting Mika Kuoppala (2018-11-09 13:56:52)
> This got duplicated on introducing icl workarounds.
> Fix by using the older definition and moving the wa bit
> definition there. No functional changes.
>
> Fixes: 908ae0517363 ("drm/i915/icl: WaDisCtxReload")
But worth backporting for no functional c
Skip the hardware dbuf slice update if we don't have active
pipes. With no active pipes, we don't have powerwell and thus
programming the dbuf slice counts leads to accessing
hardware without runtime pm ref.
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Mika Kuoppala
---
dri
Register DBUF_CTL_S2 is read and it's value is not used. As
there is no explanation why we should prime the hardware with
read, remove it as spurious.
Fixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when needed")
Cc: Mahesh Kumar
Cc: Rodrigo Vivi
Signed-off-by: Mika Kuoppala
---
sna/gen9+: Added AYUV format support for textured and sprite video adapters.
Split out wm_kernel from the sna_composite_op flags
Stanislav Lisovskiy (2):
sna/gen9+: Split out wm_kernel from the sna_composite_op flags
sna: Added AYUV format support for textured and sprite video adapters.
src/
With the extra video kernels we already ran out of bits in
the flags. To tackle that let's just split out the
wm_kernel to its own thing.
Signed-off-by: Stanislav Lisovskiy
---
src/sna/gen9_render.c | 35 ++-
src/sna/sna_render.h | 1 +
2 files changed, 23 inser
v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV.
Added comment about AYUV byte ordering in Gstreamer.
v3: Removed sna_composite_op flags related change to the separate patch.
v4: Fixed review comments, done code refactoring
v5: Fixed following review comments:
- Fixed comment in shade
This got duplicated on introducing icl workarounds.
Fix by using the older definition and moving the wa bit
definition there. No functional changes.
v2: avoid fixes tag, whitespace (Chris)
References: 908ae0517363 ("drm/i915/icl: WaDisCtxReload")
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris W
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Drop spurious register read
from icl_dbuf_slices_update
URL : https://patchwork.freedesktop.org/series/52299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5c3d07354868 drm/i915/icl: Drop spurious register r
Quoting Mika Kuoppala (2018-11-09 14:18:19)
> This got duplicated on introducing icl workarounds.
> Fix by using the older definition and moving the wa bit
> definition there. No functional changes.
>
> v2: avoid fixes tag, whitespace (Chris)
>
> References: 908ae0517363 ("drm/i915/icl: WaDisCtxR
On Thu, Nov 08, 2018 at 03:52:02PM -0800, Matt Roper wrote:
> On Thu, Nov 01, 2018 at 05:06:01PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We're going to need access to the new crtc state in ->disable_plane()
> > for SKL+ wm/ddb programming and pre-skl pipe gamma/csc control. Pa
On Thu, Nov 08, 2018 at 04:01:18PM -0800, Matt Roper wrote:
> On Thu, Nov 01, 2018 at 05:06:02PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > If the level 0 latency is 0 we can't do anything. Return an error
> > rather than success.
> >
> > Signed-off-by: Ville Syrjälä
>
> Is it
Skip the hardware dbuf slice update if we don't have active
pipes. With no active pipes, we don't have powerwell and thus
programming the dbuf slice counts leads to accessing
hardware without runtime pm ref.
v2: bugzilla tag (Imre)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108654
Cc:
On Thu, Nov 08, 2018 at 05:38:37PM -0800, Matt Roper wrote:
> On Wed, Nov 07, 2018 at 08:44:30PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On SKL+ the plane WM/BUF_CFG registers are a proper part of each
> > plane's register set. That means accessing them will cancel any
> > pen
This got duplicated on introducing icl workarounds.
Fix by using the older definition and moving the wa bit
definition there. No functional changes.
v3: avoid fixes tag, whitespace (Chris)
References: 908ae0517363 ("drm/i915/icl: WaDisCtxReload")
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris W
Align icl workarounds whitespace with the rest of the file
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_workarounds.c | 27 ++--
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/driver
Even though PW#1 and the MISC_IO power wells are managed by the
DMC firmware (toggled dynamically if conditions allow it) from the
driver's POV they are always on if the display core is initialized
(always restored by DMC to the enabled state after exiting from DC5/6
for instance b/c of MMIO access
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Drop spurious register read
from icl_dbuf_slices_update
URL : https://patchwork.freedesktop.org/series/52299/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5112 -> Patchwork_10791 =
== Summary - WARNING
We can just use a proper true/false initializer even for bitfields,
which is more descriptive.
Cc: Ramalingam C
Cc: Daniel Vetter
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(
A DMC bug on GEN9 big core machines fails to restore the driver's
request bits for the PW1 and MISC_IO power wells after a DC5/6
entry->exit sequence. As a consequence the driver's subsequent check for
the enabled status of these power wells will fail, as the check
considers the power wells being e
On Fri, Nov 09, 2018 at 04:58:20PM +0200, Imre Deak wrote:
> A DMC bug on GEN9 big core machines fails to restore the driver's
> request bits for the PW1 and MISC_IO power wells after a DC5/6
> entry->exit sequence. As a consequence the driver's subsequent check for
> the enabled status of these po
== Series Details ==
Series: drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IA (rev2)
URL : https://patchwork.freedesktop.org/series/52297/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c48f4f89537d drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IA
Quoting Mika Kuoppala (2018-11-09 14:53:33)
> Align icl workarounds whitespace with the rest of the file
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
That'll do. Fine piece of Wensleydale,
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing
== Series Details ==
Series: series starting with [v3,1/3] drm/i915: Reuse the aux_domain cached
URL : https://patchwork.freedesktop.org/series/52194/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5105_full -> Patchwork_10778_full =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IA (rev2)
URL : https://patchwork.freedesktop.org/series/52297/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5113 -> Patchwork_10792 =
== Summary - SUCCESS ==
No regressions found
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Drop spurious register read
from icl_dbuf_slices_update (rev2)
URL : https://patchwork.freedesktop.org/series/52299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b65f68a1dad drm/i915/icl: Drop spurious reg
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Drop spurious register read
from icl_dbuf_slices_update (rev2)
URL : https://patchwork.freedesktop.org/series/52299/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5113 -> Patchwork_10793 =
== Summary - S
== Series Details ==
Series: series starting with [1/2] drm/i915: Deduplicate register definition
for GAMW_ECO_DEV_RW_IA
URL : https://patchwork.freedesktop.org/series/52301/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4297fd927509 drm/i915: Deduplicate register definition f
On Thu, Nov 08, 2018 at 06:35:10PM -0500, Lyude Paul wrote:
> lgtm
>
> Reviewed-by: Lyude Paul
Thanks. Pushed to dinq.
>
> On Thu, 2018-11-08 at 22:04 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > In my haste to remove irq_port[] I accidentally changed the
> > way we deal with
On Thu, Nov 08, 2018 at 06:36:15PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 08, 2018 at 04:23:48PM +, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-11-08 14:36:35)
> > > From: Ville Syrjälä
> > >
> > > IBX has a documented workaround which states that when we disable the
> > > port we
== Series Details ==
Series: series starting with [1/2] drm/i915: Deduplicate register definition
for GAMW_ECO_DEV_RW_IA
URL : https://patchwork.freedesktop.org/series/52301/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5113 -> Patchwork_10794 =
== Summary - SUCCESS ==
Quoting Stanislav Lisovskiy (2018-11-09 14:14:40)
> diff --git a/src/sna/sna_video_textured.c b/src/sna/sna_video_textured.c
> index a784fe2e..46c213ef 100644
> --- a/src/sna/sna_video_textured.c
> +++ b/src/sna/sna_video_textured.c
> @@ -68,6 +68,7 @@ static const XvImageRec gen4_Images[] = {
>
On Fri, Nov 09, 2018 at 03:29:27PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v3,1/3] drm/i915: Reuse the aux_domain cached
> URL : https://patchwork.freedesktop.org/series/52194/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_5
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Friday, November 9, 2018 6:12 PM
> To: Lisovskiy, Stanislav ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville ; Peres, Martin
> ; Lisovskiy, Stanislav
> ;
> Heikkila, Juha-pekka ;
> maarten.lankho
== Series Details ==
Series: series starting with [1/2] drm/i915/ddi: Add more sanity check to the
encoder HW readout
URL : https://patchwork.freedesktop.org/series/52187/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5100_full -> Patchwork_10758_full =
== Summary - WARNIN
== Series Details ==
Series: series starting with [1/3] drm/i915/gen9_bc: Work around DMC bug
zeroing power well requests
URL : https://patchwork.freedesktop.org/series/52302/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5115 -> Patchwork_10795 =
== Summary - WARNING ==
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result from
Context Status Buffer.
Preemption in previous gens required a special batch buffer to be executed,
so the Command Streamer never preempted to idle dir
On Wed, Nov 07, 2018 at 08:29:53PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 01, 2018 at 11:13:50AM -0700, Rodrigo Vivi wrote:
> > On Thu, Nov 01, 2018 at 05:17:36PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Remove the "sizes are 0 based" stuff that is not even true for th
Pushed with small changes to drm-misc-fixes: Renamed patch and added stable Cc
Thanks!
On Fri, 2018-11-09 at 11:00 +0200, Stanislav Lisovskiy wrote:
> Unfortunately drm_dp_get_mst_branch_device which is called from both
> drm_dp_mst_handle_down_rep and drm_dp_mst_handle_up_rep seem to rely
> on t
== Series Details ==
Series: series starting with [1/3] drm/i915: Handle -EDEADLK from
ironlake_check_fdi_lanes()
URL : https://patchwork.freedesktop.org/series/52191/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5115 -> Patchwork_10796 =
== Summary - SUCCESS ==
No reg
On Fri, Nov 09, 2018 at 05:04:40PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 09, 2018 at 04:58:20PM +0200, Imre Deak wrote:
> > A DMC bug on GEN9 big core machines fails to restore the driver's
> > request bits for the PW1 and MISC_IO power wells after a DC5/6
> > entry->exit sequence. As a consequ
I think we have some interest in reviving this for the performance query
use case.
Is that on anybody's todo list?
Thanks,
-
Lionel
On 14/03/2018 09:37, Chris Wilson wrote:
Often, we find ourselves facing a workload where the user knows in
advance what GPU frequency they require for it to com
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/in
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.
Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that s
With the address range being specified for each platform, we can use
that instead of the .ppgtt enum to handle the differences between
3 level and 4 level PPGTT. In most cases, we really only care if the
platform supports PPGTT or not. Because of this, we can now remove
the HAS_FULL_PPGTT macro and
== Series Details ==
Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev8)
URL : https://patchwork.freedesktop.org/series/40747/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
565cd7090a44 drm/i915/icl: Preempt-to-idle support in execlists.
-:18: WARNING:COMMIT_LO
== Series Details ==
Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev8)
URL : https://patchwork.freedesktop.org/series/40747/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Preempt-to-idle support in execlists.
-drivers/
== Series Details ==
Series: drm/i915/gen11: Preempt-to-idle support in execlists. (rev8)
URL : https://patchwork.freedesktop.org/series/40747/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5116 -> Patchwork_10797 =
== Summary - SUCCESS ==
No regressions found.
Extern
== Series Details ==
Series: series starting with [1/3,CI] drm/i915: Make 48bit full ppgtt
configuration generic (v10)
URL : https://patchwork.freedesktop.org/series/52309/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Make 48bit full ppgtt
Thanks for the reviews DK, patches pushed to drm-intel-next-queued
On Fri, 2018-11-09 at 06:36 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v4,1/4] drm/i915/psr: Use
> intel_psr_exit() in intel_psr_disable_source()
> URL : https://patchwork.freedesktop.org/se
== Series Details ==
Series: series starting with [1/3,CI] drm/i915: Make 48bit full ppgtt
configuration generic (v10)
URL : https://patchwork.freedesktop.org/series/52309/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5116 -> Patchwork_10798 =
== Summary - WARNING ==
M
== Series Details ==
Series: drm/i915: Move skip_intermediate_wm handling into
ilk_compute_intermediate_wm()
URL : https://patchwork.freedesktop.org/series/52248/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5116 -> Patchwork_10799 =
== Summary - WARNING ==
Minor unkno
While PSR is active hardware will do aux transactions by it self to
wakeup sink to receive a new frame when necessary. If that
transaction is not acked by sink, hardware will trigger this
interruption.
So let's disable PSR as it is a hint that there is problem with this
sink.
The removed FIXME wa
If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
will still keep the error set even after the reset done in the
irq_preinstall and irq_uninstall hooks.
And enabling in this situation cause the screen to freeze in the
first time that PSR HW tries to activate so lets keep PSR disab
When we detect a error and disable PSR, it is kept disable until the
next modeset but as the sink already show signs that it do not
properly work with PSR lets disabled it for good to avoid any
additional flickering.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/d
When a PSR error happens sink sets the PSR errors register and also
set the link to a error status.
So in the short pulse handling it was returning earlier and doing a
full detection and attempting to retrain but it fails as PSR HW is
in change of the main-link.
Just call intel_psr_short_pulse() b
Some eDP panels do not set a valid sink count value and even for the
ones that sets is should always be one for eDP, that is why it is not
cached in intel_edp_init_dpcd().
But intel_dp_short_pulse() compares the old count with the read one
if there is a mistmatch a full port detection will be exec
We should not access hardware while computing config also we don't
support stereo 3D so this tests was never true.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/d
If panel supports DRRS and PSR and if driver is loaded without PSR
enabled, driver will enable DRRS as expected but if PSR is enabled by
debugfs latter it will keep PSR and DRRS enabled causing possible
problems as DRRS will lower the refresh rate while PSR enabled.
Bugzilla: https://bugs.freedesk
== Series Details ==
Series: series starting with [1/7] drm/i915: Avoid a full port detection in the
first eDP short pulse
URL : https://patchwork.freedesktop.org/series/52313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eb5d436583c5 drm/i915: Avoid a full port detection in
== Series Details ==
Series: series starting with [1/7] drm/i915: Avoid a full port detection in the
first eDP short pulse
URL : https://patchwork.freedesktop.org/series/52313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Avoid a full port
== Series Details ==
Series: drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IA (rev2)
URL : https://patchwork.freedesktop.org/series/52297/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5113_full -> Patchwork_10792_full =
== Summary - WARNING ==
Minor unkn
== Series Details ==
Series: series starting with [1/7] drm/i915: Avoid a full port detection in the
first eDP short pulse
URL : https://patchwork.freedesktop.org/series/52313/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5117 -> Patchwork_10800 =
== Summary - FAILURE ==
On 06/11/2018 10:33, Lionel Landwerlin wrote:
On 06/11/2018 18:29, Daniele Ceraolo Spurio wrote:
We have a subslice mask per slice, not per subslice.
MAX_SUBSLICES > MAX_SLICES, so the wrong size didn't cause any issue
apart from using extra memory.
Cc: Lionel Landwerlin
Signed-off-by: Danie
On 09/11/2018 03:15, Patchwork wrote:
== Series Details ==
Series: drm/i915/query: fix subslice length
URL : https://patchwork.freedesktop.org/series/52270/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5108_full -> Patchwork_10784_full =
== Summary - WARNING ==
Min
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Drop spurious register read
from icl_dbuf_slices_update (rev2)
URL : https://patchwork.freedesktop.org/series/52299/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5113_full -> Patchwork_10793_full =
== S
== Series Details ==
Series: series starting with [1/2] drm/i915: Deduplicate register definition
for GAMW_ECO_DEV_RW_IA
URL : https://patchwork.freedesktop.org/series/52301/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5113_full -> Patchwork_10794_full =
== Summary - WAR
1 - 100 of 108 matches
Mail list logo
