On Tue, 30 Oct 2018, Lucas De Marchi wrote:
> On Tue, Oct 30, 2018 at 11:52:30AM +0200, Jani Nikula wrote:
>> On Mon, 29 Oct 2018, Rodrigo Vivi wrote:
>> > +#define IS_DISPLAY_GEN2(dev_priv) (!!((dev_priv)->info.display_gen_mask \
>> > + & BIT(2)))
>> > +#defi
The i915 driver uses shmemfs to allocate backing storage for gem
objects. These shmemfs pages can be pinned (increased ref count) by
shmem_read_mapping_page_gfp(). When a lot of pages are pinned, vmscan
wastes a lot of time scanning these pinned pages. In some extreme case,
all pages in the inactiv
Quoting Zhenyu Wang (2018-10-31 05:17:48)
> On 2018.10.30 15:08:01 +0800, intel-gfx-boun...@lists.freedesktop.org wrote:
> > From: Hang Yuan
> >
> > This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd.
> >
> > Checked GVT codes that guest PPGTT PTE flag bits are propagated
> > to shadow
On 31/10/2018 08:13, Jani Nikula wrote:
On Tue, 30 Oct 2018, Lucas De Marchi wrote:
On Tue, Oct 30, 2018 at 11:52:30AM +0200, Jani Nikula wrote:
On Mon, 29 Oct 2018, Rodrigo Vivi wrote:
+#define IS_DISPLAY_GEN2(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+
Quoting Patchwork (2018-10-29 23:07:25)
> == Series Details ==
>
> Series: drm/i915/selftest: test aligned offsets for 64K
> URL : https://patchwork.freedesktop.org/series/51707/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10636 =
>
> == Summar
On Wed, 31 Oct 2018, Tvrtko Ursulin wrote:
> I saw some mention somewhere on IS_GEN_RANGE, which looked clearer than
> IS_GEN(dev_priv, s, e). Presumably that did not go anywhere since now
> the proposal is the above? I have to say I am not sure it reads
> completely intuitive when seen near in
We observe that the ordering of writes for a CS event is not as strong
from the GPU as we would like, and that on occasions we see the
ringbuffer tail updated before the event is written into the ringbuffer,
leading us to reuse the stale data.
Through around a big hammer to try and batter ELSQ int
Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.
As this involved adding a potentially sleeping
In preparation for the next few commits, make resetting the GPU atomic.
Currently, we have prepared gen6+ for atomic resetting of individual
engines, but now there is a requirement to perform the whole device
level reset (just the register poking) from inside an atomic context.
Signed-off-by: Chri
We observe that the ordering of writes for a CS event is not as strong
from the GPU as we would like, and that on occasions we see the
ringbuffer tail updated before the event is written into the ringbuffer,
leading us to reuse the stale data.
Through around a big hammer to try and batter ELSQ int
Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
notifiers") we have been able to report failure from
mmu_invalidate_range_start which allows us to use a trylock on the
struct_mutex to avoid potential recursion and report -EBUSY instead.
Furthermore, this allows us to pull th
Track where and when we acquire and release the power well for pps
access along the dp aux link, with a view to detecting if we leak any
wakerefs.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_dp.c | 226 +---
1 file changed, 118 insertions(+), 108 deleti
The majority of runtime-pm operations are bounded and scoped within a
function; these are easy to verify that the wakeref are handled
correctly. We can employ the compiler to help us, and reduce the number
of wakerefs tracked when debugging, by passing around cookies provided
by the various rpm_get
Include the total size of closed vma when reporting the per_ctx_stats of
debugfs/i915_gem_objects.
Whilst adjusting the context tracking, note that we can simply use our
list of contexts in i915->contexts rather than circumlocute via
dev->filelist and the per-file context idr, with the result that
When we first introduced the reset to sanitize the GPU on taking over
from the BIOS and before returning control to third parties (the BIOS!),
we restricted it to only systems utilizing HW contexts as we were
uncertain of how stable our reset mechanism truly was. We now have
reasonable coverage acr
Frequently, we use intel_runtime_pm_get/_put around a small block.
Formalise that usage by providing a macro to define such a block with an
automatic closure to scope the intel_runtime_pm wakeref to that block,
i.e. macro abuse smelling of python.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/
Since capturing the error state requires fiddling around with the GGTT
to read arbitrary buffers and is itself run under stop_machine(), it
deadlocks the machine (effectively a hard hang) when run in conjunction
with Broxton's VTd workaround to serialize GGTT access.
v2: Store the ERR_PTR in first
Currently the code to reset the GPU and our state is spread widely
across a few files. Pull the logic together into a common file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile |3 +-
drivers/gpu/drm/i915/i915_debugfs.c |2 +
drivers/gpu/drm/i915
We have two classes of VM, global GTT and per-process GTT. In order to
allow ourselves the freedom to mix both along call chains, distinguish
the two classes with regards to their mutex and lockdep maps.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +-
d
As we only release each power well once, we assume that each transcoder
maps to a different domain. Complain if this is not so.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/d
The majority of runtime-pm operations are bounded and scoped within a
function; these are easy to verify that the wakeref are handled
correctly. We can employ the compiler to help us, and reduce the number
of wakerefs tracked when debugging, by passing around cookies provided
by the various rpm_get
Make i915_gem_set_wedged() and i915_gem_unset_wedged() behaviour more
consistently if called concurrently.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem.c | 32 ++-
drivers/gpu/drm/i915/i915_gpu_error.h | 4 ++-
.../gpu/dr
As the GT_IRQ power domain implies a wakeref, we can use it inplace of
our existing redundant rpm grab.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem.c | 11 ---
drivers/gpu/drm/i915/selftests/mock_
The information presented here is not relevant to current development.
We can either use the context information, but more often we want to
inspect the active gpu state.
The ulterior motive is to eradicate dev->filelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 119
On module load and unload, we grab the POWER_DOMAIN_INIT powerwells and
transfer them to the runtime-pm code. We can use our wakeref tracking to
verify that the wakeref is indeed passed from init to enable, and
disable to fini; and across suspend.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/
Everytime we take a wakeref, record the stack trace of where it was
taken; clearing the set if we ever drop back to no owners. For debugging
a rpm leak, we can look at all the current wakerefs and check if they
have a matching rpm_put.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig
Currently, we convert the error state into a string every time we read
from sysfs (and sysfs reads in page size (4KiB) chunks). We do try to
window the string and only capture the portion that is being read, but
that means that we must always convert up to the window to find the
start. For a very l
Ping review, thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; H
Ping review. Thanks very much.
BRs
Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He,
Ping review. Thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; H
Ping review. Thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51785/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dsc: Add slice_row_pe
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Move DSI connector functions to intel_dsi.c and make them available to
both legacy and ICL DSI.
v2 by Jani:
- Move the functions to intel_dsi.c
- Don't reuse intel_dsi_connector_destroy()
Patch 1 & 2 v2 changes, i.e. code mov
Ping review, thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He,
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
v3 by Jani:
- Add FIXME note.
Looks OK to me.
Regards,
Madha
On Tue, 30 Oct 2018, Lucas De Marchi wrote:
> On Tue, Oct 30, 2018 at 6:56 AM Jani Nikula
> wrote:
>>
>> On Mon, 29 Oct 2018, Anusha Srivatsa wrote:
>> > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
>> > from the base - which is the FLexi IO Adaptor. Lets follow the
>> > offs
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51785/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5059 -> Patchwork_10656 =
== Summary - SUCCESS ==
On Wed, 31 Oct 2018, Madhav Chauhan wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan
>>
>> This patch programs maximum size of the payload transmitted
>> from peripheral back to the host processor using short packet
>> as a part of panel programming.
>>
>> v2: Rebase
>>
On Tue, 30 Oct 2018, Jani Nikula wrote:
> From: Madhav Chauhan
>
> This patch execute poweron, deassert reset, display on
> VBT sequences and send TURN_ON DSI command to panel for
> powering it up.
>
> Signed-off-by: Madhav Chauhan
> Reviewed-by: Jani Nikula
> Signed-off-by: Jani Nikula
Pushe
Quoting Kuo-Hsin Yang (2018-10-31 08:19:45)
> The i915 driver uses shmemfs to allocate backing storage for gem
> objects. These shmemfs pages can be pinned (increased ref count) by
> shmem_read_mapping_page_gfp(). When a lot of pages are pinned, vmscan
> wastes a lot of time scanning these pinned p
On Tue, 16 Oct 2018, Greg Kroah-Hartman wrote:
> On Tue, Oct 16, 2018 at 03:10:24PM +0300, Jani Nikula wrote:
>> On Tue, 16 Oct 2018, Greg Kroah-Hartman wrote:
>> > On Tue, Oct 16, 2018 at 02:38:53PM +0300, Jani Nikula wrote:
>> >> On Tue, 16 Oct 2018, Greg Kroah-Hartman
>> >> wrote:
>> >> > On
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.
As per
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch disables transcoders by writing to TRANS_CONF
registers for each DSI ports.
v2 by Jani:
- Wait for pipeconf active to go low
Thanks for catching this, it has to be low.
Regards,
Madhav
Signed-off-by: Madhav Chauha
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
and DSI_TA_TO registers for DSI transcoders '0' and '1'.
They are used for contention recovery on DPHY.
v2: Define SHIFT for bitfields.
v3 by Jani:
- Fix timeout bit defini
On Wed, Oct 31, 2018 at 5:42 PM Chris Wilson wrote:
> Will do. As you are confident, I'll try a few different machines. :)
> -Chris
Great! Thanks for your help. :)
Vovo
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop
== Series Details ==
Series: Forward Error Correction (rev4)
URL : https://patchwork.freedesktop.org/series/47848/
State : failure
== Summary ==
Applying: i915/dp/fec: Cache the FEC_CAPABLE DPCD register
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_dp.c).
error: co
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
Program the timeout values (in escape clock) for HS TX, LP RX and TA
timeout.
HX TX: Ensure that host does not continuously transmit in the HS
state. If this timer expires, then host will gracefully end its HS
transmission and allo
The device info offset arrays for unevenly spaced register offsets is
great for widely used registers. However, the palette registers are only
used in one function, i9xx_load_luts_internal(), and only for GMCH
platforms, wasting device info. Replace palette_offsets with _PICK() in
palette register
Try to make it slightly less of an eye sore. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg
Minor semantic nit, no functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d97cf98e3edf..0d0145967482 100644
--- a/drivers/gp
Keep the register choosing macros together. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
ind
== Series Details ==
Series: mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev2)
URL : https://patchwork.freedesktop.org/series/25337/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c5bc6a6a53e8 mm, drm/i915: mark pinned shmemfs pages as unevictable
-:126: CHECK:AVOID_
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51785/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5059_full -> Patchwork_10656_full =
== Summary - SUCC
On Wed, 31 Oct 2018, Madhav Chauhan wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan
>>
>> Program the timeout values (in escape clock) for HS TX, LP RX and TA
>> timeout.
>>
>> HX TX: Ensure that host does not continuously transmit in the HS
>> state. If this timer expi
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch detects DSI presence for ICL platform
by reading VBT. DSI detection is done while initializing
DSI using newly added function intel_gen11_dsi_init.
v2 by Jani:
- Preserve old behavour of intel_bios_is_dsi_present()
-
== Series Details ==
Series: mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev2)
URL : https://patchwork.freedesktop.org/series/25337/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5061 -> Patchwork_10658 =
== Summary - WARNING ==
Minor unknown changes coming w
On 10/30/2018 5:26 PM, Jani Nikula wrote:
This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired mode info to connector
On 10/30/2018 5:26 PM, Jani Nikula wrote:
This patch allocates DSI host structure for each
DSI port available on gen11 and register them with
DSI fwk of DRM. Some of the DSI host operations are
also registered as part of this. This patch also fills
MIPI config block info from VBT to local structu
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.
v2 by Jani:
- Drop full register mask and shift for payload
- Use lower case for hex 0x
v2 change are fine.
Regards,
Madh
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch retrieves DSI pkt (from DSI msg) to be
sent over DSI link using DRM DSI exported functions.
A wrapper function is also added as "DSI host transfer"
for sending DSI data/cmd.
v2 by Jani:
- Use the new credit available
This patch adds a colorspace property enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the colorspace enum to incorporate both HDMI and DP supported
colorspaces. Als
This patch attaches the colorspace connector property to the
hdmi connector. Based on colorspace change, modeset will be
triggered to switch to new colorspace.
Based on colorspace property value create an infoframe
with appropriate colorspace. This can be used to send an
infoframe packet with prop
This patch series creates a new connector property to program
colorspace to sink devices. Modern sink devices support more
than 1 type of colorspace like 601, 709, BT2020 etc. This helps
to switch based on content type which is to be displayed. The
decision lies with compositors as to in which scen
On 10/30/2018 5:26 PM, Jani Nikula wrote:
This patch adds DSI packet payload to command payload
queue using credit based mechanism for *long* packets.
v2 by Jani:
- Add intel_dsi local variable for better code flow
- Use the new credit available helper
- Use int for free_credits, i, and j
On 10/30/2018 5:26 PM, Jani Nikula wrote:
From: Madhav Chauhan
This patch read out the current hw state for DSI and
return true if encoder is active.
v2 by Jani:
- Squash connector get hw state hook here
- Squash encode get hw state fix here
Looks fine to me.
Regards,
Madhav
Signed-o
drivers/gpu/drm/drm_syncobj.c:181:6: warning: no previous prototype for
‘drm_syncobj_add_callback’ [-Wmissing-prototypes]
drivers/gpu/drm/drm_syncobj.c:190:6: warning: no previous prototype for
‘drm_syncobj_remove_callback’ [-Wmissing-prototypes]
Fixing that leads to
drivers/gpu/drm/drm_syncobj
== Series Details ==
Series: series starting with [01/20] RFT drm/i915/execlists: Flush memory
before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51797/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
== Series Details ==
Series: i915 pvmmio to improve GVTg performance (rev6)
URL : https://patchwork.freedesktop.org/series/51235/
State : failure
== Summary ==
Applying: drm/i915: introduced pv capability for vgpu
error: patch fragment without header at line 38: @@ -3878,4 +3885,8 @@ static
i
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10659 =
== Summary - WARNING ==
Minor unknown changes coming with
>-Original Message-
>From: Roper, Matthew D
>Sent: Tuesday, October 30, 2018 4:59 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst, Maarten
>Subject: Re: [Intel-gfx] [v5 2/2] drm/i915/icl: Enable Plane Input CSC for YUV
>to
>RGB Conversion
>
>On Fr
== Series Details ==
Series: Add Colorspace connector property interface (rev2)
URL : https://patchwork.freedesktop.org/series/47132/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b716d24947ce drm: Add colorspace property
33d07ea8810b drm/i915: Attach colorspace property and en
== Series Details ==
Series: Add Colorspace connector property interface (rev2)
URL : https://patchwork.freedesktop.org/series/47132/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm: Add colorspace property
Okay!
Commit: drm/i915: Attach colorspace
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Tuesday, October 30, 2018 4:25 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [v5 2/2] drm/i915/icl: Enable Plane Inp
== Series Details ==
Series: series starting with [1/4] drm/i915: remove palette_offsets from device
info in favor of _PICK()
URL : https://patchwork.freedesktop.org/series/51802/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10662 =
== Summary - SUCCESS
== Series Details ==
Series: Add Colorspace connector property interface (rev2)
URL : https://patchwork.freedesktop.org/series/47132/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10663 =
== Summary - FAILURE ==
Serious unknown changes coming with Patch
On Wed, Oct 31, 2018 at 01:04:50PM +0200, Jani Nikula wrote:
> The device info offset arrays for unevenly spaced register offsets is
> great for widely used registers. However, the palette registers are only
> used in one function, i9xx_load_luts_internal(), and only for GMCH
> platforms, wasting d
On Wed, Oct 31, 2018 at 01:04:51PM +0200, Jani Nikula wrote:
> Minor semantic nit, no functional changes.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm
On Wed, Oct 31, 2018 at 01:04:52PM +0200, Jani Nikula wrote:
> Try to make it slightly less of an eye sore. No functional changes.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 31 +--
> 1 file changed, 17 insertions(+), 14 deletions(-)
>
>
On Wed, Oct 31, 2018 at 01:04:53PM +0200, Jani Nikula wrote:
> Keep the register choosing macros together. No functional changes.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 26 ++
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff
== Series Details ==
Series: drm/syncobj: Mark local add/remove callback functions as static
URL : https://patchwork.freedesktop.org/series/51809/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/syncobj: Mark local add/remove callback functions as s
On Tue, Oct 30, 2018 at 03:15:55PM -0700, Rodrigo Vivi wrote:
> Let's introduce the WA number that is the
> cause of having NV12 disabled on both SLK and BXT.
>
> According to Spec:
>
> WA 0870: "Display flickers with NV12 video playback in
> Y tiling mode.
> WA: Use YUV422 surface format instead
On Tue, Oct 30, 2018 at 04:45:35PM -0700, Manasi Navare wrote:
> On Thu, Oct 25, 2018 at 05:09:42PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:34PM -0700, Manasi Navare wrote:
> > > DSC PPS secondary data packet infoframes are filled with
> > > DSC picure parameter set metadata a
On Tue, Oct 30, 2018 at 04:53:49PM -0700, Manasi Navare wrote:
> On Wed, Oct 24, 2018 at 03:28:24PM -0700, Manasi Navare wrote:
> > Basic DSC parameters and DSC configuration data needs to be computed
> > for each of the requested mode during atomic check. This is
> > required since for certain mod
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro definitio
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It
This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.
This series enables color conversion for Full Range YUV data,
limited range handling will be done
== Series Details ==
Series: drm/syncobj: Mark local add/remove callback functions as static
URL : https://patchwork.freedesktop.org/series/51809/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10664 =
== Summary - WARNING ==
Minor unknown changes coming
On Tue, Oct 30, 2018 at 02:57:51PM -0700, Lucas De Marchi wrote:
> On Tue, Oct 30, 2018 at 05:40:50PM +0200, Imre Deak wrote:
> > Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
> > parameters. As opposed to this the flag specifying the thunderbolt vs.
> > non-thunderbolt mode of th
On Wed, Oct 31, 2018 at 01:28:07AM +0200, Souza, Jose wrote:
> On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
> > parameters. As opposed to this the flag specifying the thunderbolt
> > vs.
> > non-thunderbolt mode of the port
On Wed, Oct 31, 2018 at 12:36:00AM +0200, Souza, Jose wrote:
> On Tue, 2018-10-30 at 17:40 +0200, Imre Deak wrote:
> > From ICL onwards all DDI/TypeC ports - even working in HDMI mode -
> > need
> > to know their corresponding AUX CH, so move the field to a common
> > struct.
> >
> > No functional
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev5)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0788076afc3f drm/i915/icl: Define Plane Input CSC Coefficient Registers
-:58: CHECK:MACRO_ARG_REUSE: Macro argu
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev5)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers
Okay!
Commit: drm/i915/i
On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10665 =
== Summary - SUCCESS ==
No regressions found.
External
On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev5)
URL : https://patchwork.freedesktop.org/series/51463/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10666 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchw
On 10/31/18 1:19 AM, owner-linux...@kvack.org wrote:
> -These are currently used in two places in the kernel:
> +These are currently used in three places in the kernel:
>
> (1) By ramfs to mark the address spaces of its inodes when they are created,
> and this mark remains for the life of
From: Oscar Mateo
SFC (Scaler & Format Converter) units are shared between VD and VEBoxes.
They also happen to have separate reset bits. So, whenever we want to reset
one or more of the media engines, we have to make sure the SFCs do not
change owner in the process and, if this owner happens to b
From: Oscar Mateo
In Gen11, only even numbered "logical" VDBoxes are hooked up to an SFC
(Scaler & Format Converter) unit. We will use this information to decide
when the SFC units need to be reset.
BSpec: 20189
Signed-off-by: Tomasz Lis
Signed-off-by: Oscar Mateo
Signed-off-by: Michel Thierr
On Wed 31-10-18 16:19:45, Kuo-Hsin Yang wrote:
[...]
> The previous mapping_set_unevictable patch is worse on gem_syslatency
> because it defers to vmscan to move these pages to the unevictable list
> and the test measures latency to allocate 2MiB pages. This performance
> impact can be solved by e
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