== Series Details ==
Series: drm/i915: Add ppgtt to GVT GEM context
URL : https://patchwork.freedesktop.org/series/51156/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5000_full -> Patchwork_10500_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues
On Thu 18-10-18 07:56:45, Chris Wilson wrote:
> Quoting Chris Wilson (2018-10-16 19:31:06)
> > Fwiw, the shmem_unlock_mapping() call feels quite expensive, almost
> > nullifying the advantage gained from not walking the lists in reclaim.
> > I'll have better numbers in a couple of days.
>
> Using
On Fri, Mar 16, 2018 at 12:26 AM Byungchul Park wrote:
>
> On 3/15/2018 9:41 PM, Peter Zijlstra wrote:
> > On Thu, Mar 15, 2018 at 11:31:57AM +0100, Daniel Vetter wrote:
> >> Is there any progress on getting cross-release enabled again?
> >
> > Not yet, I'm still fighting the meltdown/spectre indu
Quoting Michal Wajdeczko (2018-10-18 00:22:43)
> On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
> wrote:
>
> >
> >
> > On 17/10/18 13:29, Chris Wilson wrote:
> >> Propagate the timeout on transferring the fw back to the caller where it
> >> may act upon it, usually by restarting the
On 12/10/2018 08:16, Patchwork wrote:
== Series Details ==
Series: drm/i915: GEM_WARN_ON considered harmful (rev2)
URL : https://patchwork.freedesktop.org/series/49340/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4976 -> Patchwork_10434 =
== Summary - SUCCESS ==
No
Use single exit point to drop rpm wakeref in case of an error.
Fixes: 9d3eb2c33f03 ("drm/i915: Hold rpm wakeref for
debugfs/i915_drop_caches_set")
Signed-off-by: Joonas Lahtinen
Cc: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2 insertions(+)
Quoting Joonas Lahtinen (2018-10-18 10:20:25)
> Use single exit point to drop rpm wakeref in case of an error.
>
> Fixes: 9d3eb2c33f03 ("drm/i915: Hold rpm wakeref for
> debugfs/i915_drop_caches_set")
> Signed-off-by: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Ville Syrjälä
Mea culpa,
Reviewed-
Quoting Michal Wajdeczko (2018-10-17 20:52:45)
> In response for I915_PARAM_HAS_HUC we are returning value that
> indicates if HuC firmware was loaded and verified. However, our
> previously used positive value was based on specific register bit
> which is about to change on future platform. Let's
This patch seems to have fallen through the cracks..
On 19/03/2018 15:26, Sagar Arun Kamble wrote:
On 3/16/2018 5:44 PM, Mika Kuoppala wrote:
From: Oscar Mateo
In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
Video Enhancement engines (aka VEBOX, aka VECS) could be
On Fri, Oct 12, 2018 at 11:45 PM Jeff McGee wrote:
>
> On Fri, Oct 12, 2018 at 02:33:26PM -0700, Jeff McGee wrote:
> > On Fri, Oct 12, 2018 at 01:51:46PM -0700, Rodrigo Vivi wrote:
> > > On Fri, Oct 12, 2018 at 01:24:30PM -0700, Jeff McGee wrote:
> > > > The GuC firmware team is proposing a change
== Series Details ==
Series: drm/i915: Drop rpm wakeref on error in debugfs/i915_drop_caches_set
URL : https://patchwork.freedesktop.org/series/51169/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5005 -> Patchwork_10501 =
== Summary - SUCCESS ==
No regressions found.
On Wed, Oct 17, 2018 at 04:10:34PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> HDMI 2.0 monitors may not support SCDC and still be able to accept VICs
> above 63. Use multiple EDID capbilities to determine if the SINK is
> actually an HDMI 2.0 device. The QD980B HDMI 2.0 Ana
From: Tvrtko Ursulin
Upcoming GuC code will need to read the fused off engine masks as well,
and will also want to have them as enabled instead of disabled masks.
To consolidate the read-out place we can store them in this fashion inside
INTEL_INFO so they can be easily referenced in the future.
== Series Details ==
Series: drm/i915/icl: Store available engine masks in INTEL_INFO
URL : https://patchwork.freedesktop.org/series/51175/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5005 -> Patchwork_10502 =
== Summary - SUCCESS ==
No regressions found.
External U
New version, with a lot of reworking to incorporate all the feedback.
We currently don't set the plane input CSC correctly, so colors are a
bit off. As a result I can't verify for 100% we program the chroma
upsampler correctly, but I still want to put out this series for review.
Maarten Lankhorst
The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
upsampler to upscale YUV420 to YUV444 and the scaler should only be
used for upscaling. Because of this we shouldn't program the scalers
in planar mode if NV12 and the chroma upsampler are used. Instead
program the scalers like on
To make NV12 working on icl, we need to update 2 planes simultaneously.
I've chosen to do this in the CRTC step after plane validation is done,
so we know what planes are (in)visible. The linked Y plane will get
updated in intel_plane_update_planes_on_crtc(), by the call to
update_slave, which gets
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5997097177e9..8299eb9193b4 100644
--- a/drivers/gpu/drm/i915/intel_displ
The UV plane is the master plane that does all color correction etc.
It needs to be programmed with the dimensions for color plane 1 (UV).
The Y plane just feeds the Y pixels to it. Program the scaler from the
master only, and set PLANE_CTL_YUV420_Y_PLANE on the slave plane.
Changes since v1:
- M
Skylake style watermarks program the UV parameters into wm->uv_wm,
and have a separate DDB allocation for UV blocks into the same plane.
Gen11 watermarks have a separate plane for Y and UV, with separate
mechanisms. The simplest way to make it work is to keep the current
way of programming waterma
On gen11, we can definitely smash the 32-bits barrier with just a
when we enable all planes in the next patch.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 47 +++--
1 file changed, 22 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/
Gen11 supports 7 planes + 1 cursor on each pipe. Bump
I915_MAX_PLANES to 8, and set num_sprites correctly.
Signed-off-by: Maarten Lankhorst
[mlankhorst: Move the skl/bxt comment to the BXT branch. (Matt)]
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/intel_device_info.c | 22 +---
We configure the chroma upsampler with the same chroma siting as
used by the scaler for consistency, the chroma upsampler is used
instead of the scaler for YUV 4:2:0 on ICL's HDR planes.
Signed-off-by: Maarten Lankhorst
---
Can't test this completely until we have correct colors by programming
th
== Series Details ==
Series: drm/i915/gen11: Add support for the NV12 format.
URL : https://patchwork.freedesktop.org/series/51178/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0cce6a850fe7 drm/i915: Fix unsigned overflow when calculating total data rate
-:36: CHECK:CAMELCASE:
== Series Details ==
Series: drm/i915/gen11: Add support for the NV12 format.
URL : https://patchwork.freedesktop.org/series/51178/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Fix unsigned overflow when calculating total data rate
Okay!
C
On Wed, 17 Oct 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-10-17 10:35:39)
>> Pass the type we want to simplify. No functional changes.
>>
>> v2: s/dev_priv/i915/g (Chris)
>>
>> Cc: Chris Wilson
>> Signed-off-by: Jani Nikula
> Reviewed-by: Chris Wilson
Thanks, pushed.
BR,
Jani.
-
== Series Details ==
Series: drm/i915/gen11: Add support for the NV12 format.
URL : https://patchwork.freedesktop.org/series/51178/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5005 -> Patchwork_10503 =
== Summary - SUCCESS ==
No regressions found.
External URL:
htt
On Tue, 16 Oct 2018, Madhav Chauhan wrote:
> On 10/15/2018 7:57 PM, Jani Nikula wrote:
>> intel_dsi_vbt_init() has grown too unwieldy, and it's about to be
>> modified due to ICL DSI. Abstract out the VLV specific dphy param
>> init. No functional changes. Intentionally no stylistic changes during
On Thu, 18 Oct 2018 02:46:05 +0200, Daniele Ceraolo Spurio
wrote:
The test requires driver tweaks to avoid causing error messages
on intentionally-triggered errors and to stop accessing non
existing register. However, this is a pure GuC FW interface test
and should be covered by FW validation
Quoting Michal Wajdeczko (2018-10-18 13:21:33)
> On Thu, 18 Oct 2018 02:46:05 +0200, Daniele Ceraolo Spurio
> wrote:
>
> > The test requires driver tweaks to avoid causing error messages
> > on intentionally-triggered errors and to stop accessing non
> > existing register. However, this is a pu
On Thu, 18 Oct 2018 02:46:08 +0200, Daniele Ceraolo Spurio
wrote:
A collection of very small cleanups/improvements around doorbell checking
that do not deserve their own patch:
- Move doorbell-related HW defs to intel_guc_reg.h
- use GUC_NUM_DOORBELLS instead of GUC_DOORBELL_INVALID where
On Thu, 18 Oct 2018 02:46:09 +0200, Daniele Ceraolo Spurio
wrote:
We stopped supporting fallback to execlists in commit 121981fafe69
(drm/i915/guc: Combine enable_guc_loading|submission modparams). We
do instead reset and retry in some cases, depending on the workarounds
required by the platf
On Tue, Oct 16, 2018 at 04:09:19PM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 16, 2018 at 04:00:26PM -0700, Paulo Zanoni wrote:
> > Em Sex, 2018-10-12 às 15:42 +0300, Ville Syrjälä escreveu:
> > > On Thu, Oct 11, 2018 at 05:40:45PM -0700, Paulo Zanoni wrote:
> > > > These are the new recommended valu
On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote:
> BSpec does not show these WAs as applicable to GLK, and for CNL it
> only shows them applicable for a super early pre-production stepping
> we shouldn't be caring about anymore. Remove these so we can avoid
> them on ICL too.
>
> Cc:
On Tue, Oct 16, 2018 at 03:01:25PM -0700, Paulo Zanoni wrote:
> Before the patch, if a plane was not visible,
> skl_compute_plane_wm_params() would return early without writing
> anything to the wm_params struct. This would leave garbage in the
> struct since it is not previously zeroed, and then w
On Tue, Oct 16, 2018 at 03:01:26PM -0700, Paulo Zanoni wrote:
> The skl_compute_plane_wm_params() already completely sets the contents
> of its struct, or returns plane_visible=0 or returns an error code.
> There's no need to memset() it at this point for the same reason we
> don't zero-initialize
On Tue, Oct 16, 2018 at 03:01:27PM -0700, Paulo Zanoni wrote:
> We're currently doing it in two different ways, none of them based on
> the wm_params struct. Both places are correct, so I chose to keep the
> one in skl_compute_wm_levels() since it's the function that sets the
> other values for the
On Tue, Oct 16, 2018 at 03:01:28PM -0700, Paulo Zanoni wrote:
> Its control flow is not as easy to follow as it could be. We recently
> even had a double register write that went unnoticed until commit
> 9e44b180f81b ("drm/i915: don't write PLANE_BUF_CFG twice every time")
> fixed it. The return st
On Tue, Oct 16, 2018 at 03:01:29PM -0700, Paulo Zanoni wrote:
> The goal of struct skl_wm_params is to cache every watermark
> parameter so the other functions can just use them without worrying
> about the appropriate place to fetch each parameter requested by the
> spec, and without having to rec
On Tue, Oct 16, 2018 at 03:01:30PM -0700, Paulo Zanoni wrote:
> Print a more generic "failed to compute watermark levels" whenever any
> of skl_compute_wm_levels() fail, and print only the specific error
> message for the specific cases. This allows us to stop passing pstate
> everywhere, making th
On Tue, Oct 16, 2018 at 03:01:31PM -0700, Paulo Zanoni wrote:
> The function only really needs dev_priv to make its decision. If we
> ever need more, we can change it again. But then, in this case we
> should make needs_memory_bw_wa be a variable inside struct
> skl_wm_params so we won't need to ke
On Tue, Oct 16, 2018 at 03:01:32PM -0700, Paulo Zanoni wrote:
> With this one here we can finally drop the intel state structures from
> the functions that compute watermark values: they all rely on struct
> skl_wm_params now. This should help the watermarks code be a little
> more clear on its int
On Tue, Oct 16, 2018 at 03:01:33PM -0700, Paulo Zanoni wrote:
> Stop passing modeset state structures to functions that should work
> only with the skl_wm_params. The only use for cstate there was to
> reach dev_priv, so pass it directly.
>
> Signed-off-by: Paulo Zanoni
Reviewed-by: Ville Syrjäl
In order to ensure that our system suspend and resume callbacks are
called in the correct order wrt. those of the HDA driver add a device
link to the HDA driver during audio component binding time. With i915 as
the supplier and HDA as the consumer the PM framework will guarantee
the HDA->i915 suspe
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Paulo Zanoni
> Sent: keskiviikko 17. lokakuuta 2018 1.53
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for More watermarks improvements
>
> E
On 23/07/2018 13:14, Chris Wilson wrote:
Modernise the test to use igt's ioctl library as opposed to the
antiquated libdrm_intel.
Signed-off-by: Chris Wilson
---
tests/gem_tiled_fence_blits.c | 188 --
1 file changed, 110 insertions(+), 78 deletions(-)
diff
On Thu, Oct 18, 2018 at 01:51:31PM +0200, Maarten Lankhorst wrote:
> The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
> upsampler to upscale YUV420 to YUV444 and the scaler should only be
> used for upscaling. Because of this we shouldn't program the scalers
> in planar mode if
On Thu, Oct 18, 2018 at 01:51:32PM +0200, Maarten Lankhorst wrote:
> We configure the chroma upsampler with the same chroma siting as
> used by the scaler for consistency, the chroma upsampler is used
> instead of the scaler for YUV 4:2:0 on ICL's HDR planes.
>
> Signed-off-by: Maarten Lankhorst
On Thu, Oct 18, 2018 at 01:51:33PM +0200, Maarten Lankhorst wrote:
> The UV plane is the master plane that does all color correction etc.
> It needs to be programmed with the dimensions for color plane 1 (UV).
>
> The Y plane just feeds the Y pixels to it. Program the scaler from the
> master only
On 16/10/2018 16:04, Ville Syrjala wrote:
From: Ville Syrjälä
Replace the kvmalloc_array() with i915_gem_object_get_dma_address() when
populating rotated vmas. One random access mechanism ought to be enough
for everyone?
To calculate the size of the radix tree I think we can do
something like
On Thu, Oct 18, 2018 at 01:51:27PM +0200, Maarten Lankhorst wrote:
> On gen11, we can definitely smash the 32-bits barrier with just a
> when we enable all planes in the next patch.
>
> Signed-off-by: Maarten Lankhorst
I guess the per-plane data rate is still <32bit (because it doesn't
account f
== Series Details ==
Series: drm/i915: Ensure proper HDA suspend/resume ordering with a device link
URL : https://patchwork.freedesktop.org/series/51189/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5008 -> Patchwork_10504 =
== Summary - SUCCESS ==
No regressions found.
On Thu, 18 Oct 2018 16:25:58 +0200,
Imre Deak wrote:
>
> In order to ensure that our system suspend and resume callbacks are
> called in the correct order wrt. those of the HDA driver add a device
> link to the HDA driver during audio component binding time. With i915 as
> the supplier and HDA as
On Thu, Oct 18, 2018 at 01:51:27PM +0200, Maarten Lankhorst wrote:
> On gen11, we can definitely smash the 32-bits barrier with just a
> when we enable all planes in the next patch.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_pm.c | 47 +++-
On Thu, Oct 18, 2018 at 01:51:26PM +0200, Maarten Lankhorst wrote:
> New version, with a lot of reworking to incorporate all the feedback.
>
> We currently don't set the plane input CSC correctly, so colors are a
> bit off. As a result I can't verify for 100% we program the chroma
> upsampler corr
From: Tvrtko Ursulin
A bunch of patches to trace.pl and gem_wsim which enable simulation and load
balancing analysis of the Virtual Engine work done separately by Chris Wilson.
Culmination is being able to simulate a so called frame split media workloads.
Example workload for this looks like th
From: Tvrtko Ursulin
We can improve the parsing loop readability a bit more by avoiding some
line breaks caused by explicit NULL checks.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 39 +++
1 file changed, 15 insertions(+), 24 deletions(-)
diff
From: Tvrtko Ursulin
A few more opportunities to compact the code by using the error logging
helper.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 54 ---
1 file changed, 15 insertions(+), 39 deletions(-)
diff --git a/benchmarks/gem_wsim.c b
From: Tvrtko Ursulin
Support i915 virtual engine from gem_wsim (-b i915) and media-bench.pl
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 289 ++---
scripts/media-bench.pl | 9 +-
2 files changed, 251 insertions(+), 47 deletions(-)
diff --git
From: Tvrtko Ursulin
There is a repeated pattern with error handling which can be moved to a
macro to for better readability in the command parsing loop.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 244 +++---
1 file changed, 88 insertions(+),
From: Tvrtko Ursulin
Add support for submit fences in a way similar to how normal input fences
are handled. Eg:
1.RCS.500-1000.0.0
1.VCS1.3000.s-1.0
1.VCS2.3000.s-2.0
Submit fences are signalled when the originating request enters the
submission backend.
Signed-off-by: Tvrtko Ursulin
--
From: Tvrtko Ursulin
Sync with latest DRM uapi changes.
---
include/drm-uapi/amdgpu_drm.h | 52 +++-
include/drm-uapi/drm.h | 16 ++
include/drm-uapi/drm_fourcc.h | 224 +++
include/drm-uapi/drm_mode.h| 26 +-
include/drm-uapi/etnaviv_drm.h | 6 +
include/drm-uapi/
From: Tvrtko Ursulin
Parsing an integer workload descriptor field is a common pattern which we
can extract to a helper macro and by doing so further improve the
readability of the main parsing loop.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 80 ++
From: Tvrtko Ursulin
Support new i915 uAPI for configuring contexts with engine maps.
Please refer to the README file for more detailed explanation.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 212 ++---
benchmarks/wsim/README | 17 +++-
2 f
From: Tvrtko Ursulin
We are moving towards bumping the uAPI headers more often instead of using
too much local struct/ioctl/param definitions since the latter are more
challenging for rebase and maintenance.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 68 +++--
From: Tvrtko Ursulin
Use the 'completed?' tracepoint field to detect more robustly when a
request has been preempted and remove it from the engine database if so.
Otherwise the script can hit a scenario where the same global seqno will
be mentioned multiple times (on an engine seqno) which abort
From: Tvrtko Ursulin
Add virtual/queue timelines to both stdout and HTML output.
A new timeline is created for each queue/virtual engine to display
associated requests in queued and runnable states. Once requests are
submitted to a real engine for executing they show up on the physical
engine ti
From: Tvrtko Ursulin
A few additional workloads useful for experimenting with scheduling.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/wsim/frame-split-60fps.wsim | 16
benchmarks/wsim/high-composited-game.wsim | 11 +++
benchmarks/wsim/media-1080p-player.wsim
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index a77a322ee309..17325d2ceaf6 100644
--- a/benchmarks/gem_wsim.c
From: Tvrtko Ursulin
For simulating frame split workloads it is useful to express a batch which
ends at the same time as the parallel submission on the respective bonded
engine. For this we add support for infinite batch durations and the batch
terminate command ('T'). Syntax looks like this:
From: Tvrtko Ursulin
A new workload command for enabling a load balanced context map (aka
Virtual Engine). Example usage:
1.B
This turns on load balancing for context one, assuming it has already been
configured with an engine map. Only DEFAULT engine specifier can be used
with load balanced
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index adfc2b1bc819..2561817622f6 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -1170,7 +1170,6 @@ pre
From: Tvrtko Ursulin
Engine bonds are an i915 uAPI applicable to load balanced contexts with
engine map. They allow expression rules of engine selection between two
contexts when submissions are also tied with submit fences.
Please refer to the README for a more detailed description.
Signed-off
Pushed, because I need to get this cherry picked and included in PR.
Thanks for the review.
Regards, Joonas
Quoting Patchwork (2018-10-18 13:12:43)
> == Series Details ==
>
> Series: drm/i915: Drop rpm wakeref on error in debugfs/i915_drop_caches_set
> URL : https://patchwork.freedesktop.org/
On Thu, Oct 18, 2018 at 01:51:29PM +0200, Maarten Lankhorst wrote:
> To make NV12 working on icl, we need to update 2 planes simultaneously.
> I've chosen to do this in the CRTC step after plane validation is done,
> so we know what planes are (in)visible. The linked Y plane will get
> updated in i
On Thu, Oct 18, 2018 at 01:51:30PM +0200, Maarten Lankhorst wrote:
> Skylake style watermarks program the UV parameters into wm->uv_wm,
> and have a separate DDB allocation for UV blocks into the same plane.
>
> Gen11 watermarks have a separate plane for Y and UV, with separate
> mechanisms. The s
On Thu, Oct 18, 2018 at 04:55:52PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 16, 2018 at 03:01:30PM -0700, Paulo Zanoni wrote:
> > Print a more generic "failed to compute watermark levels" whenever any
> > of skl_compute_wm_levels() fail, and print only the specific error
> > message for the specif
Op 18-10-18 om 17:16 schreef Ville Syrjälä:
> On Thu, Oct 18, 2018 at 01:51:26PM +0200, Maarten Lankhorst wrote:
>> New version, with a lot of reworking to incorporate all the feedback.
>>
>> We currently don't set the plane input CSC correctly, so colors are a
>> bit off. As a result I can't verif
On Thu, Oct 18, 2018 at 01:51:34PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
I guess the skl_has_planar() thing should be in this patch..
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/d
drm-misc-fixes-2018-10-18:
drm-misc-fixes for v4.19:
- Fix use of freed memory in drm_mode_setcrtc.
- Reject pixel format changing requests in fb helper.
- Add 6 bpc quirk for HP Pavilion 15-n233sl
- Fix VSDB yCBCr420 Deep Color mode bit definitions
The following changes since commit 4d4c2d89913e2d
Hi Dave,
Here comes the final set of fixes under -next-fixes umbrella.
Next one will be then from -fixes, assuming a release next Sun.
Fixes for bunch of display related issues reported by users, then the
MST fixes that were dropped from Rodrigos PR + further Icelake fixes
and proactive improveme
On Fri, Oct 05, 2018 at 04:23:02PM -0700, Manasi Navare wrote:
> Display Stream Splitter registers need to be programmed to enable
> the joiner if two DSC engines are used and also to enable
> the left and the right DSC engines. This happens as part of
> the DSC enabling routine in the source in at
On Thu, Oct 18, 2018 at 03:52:27PM +0100, Tvrtko Ursulin wrote:
>
> On 16/10/2018 16:04, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Replace the kvmalloc_array() with i915_gem_object_get_dma_address() when
> > populating rotated vmas. One random access mechanism ought to be enough
> > f
On Thu, Oct 18, 2018 at 11:57:06AM +0200, Daniel Vetter wrote:
> On Fri, Oct 12, 2018 at 11:45 PM Jeff McGee wrote:
> >
> > On Fri, Oct 12, 2018 at 02:33:26PM -0700, Jeff McGee wrote:
> > > On Fri, Oct 12, 2018 at 01:51:46PM -0700, Rodrigo Vivi wrote:
> > > > On Fri, Oct 12, 2018 at 01:24:30PM -07
On Thu, Oct 18, 2018 at 10:32:37AM -0700, Jeff McGee wrote:
> On Thu, Oct 18, 2018 at 11:57:06AM +0200, Daniel Vetter wrote:
> > On Fri, Oct 12, 2018 at 11:45 PM Jeff McGee wrote:
> > >
> > > On Fri, Oct 12, 2018 at 02:33:26PM -0700, Jeff McGee wrote:
> > > > On Fri, Oct 12, 2018 at 01:51:46PM -07
On 18/10/18 02:13, Chris Wilson wrote:
Quoting Michal Wajdeczko (2018-10-18 00:22:43)
On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
wrote:
On 17/10/18 13:29, Chris Wilson wrote:
Propagate the timeout on transferring the fw back to the caller where it
may act upon it, usually
On Thu, 18 Oct 2018 20:18:53 +0200, Daniele Ceraolo Spurio
wrote:
On 18/10/18 02:13, Chris Wilson wrote:
Quoting Michal Wajdeczko (2018-10-18 00:22:43)
On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
wrote:
On 17/10/18 13:29, Chris Wilson wrote:
Propagate the timeout on tr
We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.
v2: No message from host to GuC uses more than 8 registers and
the GuC FW itself uses an
GuC is disabled by default. Enable it.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/g
On 18/10/18 03:41, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Upcoming GuC code will need to read the fused off engine masks as well,
and will also want to have them as enabled instead of disabled masks.
To consolidate the read-out place we can store them in this fashion inside
INTEL_INFO so
On 18/10/18 11:30, Michal Wajdeczko wrote:
We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.
v2: No message from host to GuC uses more
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/guc: Limit number of scratch
registers used for H2G
URL : https://patchwork.freedesktop.org/series/51206/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5010 -> Patchwork_10505 =
== Summary - FAILURE ==
On Thu, Oct 18, 2018 at 6:57 PM Joonas Lahtinen
wrote:
>
> Hi Dave,
>
> Here comes the final set of fixes under -next-fixes umbrella.
> Next one will be then from -fixes, assuming a release next Sun.
>
> Fixes for bunch of display related issues reported by users, then the
> MST fixes that were dr
Quoting Michal Wajdeczko (2018-10-18 19:27:20)
> On Thu, 18 Oct 2018 20:18:53 +0200, Daniele Ceraolo Spurio
> wrote:
>
> >
> >
> > On 18/10/18 02:13, Chris Wilson wrote:
> >> Quoting Michal Wajdeczko (2018-10-18 00:22:43)
> >>> On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
> >>> w
Propagate the timeout on transferring the fw back to the caller where it
may act upon it, usually by restarting the xfer before failing.
v2: Simplify the wait to only wait upon the guc signaling completion,
with an assertion that the fw xfer must have completed for it to be
ready!
Testcase: igt/d
Propagate the timeout on transferring the fw back to the caller where it
may act upon it, usually by restarting the xfer before failing.
v2: Simplify the wait to only wait upon the guc signaling completion,
with an assertion that the fw xfer must have completed for it to be
ready!
Testcase: igt/d
From: Ville Syrjälä
The SKL+ NV12 src width alignment w/a is still living in an odd place.
Everything else was already relocated closer to the main plane check
function. Move this workaround as well.
As a bonus we avoid the funky rotated vs. not mess with the src
coordinates as this now gets che
From: Ville Syrjälä
Let's run through the entire plane check even when the plane
is invisible due to zero constant alpha. This makes for more
consistent behaviour since we check the src/dst coordinates,
stride etc. against the hardware limits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i
== Series Details ==
Series: drm/i915/guc: Propagate the fw xfer timeout (rev2)
URL : https://patchwork.freedesktop.org/series/51140/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5010 -> Patchwork_10506 =
== Summary - FAILURE ==
Serious unknown changes coming with Patch
== Series Details ==
Series: drm/i915/guc: Propagate the fw xfer timeout (rev3)
URL : https://patchwork.freedesktop.org/series/51140/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5010 -> Patchwork_10507 =
== Summary - SUCCESS ==
No regressions found.
External URL:
h
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