== Series Details ==
Series: PSR interrupts
URL : https://patchwork.freedesktop.org/series/40332/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3cde2d1d81fc drm/i915: Enable edp psr error interrupts on hsw
-:106: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#106:
== Series Details ==
Series: PSR interrupts
URL : https://patchwork.freedesktop.org/series/40332/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Enable edp psr error interrupts on hsw
-drivers/gpu/drm/i915/gvt/gtt.c:661:9:expected void [noderef] **slot
-drivers
== Series Details ==
Series: PSR interrupts
URL : https://patchwork.freedesktop.org/series/40332/
State : success
== Summary ==
Series 40332v1 PSR interrupts
https://patchwork.freedesktop.org/api/1.0/series/40332/revisions/1/mbox/
Possible new issues:
Test kms_pipe_crc_basic:
Su
On Tue, Mar 20, 2018 at 09:17:52PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we're leaking fbs on load detect on account of nothing setting
> up plane->old_fb for the drm_atomic_clean_old_fb() call in
> drm_atomic_helper_commit_duplicated_state(). Removing the
> drm_atomic_c
On Tue, Mar 20, 2018 at 01:24:09PM +0200, Laurent Pinchart wrote:
> Hi Ulrich,
>
> Thank you for the patch.
>
> On Thursday, 15 March 2018 16:45:38 EET Ulrich Hecht wrote:
> > Fixes false negatives on non-i915 platforms.
> >
> > Signed-off-by: Ulrich Hecht
> > ---
> > tests/kms_panel_fitting.c
== Series Details ==
Series: series starting with [1/2] drm/i915: Add code to accept valid locked
WOPCM register values
URL : https://patchwork.freedesktop.org/series/40334/
State : warning
== Summary ==
Series 40334v1 series starting with [1/2] drm/i915: Add code to accept valid
locked WOPC
On Tue, Mar 20, 2018 at 01:32:17PM +0200, Laurent Pinchart wrote:
> Hello,
>
> On Monday, 19 March 2018 18:41:05 EET Ulrich Hecht wrote:
> > On Fri, Mar 16, 2018 at 9:55 AM, Daniel Vetter wrote:
> > > On Thu, Mar 15, 2018 at 03:45:36PM +0100, Ulrich Hecht wrote:
> > >> Hi!
> > >>
> > >> I have r
Hi Daniel,
On Wednesday, 21 March 2018 10:34:33 EET Daniel Vetter wrote:
> On Tue, Mar 20, 2018 at 01:24:09PM +0200, Laurent Pinchart wrote:
> > Hi Ulrich,
> >
> > Thank you for the patch.
> >
> > On Thursday, 15 March 2018 16:45:38 EET Ulrich Hecht wrote:
> > > Fixes false negatives on non-i915
We were relying on the uncached reads when processing the CSB to provide
ourselves with the serialisation with the interrupt handler (so we could
detect new interrupts in the middle of processing the old one). However,
in commit 767a983ab255 ("drm/i915/execlists: Read the context-status HEAD
from t
== Series Details ==
Series: PSR interrupts
URL : https://patchwork.freedesktop.org/series/40332/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass -> FAIL (shard-hsw) fdo#102887
Subgroup 2x-pla
== Series Details ==
Series: drm/i915/execlists: Use a locked clear_bit() for synchronisation with
interrupt
URL : https://patchwork.freedesktop.org/series/40359/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d0c27de732e3 drm/i915/execlists: Use a locked clear_bit() for synchr
== Series Details ==
Series: drm/i915/execlists: Use a locked clear_bit() for synchronisation with
interrupt
URL : https://patchwork.freedesktop.org/series/40359/
State : warning
== Summary ==
Series 40359v1 drm/i915/execlists: Use a locked clear_bit() for synchronisation
with interrupt
http
+ Jon, as we clearly have a disconnect between what was requested to be
done and what has been done.
Quoting Dunajski, Bartosz (2018-03-20 17:15:06)
> This functionality is used by new OCL drvier (aka. NEO):
> https://github.com/intel/compute-runtime
>
> Starting from commit: 933312e0986d3a7c1ef
If we fail to reset the GPU in a timely fashion, dump the GEM trace so
that we can see what operations were in flight when the GPU got stuck.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
On 20/03/2018 19:45, Oscar Mateo wrote:
From: Kelvin Gardiner
This patch adds support to detect ICL, slice, subslice and EU fuse
settings.
Add addresses for ICL 11 slice, subslice and EU fuses registers.
These register addresses are the same as previous platforms but the
format and / or the m
On 21/03/2018 09:10, Chris Wilson wrote:
We were relying on the uncached reads when processing the CSB to provide
ourselves with the serialisation with the interrupt handler (so we could
detect new interrupts in the middle of processing the old one). However,
in commit 767a983ab255 ("drm/i915/ex
Quoting Oscar Mateo (2018-03-20 18:43:45)
>
>
> On 3/19/2018 7:14 AM, Lis, Tomasz wrote:
> >
> >
> > On 2018-03-19 13:43, Chris Wilson wrote:
> >> Quoting Tomasz Lis (2018-03-19 12:37:35)
> >>> The patch adds a parameter to control the data port coherency
> >>> functionality
> >>> on a per-exec
== Series Details ==
Series: drm/i915/execlists: Use a locked clear_bit() for synchronisation with
interrupt
URL : https://patchwork.freedesktop.org/series/40359/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6cf422f94c61 drm/i915/execlists: Use a locked clear_bit() for synchr
On Tue, Mar 20, 2018 at 02:50:26PM -0700, Lucas De Marchi wrote:
> On Tue, Mar 20, 2018 at 2:56 AM, Ville Syrjälä
> wrote:
> > On Mon, Mar 19, 2018 at 11:24:17PM -0700, Lucas De Marchi wrote:
> >> This will allow the struct to be embedded in intel_shared_dpll.
> >>
> >> Signed-off-by: Lucas De Mar
From: Tvrtko Ursulin
Log up to sseu->max_slices instead basing on ARRAY_SIZE since to avoid
printing impossible and empty slices for a platform.
Also compact slice total and slice mask into one log line.
Signed-off-by: Tvrtko Ursulin
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_devic
Hi,
On Wed, Mar 14, 2018 at 12:44:10PM +0200, Petri Latvala wrote:
> On Tue, Mar 13, 2018 at 04:18:54PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > On Tue, Mar 13, 2018 at 12:42:02PM +0200, Petri Latvala wrote:
> > > On Mon, Mar 05, 2018 at 03:21:29PM +0100, Maxime Ripard wrote:
> > > > Add some
Quoting Tvrtko Ursulin (2018-03-21 10:32:28)
> From: Tvrtko Ursulin
>
> Log up to sseu->max_slices instead basing on ARRAY_SIZE since to avoid
> printing impossible and empty slices for a platform.
>
> Also compact slice total and slice mask into one log line.
>
> Signed-off-by: Tvrtko Ursulin
== Series Details ==
Series: drm/i915/execlists: Use a locked clear_bit() for synchronisation with
interrupt
URL : https://patchwork.freedesktop.org/series/40359/
State : failure
== Summary ==
Series 40359v1 drm/i915/execlists: Use a locked clear_bit() for synchronisation
with interrupt
http
Chris Wilson writes:
> We were relying on the uncached reads when processing the CSB to provide
> ourselves with the serialisation with the interrupt handler (so we could
> detect new interrupts in the middle of processing the old one). However,
> in commit 767a983ab255 ("drm/i915/execlists: Read
Reviewed-by: Lionel Landwerlin
On 21/03/18 10:32, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Log up to sseu->max_slices instead basing on ARRAY_SIZE since to avoid
printing impossible and empty slices for a platform.
Also compact slice total and slice mask into one log line.
Signed-off-by:
Quoting Chris Wilson (2018-03-21 10:41:37)
> Quoting Tvrtko Ursulin (2018-03-21 10:32:28)
> > From: Tvrtko Ursulin
> >
> > Log up to sseu->max_slices instead basing on ARRAY_SIZE since to avoid
> > printing impossible and empty slices for a platform.
> >
> > Also compact slice total and slice ma
== Series Details ==
Series: drm/i915/selftests: Include the trace as a debug aide
URL : https://patchwork.freedesktop.org/series/40362/
State : success
== Summary ==
Series 40362v1 drm/i915/selftests: Include the trace as a debug aide
https://patchwork.freedesktop.org/api/1.0/series/40362/rev
== Series Details ==
Series: drm/i915: Skip logging impossible slices
URL : https://patchwork.freedesktop.org/series/40367/
State : success
== Summary ==
Series 40367v1 drm/i915: Skip logging impossible slices
https://patchwork.freedesktop.org/api/1.0/series/40367/revisions/1/mbox/
Known
Hi,
On Mon, Mar 05, 2018 at 03:21:26PM +0100, Maxime Ripard wrote:
> Here is an RFC at starting to test the plane formats using the
> Chamelium over the HDMI. This was tested using the vc4 DRM driver
> found on the RaspberryPi.
>
> This is still pretty rough around the edges at this point, but I'
== Series Details ==
Series: drm/i915/execlists: Use a locked clear_bit() for synchronisation with
interrupt
URL : https://patchwork.freedesktop.org/series/40359/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6b81af0baaa5 drm/i915/execlists: Use a locked clear_bit() for synchr
On Wed, 21 Mar 2018, Chris Wilson wrote:
> Quoting Chris Wilson (2018-03-21 10:41:37)
>> Quoting Tvrtko Ursulin (2018-03-21 10:32:28)
>> > From: Tvrtko Ursulin
>> >
>> > Log up to sseu->max_slices instead basing on ARRAY_SIZE since to avoid
>> > printing impossible and empty slices for a platfor
== Series Details ==
Series: drm/i915/selftests: Include the trace as a debug aide
URL : https://patchwork.freedesktop.org/series/40362/
State : success
== Summary ==
Known issues:
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass -> FAIL (sha
== Series Details ==
Series: drm/i915/execlists: Use a locked clear_bit() for synchronisation with
interrupt
URL : https://patchwork.freedesktop.org/series/40359/
State : success
== Summary ==
Series 40359v1 drm/i915/execlists: Use a locked clear_bit() for synchronisation
with interrupt
http
Joonas suggests to include these files guc.c and wopcm.c in i915.rst
with WOPCM being separate section from GuC.
Also ensure make htmldocs generates proper/expected documentation.
Thanks,
Sagar
On 3/15/2018 10:24 PM, Jackie Li wrote:
GuC Address Space and WOPCM Layout diagrams won't be generat
Quoting Jani Nikula (2018-03-21 11:47:06)
>
> On Wed, 21 Mar 2018, Chris Wilson wrote:
> > Quoting Chris Wilson (2018-03-21 10:41:37)
> >> Quoting Tvrtko Ursulin (2018-03-21 10:32:28)
> >> > From: Tvrtko Ursulin
> >> >
> >> > Log up to sseu->max_slices instead basing on ARRAY_SIZE since to avoi
Tvrtko Ursulin writes:
> On 20/03/2018 19:45, Oscar Mateo wrote:
>> From: Kelvin Gardiner
>>
>> This patch adds support to detect ICL, slice, subslice and EU fuse
>> settings.
>>
>> Add addresses for ICL 11 slice, subslice and EU fuses registers.
>> These register addresses are the same as pre
On Wed, 21 Mar 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-03-21 11:47:06)
>>
>> On Wed, 21 Mar 2018, Chris Wilson wrote:
>> > Quoting Chris Wilson (2018-03-21 10:41:37)
>> >> Quoting Tvrtko Ursulin (2018-03-21 10:32:28)
>> >> > From: Tvrtko Ursulin
>> >> >
>> >> > Log up to sseu->ma
On Wed, Mar 21, 2018 at 09:25:06AM +0100, Daniel Vetter wrote:
> On Tue, Mar 20, 2018 at 09:17:52PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently we're leaking fbs on load detect on account of nothing setting
> > up plane->old_fb for the drm_atomic_clean_old_fb() call in
>
== Series Details ==
Series: drm/i915: Skip logging impossible slices
URL : https://patchwork.freedesktop.org/series/40367/
State : warning
== Summary ==
Possible new issues:
Test kms_setmode:
Subgroup clone-exclusive-crtc:
pass -> DMESG-WARN (shard-hsw)
--
On Wed, 21 Mar 2018 10:08:03 +0100
Gerd Hoffmann wrote:
> On unknown/unhandled ioctls the driver should return an error, so
> userspace knows it tried to use something unsupported.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Gerd Hoffmann
> ---
> drivers/gpu/drm/i915/gvt/kvmgt.c | 2 +-
>
If we fail to reset the GPU in a timely fashion, dump the GEM trace so
that we can see what operations were in flight when the GPU got stuck.
v2: There's more than one timeout that deserves tracing!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 23 ++
== Series Details ==
Series: drm/i915/execlists: Use a locked clear_bit() for synchronisation with
interrupt
URL : https://patchwork.freedesktop.org/series/40359/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup plain-flip-fb-recreate:
pass
== Series Details ==
Series: drm/i915/selftests: Include the trace as a debug aide (rev2)
URL : https://patchwork.freedesktop.org/series/40362/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
70bb04812995 drm/i915/selftests: Include the trace as a debug aide
-:36: CHECK:SPACING:
Fix the last two direct ->gen usages.
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_devi
Prefix gen and gen_mask in struct intel_device_info with underscores to
hint that they should not be used directly, except in special
circumstances.
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++--
drivers/gpu/drm/i915/i915
== Series Details ==
Series: drm/i915/selftests: Include the trace as a debug aide (rev2)
URL : https://patchwork.freedesktop.org/series/40362/
State : success
== Summary ==
Series 40362v2 drm/i915/selftests: Include the trace as a debug aide
https://patchwork.freedesktop.org/api/1.0/series/40
Quoting Jani Nikula (2018-03-21 14:07:54)
> Fix the last two direct ->gen usages.
>
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/d
On Wed, 21 Mar 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-03-21 14:07:54)
>> Fix the last two direct ->gen usages.
>>
>> Cc: Tvrtko Ursulin
>> Cc: Mika Kuoppala
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
>> 1 file changed, 2 insertion
During debugging gpgpu_fill test on various platforms, I found out few
things that can affect newer gens:
Seting number of threads in TS in gen8_fill_interface_descriptor to 1.
This field was omitted in earlier platforms (apparently without any side
effects). Not setting it for newer platforms re
Prefer INTEL_GEN() over INTEL_INFO()->gen except in special
circumstances.
v2: don't change device info dump (Chris)
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Prefix gen and gen_mask in struct intel_device_info with underscores to
hint that they should not be used directly, except in special
circumstances.
v2: Rebase
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++--
drivers/gpu/d
== Series Details ==
Series: series starting with [1/2] drm/i915: prefer INTEL_GEN() over
INTEL_INFO()->gen
URL : https://patchwork.freedesktop.org/series/40374/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK incl
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: prefer INTEL_GEN() over
INTEL_INFO()->gen
URL : https://patchwork.freedesktop.org/series/40380/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK i
Hi Dave,
Here's the last PR for 4.17 from -misc-next, we'll move over to -misc-next-fixes
once this is pulled. We have 2 weeks of work here, since I dropped the ball when
I was out sick last week.
2 things to point out: Lukas' device link work on vga_switcheroo is pretty
awesome, and lots of pa
== Series Details ==
Series: lib/gpgpu_fill: Adding missing configuration parameters for gpgpu_fill
function
URL : https://patchwork.freedesktop.org/series/40378/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
ddc4ffb00e389a4dd584e8055eadf283dff69db5 lib:
After resetting the GPU (or subset of engines), call synchronize_irq()
to flush any pending irq before proceeding with the cleanup. For a
device level reset, we disable the interupts around the reset, but when
resetting just one engine, we have to avoid such global disabling. This
leaves us open to
On Wed, 21 Mar 2018, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/2] drm/i915: prefer INTEL_GEN() over
> INTEL_INFO()->gen
> URL : https://patchwork.freedesktop.org/series/40380/
> State : failure
>
> == Summary ==
>
> CHK include/config/kernel.release
>
Quoting Michel Thierry (2018-03-14 23:34:33)
> On 14/03/18 15:23, Michal Wajdeczko wrote:
> > On Wed, 14 Mar 2018 21:17:29 +0100, Michel Thierry
> > wrote:
> >
> >> On 14/03/18 13:04, Michal Wajdeczko wrote:
> >>> We try to keep all HuC related code in dedicated file.
> >>> There is no need to p
Quoting Patchwork (2018-03-20 19:04:24)
> == Series Details ==
>
> Series: series starting with [CI,1/3] drm/i915/guc: Unify naming of private
> GuC action functions
> URL : https://patchwork.freedesktop.org/series/40311/
> State : success
>
> == Summary ==
>
> Series 40311v1 series starting
Quoting Michal Wajdeczko (2018-03-20 16:20:20)
> There is no need to mix parameter types in public CT functions
> as we can always accept intel_guc_ct.
>
> v2: fix 'Return' doc, s/dev_priv/i915 (Sagar)
>
> Signed-off-by: Michal Wajdeczko
> Cc: Sagar Arun Kamble
> Cc: Chris Wilson
> Reviewed-by
Quoting Michał Winiarski (2018-03-20 18:56:59)
> On Mon, Mar 19, 2018 at 12:50:49PM +, Michal Wajdeczko wrote:
> > We already try to keep all GuC log related code in separate file,
> > handling flush event should be placed there too. This will also
> > allow future code reuse.
> >
> > v2: reba
Quoting Zhenyu Wang (2018-03-20 04:41:08)
>
> Hi, Joonas
>
> Here's gvt-next-fixes update for 4.17. One regression that
> caused guest VM gpu hang has been fixed and with other changes
> as details below.
Pulled, thanks.
Regards, Joonas
___
Intel-gfx
On Wed, Mar 21, 2018 at 03:00:23PM +, Chris Wilson wrote:
> After resetting the GPU (or subset of engines), call synchronize_irq()
> to flush any pending irq before proceeding with the cleanup. For a
> device level reset, we disable the interupts around the reset, but when
> resetting just one
Quoting Jeff McGee (2018-03-21 15:55:16)
> On Wed, Mar 21, 2018 at 03:00:23PM +, Chris Wilson wrote:
> > After resetting the GPU (or subset of engines), call synchronize_irq()
> > to flush any pending irq before proceeding with the cleanup. For a
> > device level reset, we disable the interupts
Quoting Jeff McGee (2018-03-21 15:55:16)
> On Wed, Mar 21, 2018 at 03:00:23PM +, Chris Wilson wrote:
> > After resetting the GPU (or subset of engines), call synchronize_irq()
> > to flush any pending irq before proceeding with the cleanup. For a
> > device level reset, we disable the interupts
== Series Details ==
Series: drm/i915: Flush pending interrupt following a GPU reset
URL : https://patchwork.freedesktop.org/series/40383/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c3bbd56f3b68 drm/i915: Flush pending interrupt following a GPU reset
-:23: WARNING:COMMIT_LOG
On 3/21/2018 3:46 AM, Mika Kuoppala wrote:
Chris Wilson writes:
We were relying on the uncached reads when processing the CSB to provide
ourselves with the serialisation with the interrupt handler (so we could
detect new interrupts in the middle of processing the old one). However,
in commit 7
Quoting Michel Thierry (2018-03-21 17:01:12)
> On 3/21/2018 3:46 AM, Mika Kuoppala wrote:
> > Chris Wilson writes:
> >
> >> We were relying on the uncached reads when processing the CSB to provide
> >> ourselves with the serialisation with the interrupt handler (so we could
> >> detect new interr
Quoting Chris Wilson (2018-03-21 17:05:06)
> Quoting Michel Thierry (2018-03-21 17:01:12)
> > On 3/21/2018 3:46 AM, Mika Kuoppala wrote:
> > > Chris Wilson writes:
> > >
> > >> We were relying on the uncached reads when processing the CSB to provide
> > >> ourselves with the serialisation with th
Maxime Ripard writes:
> [ Unknown signature status ]
> Hi,
>
> On Mon, Mar 05, 2018 at 03:21:26PM +0100, Maxime Ripard wrote:
>> Here is an RFC at starting to test the plane formats using the
>> Chamelium over the HDMI. This was tested using the vc4 DRM driver
>> found on the RaspberryPi.
>>
>>
Quoting Michel Thierry (2018-03-21 17:01:12)
> On 3/21/2018 3:46 AM, Mika Kuoppala wrote:
> > Chris Wilson writes:
> >
> >> We were relying on the uncached reads when processing the CSB to provide
> >> ourselves with the serialisation with the interrupt handler (so we could
> >> detect new interr
== Series Details ==
Series: drm/i915: Flush pending interrupt following a GPU reset
URL : https://patchwork.freedesktop.org/series/40383/
State : success
== Summary ==
Series 40383v1 drm/i915: Flush pending interrupt following a GPU reset
https://patchwork.freedesktop.org/api/1.0/series/40383
On Wed, Mar 21, 2018 at 04:42:32PM +, Chris Wilson wrote:
> Quoting Jeff McGee (2018-03-21 15:55:16)
> > On Wed, Mar 21, 2018 at 03:00:23PM +, Chris Wilson wrote:
> > > After resetting the GPU (or subset of engines), call synchronize_irq()
> > > to flush any pending irq before proceeding wi
== Series Details ==
Series: drm/i915/selftests: Include the trace as a debug aide (rev2)
URL : https://patchwork.freedesktop.org/series/40362/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup flip-vs-absolute-wf_vblank:
pass -> FAIL
From: Chris Wilson
In preparation to more carefully handling incomplete preemption during
reset by execlists, we move the existing code wholesale to the backends
under a couple of new reset vfuncs.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
CC: Michel Thierry
Cc: Jeff McGee
---
driver
From: Chris Wilson
As a complement to inject_preempt_context(), follow up with the function
to handle its completion. This will be useful should we wish to extend
the duties of the preempt-context for execlists.
Signed-off-by: Chris Wilson
Cc: Jeff McGee
Cc: Michał Winiarski
---
drivers/gpu/
From: Chris Wilson
Catch up with the inflight CSB events, after disabling the tasklet
before deciding which request was truly guilty of hanging the GPU.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
CC: Michel Thierry
Cc: Jeff McGee
---
drivers/gpu/drm/i915/intel_lrc.c | 355
From: Jeff McGee
Engine reset is fast. A context switch interrupt may be generated just
prior to the reset such that the top half handler is racing with reset
post-processing. The handler may set the irq_posted bit again after
the reset code has cleared it to start fresh. Then the re-enabled
task
From: Jeff McGee
Signed-off-by: Jeff McGee
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index beb81f13a3cc..cec4e1653daf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
From: Chris Wilson
In the next patch, we will make the execlists reset prepare callback
take into account preemption by flushing the context-switch handler.
This is not applicable to the GuC submission backend, so split the two
into their own backend callbacks.
Signed-off-by: Chris Wilson
Cc: M
From: Jeff McGee
Force preemption uses engine reset to enforce a limit on the time
that a request targeted for preemption can block. This feature is
a requirement in automotive systems where the GPU may be shared by
clients of critically high priority and clients of low priority that
may not have
From: Jeff McGee
The hardware can complete the requested preemption at only certain points
in execution. Thus an uncooperative request that avoids those points can
block a preemption indefinitely. Our only option to bound the preemption
latency is to trigger reset and recovery just as we would if
From: Chris Wilson
Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error capture so add a bit to request the state to be
captured and saved.
v2: Pass msg down to i915_reset/i915_reset_en
On Wed, Mar 21, 2018 at 10:26:24AM -0700, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> Engine reset is fast. A context switch interrupt may be generated just
> prior to the reset such that the top half handler is racing with reset
> post-processing. The handler may set the irq_posted bit ag
On Wed, Mar 21, 2018 at 10:26:23AM -0700, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> Signed-off-by: Jeff McGee
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/in
On Fri, Mar 16, 2018 at 04:01:21PM +0100, Maarten Lankhorst wrote:
> Instead of taking fbc->lock inside the worker, don't take any lock
> and cancel the work synchronously to prevent races. Since the worker
> waits for a vblank before activating, wake up all vblank waiters after
> signalling the ca
Quoting Jeff McGee (2018-03-21 17:33:04)
> On Wed, Mar 21, 2018 at 10:26:23AM -0700, jeff.mc...@intel.com wrote:
> > From: Jeff McGee
> >
> > Signed-off-by: Jeff McGee
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/dr
Quoting Jeff McGee (2018-03-21 17:31:45)
> On Wed, Mar 21, 2018 at 10:26:24AM -0700, jeff.mc...@intel.com wrote:
> > From: Jeff McGee
> >
> > Engine reset is fast. A context switch interrupt may be generated just
> > prior to the reset such that the top half handler is racing with reset
> > post-
== Series Details ==
Series: lib/gpgpu_fill: Adding missing configuration parameters for gpgpu_fill
function
URL : https://patchwork.freedesktop.org/series/40378/
State : success
== Summary ==
Possible new issues:
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-at
On Wed, Mar 21, 2018 at 06:06:44PM +, Chris Wilson wrote:
> Quoting Jeff McGee (2018-03-21 17:33:04)
> > On Wed, Mar 21, 2018 at 10:26:23AM -0700, jeff.mc...@intel.com wrote:
> > > From: Jeff McGee
> > >
> > > Signed-off-by: Jeff McGee
> > > ---
> > > drivers/gpu/drm/i915/intel_lrc.c | 2 +-
== Series Details ==
Series: Force preemption (rev2)
URL : https://patchwork.freedesktop.org/series/40120/
State : failure
== Summary ==
Applying: drm/i915/execlists: Refactor out complete_preempt_context()
Applying: drm/i915: Add control flags to i915_handle_error()
error: Failed to merge in
Watch what happens if we try to reset with a queue of requests with
varying priorities -- that may need reordering or preemption across the
reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 154 +++
1 file changed, 103 insertions(+), 51
On Tue, Mar 20, 2018 at 03:41:47PM -0700, Dhinakaran Pandiyan wrote:
> From: Daniel Vetter
>
> The definitions for the error register should be valid on bdw/skl too,
> but there we haven't even enabled DE_MISC handling yet.
>
> Somewhat confusing the the moved register offset on bdw is only for
Quoting Jeff McGee (2018-03-21 18:29:46)
> On Wed, Mar 21, 2018 at 06:06:44PM +, Chris Wilson wrote:
> > Quoting Jeff McGee (2018-03-21 17:33:04)
> > > On Wed, Mar 21, 2018 at 10:26:23AM -0700, jeff.mc...@intel.com wrote:
> > > > From: Jeff McGee
> > > >
> > > > Signed-off-by: Jeff McGee
> >
Quoting Chris Wilson (2018-03-21 18:12:51)
> Quoting Jeff McGee (2018-03-21 17:31:45)
> > On Wed, Mar 21, 2018 at 10:26:24AM -0700, jeff.mc...@intel.com wrote:
> > > From: Jeff McGee
> > >
> > > Engine reset is fast. A context switch interrupt may be generated just
> > > prior to the reset such t
From: Colin Ian King
The pointer workload is dereferenced before it is null checked, hence
there is a potential for a null pointer dereference on workload. Fix
this by only dereferencing workload after it is null checked.
Detected by CoverityScan, CID#1466017 ("Dereference before null check")
F
On Wed, 2018-03-21 at 19:06 +, Colin King wrote:
> From: Colin Ian King
>
> The pointer workload is dereferenced before it is null checked, hence
> there is a potential for a null pointer dereference on workload. Fix
> this by only dereferencing workload after it is null checked.
>
> Detecte
== Series Details ==
Series: drm/i915/selftests: Stress resets-vs-request-priority
URL : https://patchwork.freedesktop.org/series/40397/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
db8550b31cc9 drm/i915/selftests: Stress resets-vs-request-priority
-:272: CHECK:SPACING: spaces
Using engine->irq_posted for execlists, we are not always serialised by
the tasklet as we supposed. On the reset paths, the tasklet is disabled
and ignored. Instead, we manipulate the engine->irq_posted directly to
account for the reset, but if an interrupt fired before the reset and so
wrote to en
On 21/03/18 19:09, Joe Perches wrote:
> On Wed, 2018-03-21 at 19:06 +, Colin King wrote:
>> From: Colin Ian King
>>
>> The pointer workload is dereferenced before it is null checked, hence
>> there is a potential for a null pointer dereference on workload. Fix
>> this by only dereferencing wor
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