On Fri, Sep 01, 2017 at 11:02:11AM +0530, Sagar Arun Kamble wrote:
> Teardown of GuC HW/SW state was not properly done in unload path.
> During unload, we can rely on intel_guc_reset_prepare being done
> as part of i915_gem_suspend for disabling GuC interfaces.
> We will have to disable GuC submiss
== Series Details ==
Series: i915: Fix obj size vs. alignment for drm_pci_alloc()
URL : https://patchwork.freedesktop.org/series/29954/
State : success
== Summary ==
Test kms_atomic_transition:
Subgroup plane-use-after-nonblocking-unbind:
incomplete -> FAIL (shard
On Fri, Sep 01, 2017 at 11:02:12AM +0530, Sagar Arun Kamble wrote:
> With GuC v9, new type of Default/critical logging in GuC to enable
> capturing minimal important logs in production systems efficiently.
> This patch enables this logging in GuC by default always. It should
> be noted that streami
Looks good to me.
Reviewed-by: Lyude Paul
On Wed, 2017-09-06 at 17:14 -0700, Dhinakaran Pandiyan wrote:
> The POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions
> allow
> the source to reqest any node in a mst path or a whole path to be
> powered down or up. This allows drivers to tar
Quoting Chris Wilson (2017-08-23 13:55:55)
> At the moment, the verify tests use an extremely brutal write-read of
> every dword, degrading performance to UC. If we break those up into
> cachelines, we can do a wcb write/read at a time instead, roughly 8x
> faster. We lose the accuracy of the force
Quoting Chris Wilson (2017-08-15 11:34:30)
> These tests do not tell the kernel they can use the upper 48bits of
> aperture space, and cause eviction on the low 4G just as effectively
> exercising the evict code.
>
> Signed-off-by: Chris Wilson
* Crickets.
> ---
> tests/gem_evict_alignment.c
On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote:
> We also see the delayed GTT write issue on i915g/i915gm, so let's
> presume that it is a universal problem for all llc machines, and that we
> just haven't yet noticed on g33, gen4 and gen5 machines.
>
> Testcase: igt/gem_mmap_gtt/coh
On 9/7/2017 5:15 AM, Katarzyna Dec wrote:
Added comments in tricky places for better feature understanding.
Added IGT_TEST_DESCRIPTION and short description for non-obvious
subtests.
Changed name of 'magic' checkit() function to something meaningfull.
Changed junk struct and stuff array names.
It's a silly test. If fails if there is an *ERROR* in the dmesg ringbuf,
so it neither is testing that errors are generated as expected, and as a
pre-check it can only see what's at the end of the dmesg and may miss
earlier faults. As a test it just randomly fails; worse than useless.
Signed-off-b
Quoting Ville Syrjälä (2017-09-07 19:23:27)
> On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote:
> > We also see the delayed GTT write issue on i915g/i915gm, so let's
> > presume that it is a universal problem for all llc machines, and that we
> > just haven't yet noticed on g33, gen4 an
Quoting ville.syrj...@linux.intel.com (2017-09-06 14:04:01)
> From: Ville Syrjälä
>
> "echo 1 > vtconN/bind" doesn't actually do anything. Looks like the only
> way to rebind fbcon is to unbind the current console.
>
> I suppose the failure to rebind might be a kernel bug, but I can't be
> bothe
We also see the delayed GTT write issue on i915g/i915gm, so let's
presume that it is a universal problem for all !llc machines, and that we
just haven't yet noticed on g33, gen4 and gen5 machines.
v2: Use a register that exists on all platforms
Testcase: igt/gem_mmap_gtt/coherency # i915gm
Refere
On Thu, Sep 07, 2017 at 07:35:22PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2017-09-07 19:23:27)
> > On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote:
> > > We also see the delayed GTT write issue on i915g/i915gm, so let's
> > > presume that it is a universal problem for all
On Thu, Sep 07, 2017 at 07:45:20PM +0100, Chris Wilson wrote:
> We also see the delayed GTT write issue on i915g/i915gm, so let's
> presume that it is a universal problem for all !llc machines, and that we
> just haven't yet noticed on g33, gen4 and gen5 machines.
>
> v2: Use a register that exist
On Thu, 2017-09-07 at 14:04 -0400, Lyude Paul wrote:
> Looks good to me.
>
> Reviewed-by: Lyude Paul
>
Thanks for the review.
-DK
> On Wed, 2017-09-06 at 17:14 -0700, Dhinakaran Pandiyan wrote:
> > The POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions
> > allow
> > the source
On Thu, Sep 07, 2017 at 05:53:30PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 07, 2017 at 03:43:26PM +0100, Chris Wilson wrote:
> > Quoting ville.syrj...@linux.intel.com (2017-09-07 15:32:03)
> > > From: Ville Syrjälä
> > >
> > > drm_pci_alloc() refuses to cooperate if the passed alignment exceeds
== Series Details ==
Series: drm/i915: Apply the GTT write flush for all !llc machines (rev2)
URL : https://patchwork.freedesktop.org/series/29953/
State : failure
== Summary ==
Series 29953v2 drm/i915: Apply the GTT write flush for all !llc machines
https://patchwork.freedesktop.org/api/1.0/s
Quoting Chris Wilson (2017-09-07 19:29:25)
> It's a silly test. If fails if there is an *ERROR* in the dmesg ringbuf,
> so it neither is testing that errors are generated as expected, and as a
> pre-check it can only see what's at the end of the dmesg and may miss
> earlier faults. As a test it jus
== Series Details ==
Series: igt/tools_test: Remove dmesg subtest
URL : https://patchwork.freedesktop.org/series/29970/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
e49c3feda5e379fbba58731b74beccb8f77a9b88 igt/gem_exec_suspend: Try to suspend
with a pend
Random change when it copied broke the interface I was using.
Signed-off-by: Chris Wilson
---
lib/igt_dummyload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index c3516b96..d19b4e5e 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_
Hi Linus,
Since Dave is on paternity leave we are sending drm/i915 fixes for
v4.14-rc1 directly to you as he had asked us to do.
The most critical ones are the GPU reset fix for gen2-4 and GVT fix
for a regression that is blocking gvt init to work on your tree.
The rest is general fixes for patc
On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote:
> Oh HSW the real activate of PSR is decided by the source
Typos: On HSW+
> after certain amount of configured idle frames.
>
> However for the driver perspective where we track psr.active
> variable this function here is the actual activate
Sorry for the delayed review, this series needs to rebased as we are
passing crtc_state to a lot of these functions now. I don't see any
issues based on my cursory review.
On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote:
> Most of patches on this series is only a clean up with
> no function
== Series Details ==
Series: lib/igt_dummyload: Use -1 for all engines
URL : https://patchwork.freedesktop.org/series/29973/
State : failure
== Summary ==
IGT patchset tested on top of latest successful build
e49c3feda5e379fbba58731b74beccb8f77a9b88 igt/gem_exec_suspend: Try to suspend
with a
== Series Details ==
Series: series starting with [1/6] drm/i915: Transform
WaInPlaceDecompressionHang into a simple reg write
URL : https://patchwork.freedesktop.org/series/29957/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
pass -> FAIL
On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote:
> Continue on VPV PSR split with vfunc, let's also create one
Typo s/VPV/VLV
> for enabling sink.
>
> Cc: Daniel Vetter
> Cc: Dhinakaran Pandiyan
> Cc: Jim Bride
> Cc: Vathsala NAgaraju
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gp
On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote:
> Continue on VPV PSR split with vfunc, let's also create one
Typo: s/VPV/VLV
> for enabling source.
>
> Also since we are touching *_enable_source functions let's
> fix a comment with wrong name for vlv's one.
>
> Cc: Daniel Vetter
> Cc
Quoting Ville Syrjälä (2017-09-07 19:50:13)
> On Thu, Sep 07, 2017 at 07:45:20PM +0100, Chris Wilson wrote:
> > We also see the delayed GTT write issue on i915g/i915gm, so let's
> > presume that it is a universal problem for all !llc machines, and that we
> > just haven't yet noticed on g33, gen4 a
Quoting Patchwork (2017-09-07 16:58:53)
> == Series Details ==
>
> Series: series starting with [1/6] drm/i915: Transform
> WaInPlaceDecompressionHang into a simple reg write
> URL : https://patchwork.freedesktop.org/series/29957/
> State : success
>
> == Summary ==
>
> Series 29957v1 series
On 8 September 2017 at 06:03, Rodrigo Vivi wrote:
> Hi Linus,
>
> Since Dave is on paternity leave we are sending drm/i915 fixes for
> v4.14-rc1 directly to you as he had asked us to do.
>
> The most critical ones are the GPU reset fix for gen2-4 and GVT fix
> for a regression that is blocking gvt
Quoting Zhi Wang (2017-09-05 20:58:24)
> Factor out setup_private_pat() for introducing the following patches.
>
> Cc: Ben Widawsky
> Cc: Rodrigo Vivi
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Signed-off-by: Zhi Wang
Reviewed-by: Chris Wilson
-Chris
_
Quoting Zhi Wang (2017-09-05 20:58:25)
> The private PAT management is to support PPAT entry manipulation. Two
> APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
> and intel_ppat_put.
>
> intel_ppat_get will search for an existing PPAT entry which perfectly
> matches the r
Quoting Zhi Wang (2017-09-05 20:58:26)
> static void gen6_gmch_remove(struct i915_address_space *vm)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index e10ca89..575da15 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/
Quoting Zhi Wang (2017-09-05 20:58:27)
> Introduce two live tests of private PAT managment:
>
> igt_ppat_init - This test is to check if all the PPAT configuration is
> written into HW.
>
> igt_ppat_get - This test performs several sub-tests on intel_ppat_get()
> and intel_ppat_put().
>
> The "p
Quoting Chris Wilson (2017-09-04 13:02:27)
> Quoting Patchwork (2017-09-03 15:17:57)
> > == Series Details ==
> >
> > Series: series starting with [1/8] drm/i915: Try harder to finish the
> > idle-worker
> > URL : https://patchwork.freedesktop.org/series/29764/
> > State : success
> >
> > == S
Quoting Tvrtko Ursulin (2017-09-07 09:49:02)
>
> On 07/09/2017 01:37, Anusha Srivatsa wrote:
> > Calculate the time that GuC takes to load.
> > This information could be very useful in
> > determining if GuC is taking unreasonably long time
> > to load in a certain platforms.
>
> Do we need this
Let's move the activation calls together after enable is done.
No real functional change should be expected here. Just an attempt
to get it clear when we are really activating PSR after enabling it.
v2: Add braces on if/else because commit message there is too long
as suggested by Jani.
v3: R
Continue on VLV PSR split with vfunc, let's move activate
function there.
Cc: Daniel Vetter
Cc: Dhinakaran Pandiyan
Cc: Vathsala Nagaraju
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 9 +++--
2 files changed, 4 insertions(+), 6
No functional change is expected here since at this point
PSR is not allowed to go to any active state. In other
words, not really enabled.
However let's do in a separated patch so it gets clear
on what is change and specially it can helps on bisect
case if we figure something has caused changes i
Continue on VLV PSR split with vfunc, let's also create
one for setting up VSC.
v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
crtc_state to PSR enable/disable")
Cc: Daniel Vetter
Cc: Dhinakaran Pandiyan
Cc: Vathsala Nagaraju
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i
We really don't want to setup vfuncs and lock mutexes on
platforms that has no support to PSR.
Also we know what platforms they are so let's do it quietly.
Cc: Daniel Vetter
Cc: Dhinakaran Pandiyan
Cc: Vathsala Nagaraju
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 19 ++
Continue on VLV PSR split with vfunc, let's also create one
for enabling sink.
v2: Fix typo on commit message (DK).
Cc: Daniel Vetter
Cc: Dhinakaran Pandiyan
Cc: Vathsala Nagaraju
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 9 +++
This sequence is part of enable source anyways, but they
only need to be executed once and not on every activation,
So let's re-create hsw_enable_source.
v2: Avoid changing order here to avoid changing behaviour
as suggested by Jani.
v3: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
VLV/CHV has a total different PSR implementation than the
other platforms, so let's start moving that to vfuncs.
Let's start with disable_src one.
v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
crtc_state to PSR enable/disable")
Cc: Daniel Vetter
Cc: Dhinakaran Pandiyan
Cc: Vat
VSC package is decided per eDP spec for psr1 or psr2,
and not per platform, so let's unify it and kill "skl"
func.
v2: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
crtc_state to PSR enable/disable")
Cc: Dhinakaran Pandiyan
Cc: Vathsala Nagaraju
Signed-off-by: Rodrigo Vivi
---
d
The ultimate goal is to be able to use more HW tracking on the PSR
implementation where that is possible, i.e. all other platforms but VLV/CHV.
But before doing that, let's organize PSR a bit more so it will be really
clear the platforms where HW tracking is possible.
This series is not addressin
Continue on VLV PSR split with vfunc, let's also create one
for enabling source.
Also since we are touching *_enable_source functions let's
fix a comment with wrong name for vlv's one.
v2: Fix typo on commit message (DK).
Cc: Daniel Vetter
Cc: Dhinakaran Pandiyan
Cc: Vathsala Nagaraju
Signed-
On HSW+ the real activate of PSR is decided by the source
after certain amount of configured idle frames.
However for the driver perspective where we track psr.active
variable this function here is the actual activate one. So
let's rename it before moving to vfunc with that.
v2: Fix typo on commi
== Series Details ==
Series: igt/tools_test: Remove dmesg subtest
URL : https://patchwork.freedesktop.org/series/29970/
State : success
== Summary ==
Test kms_atomic_transition:
Subgroup plane-use-after-nonblocking-unbind:
incomplete -> FAIL (shard-hsw) fdo#101847
We now have Coffee Lake on our CI systems.
Coffee Lake is at this point in same stage as Kaby Lake.
And it seems that we don't have any risk of bad blank
screens or anything like that. So let's remove the protection.
Cc: Daniel Vetter
Cc: Dhinakaran Pandiyan
Signed-off-by: Rodrigo Vivi
---
d
== Series Details ==
Series: PSR clean-up and vfuncs for clear split between different psr
implementations
URL : https://patchwork.freedesktop.org/series/29980/
State : success
== Summary ==
Series 29980v1 PSR clean-up and vfuncs for clear split between different psr
implementations
https://
== Series Details ==
Series: drm/i915/cfl: Remove alpha support protection.
URL : https://patchwork.freedesktop.org/series/29981/
State : success
== Summary ==
Series 29981v1 drm/i915/cfl: Remove alpha support protection.
https://patchwork.freedesktop.org/api/1.0/series/29981/revisions/1/mbox/
== Series Details ==
Series: PSR clean-up and vfuncs for clear split between different psr
implementations
URL : https://patchwork.freedesktop.org/series/29980/
State : failure
== Summary ==
Test kms_flip:
Subgroup wf_vblank-vs-dpms-interruptible:
pass -> DMESG-W
== Series Details ==
Series: drm/i915/cfl: Remove alpha support protection.
URL : https://patchwork.freedesktop.org/series/29981/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
fdo#99912 https://bugs.freed
On Thu, 2017-09-07 at 16:00 -0700, Rodrigo Vivi wrote:
> Continue on VLV PSR split with vfunc, let's also create one
> for enabling source.
>
> Also since we are touching *_enable_source functions let's
> fix a comment with wrong name for vlv's one.
>
> v2: Fix typo on commit message (DK).
>
> C
On Thu, 2017-09-07 at 16:06 -0700, Rodrigo Vivi wrote:
> We now have Coffee Lake on our CI systems.
>
> Coffee Lake is at this point in same stage as Kaby Lake.
>
> And it seems that we don't have any risk of bad blank
> screens or anything like that. So let's remove the protection.
>
Reviewed-
The function is perhaps a bit renamed, but if a previous tests failed
so badly it left the gpu wrecked, then we should fail, not skip.
Testcases shouldn't ever randomly skip at least, since that just
indicates whether the feature is there or not. Pass/fail is for
whether it's working or not.
Cc:
bb9d2d050503c69695557b8b741276686ca2a396:
drm/i915: Update DRIVER_DATE to 20170907 (2017-09-07 11:28:20 +0300)
are available in the git repository at:
https://github.com/01org/gvt-linux.git tags/gvt-next-2017-09-08
for you to fetch changes up to 02d578e5edd980eac3fbed15db4d9e5665f22089:
drm/i915/gvt: Add
On Tue, Sep 05, 2017 at 04:34:32PM -0700, Belgaumkar, Vinay wrote:
>
>
> On 9/4/2017 1:30 AM, Daniel Vetter wrote:
> > On Thu, Aug 31, 2017 at 02:33:23PM -0700, Vinay Belgaumkar wrote:
> > > Added the missing IGT_TEST_DESCRIPTION and some subtest
> > > descriptions. Trying to establish a method t
On Wed, Sep 06, 2017 at 05:01:42PM +0300, Jani Nikula wrote:
> On Tue, 05 Sep 2017, Daniel Vetter wrote:
> > Why?
> >
> > Because it's fast.
>
> And that's not even the main reason from my perspective! ;)
>
> Please find some comments inline. None of them are blockers.
>
> BR,
> Jani.
>
> >
>
On Wed, Sep 06, 2017 at 12:44:20PM +0100, Chris Wilson wrote:
> Quoting Daniel Vetter (2017-09-05 13:36:09)
> > diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> > index f2a94b5572ea..a2061ff6138e 100644
> > --- a/lib/igt_dummyload.c
> > +++ b/lib/igt_dummyload.c
> > @@ -22,11 +22,18 @@
> >
On Wed, Sep 06, 2017 at 12:31:05PM +0300, Petri Latvala wrote:
>
>
> On 09/05/2017 07:16 PM, Daniel Vetter wrote:
> > On Tue, Sep 05, 2017 at 03:39:49PM +0300, Petri Latvala wrote:
> > > When no action is specified on the command line, print the usage help
> > > text and exit with failure instead
On Wed, Sep 06, 2017 at 07:48:33PM +0300, Martin Peres wrote:
> On 06/09/17 13:09, Mika Kahola wrote:
> > On Tue, 2017-09-05 at 18:11 +0200, Daniel Vetter wrote:
> > > On Tue, Sep 05, 2017 at 04:35:04PM +0300, Mika Kahola wrote:
> > > >
> > > > It appears that we cannot trust scanline counters whe
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