>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Friday, April 28, 2017 6:09 PM
>To: Chen, Xiaoguang
>Cc: kra...@redhat.com; alex.william...@redhat.com; intel-
>g...@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; Wang, Zhi A
>; zhen...@linux.i
Hi all,
Somehow not much these 2 weeks ...
- (hopefully) stability fixes for byt/bsw gt wake (Chris)
- tighten up requests (especially restarts) checks and debug tracking
(Chris)
- unify context handling more for gen5+ (Chris+Joonas)
- oddball bugfixes as usual
Happy testing!
Cheers, Daniel
On Mon, Apr 24, 2017 at 02:01:05PM +0200, Maarten Lankhorst wrote:
> On 19-04-17 17:43, Daniel Vetter wrote:
> > On Thu, Apr 13, 2017 at 11:15:37AM +0200, Maarten Lankhorst wrote:
> >> This is required to for i915 to convert connector properties to atomic.
> >>
> >> Changes since v1:
> >> - Add doc
Op 02-05-17 om 10:12 schreef Daniel Vetter:
> On Mon, Apr 24, 2017 at 02:01:05PM +0200, Maarten Lankhorst wrote:
>> On 19-04-17 17:43, Daniel Vetter wrote:
>>> On Thu, Apr 13, 2017 at 11:15:37AM +0200, Maarten Lankhorst wrote:
This is required to for i915 to convert connector properties to ato
On Mon, Apr 24, 2017 at 11:25:12AM +1000, Stephen Rothwell wrote:
> Hi all,
>
> On Fri, 21 Apr 2017 12:10:14 +1000 Stephen Rothwell
> wrote:
> >
> > After merging the drm-misc tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> > drivers/tee/tee_shm.c:87:2: error: u
Hi Daniel,
On Tue, 2 May 2017 10:25:18 +0200 Daniel Vetter wrote:
>
> Since this is an all-new driver it might be best to stagger the pull
> requests and merge the new tee subsystem (or whatever it is) after drm?
>
> Not sure what to best do here ...
This will merge via Dave, so Dave just needs
On Tue, May 2, 2017 at 10:41 AM, Stephen Rothwell wrote:
> Hi Daniel,
>
> On Tue, 2 May 2017 10:25:18 +0200 Daniel Vetter wrote:
>>
>> Since this is an all-new driver it might be best to stagger the pull
>> requests and merge the new tee subsystem (or whatever it is) after drm?
>>
>> Not sure wha
On Mon, May 01, 2017 at 07:28:12AM +, Oscar Mateo wrote:
>
>
> On 04/29/2017 08:31 AM, Chris Wilson wrote:
> >On Fri, Apr 28, 2017 at 05:26:09PM +, Oscar Mateo wrote:
> >>This will be more useful later to support platforms that need to emit
> >>HW commands at the beginning of every reques
Currently GVT-g cannot work properly when host GuC submission
is enabled, so disable GVT in this case.
Cc: Zhenyu Wang
Signed-off-by: Chuanxiao Dong
---
drivers/gpu/drm/i915/intel_gvt.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i
On Mon, May 01, 2017 at 10:36:13PM +0200, Rafael J. Wysocki wrote:
> On Sunday, April 30, 2017 03:57:13 PM Imre Deak wrote:
> > On Sat, Apr 29, 2017 at 12:21:57PM +0200, Rafael J. Wysocki wrote:
> > > On Friday, April 28, 2017 11:33:02 PM Rafael J. Wysocki wrote:
> > > > On Friday, April 28, 2017 0
Chris Wilson writes:
> On Fri, Apr 28, 2017 at 09:11:06AM +, Oscar Mateo wrote:
>> The new batchbuffer for CNL surpasses the 4096 byte mark.
>>
>> Cc: Mika Kuoppala
>> Cc: Ben Widawsky
>> Signed-off-by: Oscar Mateo
>
> Evil, 4k+ of nothing-ness that userspace then has to configure for its
On Tue, May 2, 2017 at 10:55 AM, Arnd Bergmann wrote:
> On Tue, May 2, 2017 at 10:41 AM, Stephen Rothwell
> wrote:
>> Hi Daniel,
>>
>> On Tue, 2 May 2017 10:25:18 +0200 Daniel Vetter wrote:
>>>
>>> Since this is an all-new driver it might be best to stagger the pull
>>> requests and merge the n
Hi,
> > +#ifndef _GVT_DMABUF_H_
> > +#define _GVT_DMABUF_H_
> > +
> > +#define INTEL_VGPU_QUERY_DMABUF0
> > +#define INTEL_VGPU_GENERATE_DMABUF 1
> > +
> > +struct intel_vgpu_dmabuf {
>
> This looks to be uapi. What's it doing here?
It is indeed, should go to include/uapi/
cheers,
On Mon, May 01, 2017 at 03:37:54PM +0200, Maarten Lankhorst wrote:
> Some connectors may not allow all scaling mode properties, this function will
> allow
> creating the scaling mode property with only the supported subset. It also
> wires up
> this state for atomic.
>
> This will make it possib
On Fr, 2017-04-28 at 17:35 +0800, Xiaoguang Chen wrote:
> +static size_t intel_vgpu_reg_rw_gvtg(struct intel_vgpu *vgpu, char
> *buf,
> + size_t count, loff_t *ppos, bool iswrite)
> +{
> + unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
> + VFIO_PCI_NUM_
On Wed, Apr 19, 2017 at 01:01:47PM +0200, Arkadiusz Hiler wrote:
> Also igt_chamelium.h included config.h without proper "HAVE_CONFIG_H"
> guard, and the file itself was included unconditionally.
I see unconditional config.h inclusion in several other places,
is igt_chamelium.h the only file where
On Mon, May 01, 2017 at 03:37:53PM +0200, Maarten Lankhorst wrote:
> This is only used in i915, which had used its own non-taomic way to
> deal with the picture aspect ratio. Move selected aspect_ratio to
> atomic state and use the atomic state in the affected i915 connectors.
>
> Signed-off-by: M
On Mon, May 01, 2017 at 03:37:57PM +0200, Maarten Lankhorst wrote:
> Some atomic properties are common between the various kinds of
> connectors, for example a lot of them use panel fitting mode.
> It makes sense to put a lot of it in a common place, so each
> connector can use it while they're bei
== Series Details ==
Series: drm/i915/gvt: disable GVT-g if host GuC submission is enabled
URL : https://patchwork.freedesktop.org/series/23796/
State : success
== Summary ==
Series 23796v1 drm/i915/gvt: disable GVT-g if host GuC submission is enabled
https://patchwork.freedesktop.org/api/1.0/
It is safer to setup valid send function after successful GuC
hardware initialization. In addition we prepare placeholder
where we can setup any alternate GuC communication mechanism.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spu
This is just for CI testing, *** DO NOT MERGE ***
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index b6a7e36..abd2894 100
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: Enable send function only
after successful init
URL : https://patchwork.freedesktop.org/series/23799/
State : success
== Summary ==
Series 23799v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/ser
Op 02-05-17 om 11:44 schreef Daniel Vetter:
> On Mon, May 01, 2017 at 03:37:54PM +0200, Maarten Lankhorst wrote:
>> Some connectors may not allow all scaling mode properties, this function
>> will allow
>> creating the scaling mode property with only the supported subset. It also
>> wires up
>> t
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
first use, the adjust
When we query the available eu on each subslice, we currently only
report the max. It would also be useful to report the minimum found as
well.
When we set RPCS (power gating over the EU), we can also specify both
the min and max number of eu to configure on each slice; currently we
just set it to
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may want to
opt out of th
In the next patch, we will expose the ability to reconfigure the slices,
subslice and eu per context. To facilitate that, store the current
configuration on the context, which is initially set to the device
default upon creation.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h
Since
commit bac2a909a096c9110525c18cbb8ce73c660d5f71
Author: Rafael J. Wysocki
Date: Wed Jan 21 02:17:42 2015 +0100
PCI / PM: Avoid resuming PCI devices during system suspend
PCI devices will default to allowing the system suspend complete
optimization where devices are not woken up duri
Some drivers - like i915 - may not support the system suspend direct
complete optimization due to differences in their runtime and system
suspend sequence. Add a flag that when set resumes the device before
calling the driver's system suspend handlers which effectively disables
the optimization.
N
On Tue, May 02, 2017 at 10:32:42AM +, Michal Wajdeczko wrote:
> It is safer to setup valid send function after successful GuC
> hardware initialization. In addition we prepare placeholder
> where we can setup any alternate GuC communication mechanism.
>
> Signed-off-by: Michal Wajdeczko
> Cc:
== Series Details ==
Series: series starting with [RFC,1/4] drm/i915: Record both min/max
eu_per_subslice in sseu_dev_info
URL : https://patchwork.freedesktop.org/series/23802/
State : success
== Summary ==
Series 23802v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/s
On ti, 2017-05-02 at 12:49 +0100, Chris Wilson wrote:
> When we query the available eu on each subslice, we currently only
> report the max. It would also be useful to report the minimum found as
> well.
>
> When we set RPCS (power gating over the EU), we can also specify both
> the min and max nu
On pe, 2017-04-28 at 10:46 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Do not leak dev_priv->l3_parity.remap_info[]
> URL : https://patchwork.freedesktop.org/series/23679/
> State : success
Merged the patch. Thanks for the review.
> == Summary ==
>
> Series 23679v1 dr
On ti, 2017-05-02 at 12:49 +0100, Chris Wilson wrote:
> Currently we only configure the power gating for Skylake and above, but
> the configuration should equally apply to Broadwell and Braswell. Even
> though, there is not as much variation as for later generations, we want
> to expose control ove
On 28/04/2017 20:02, Chris Wilson wrote:
Track the latest fence waited upon on each context, and only add a new
asynchronous wait if the new fence is more recent than the recorded
fence for that context. This requires us to filter out unordered
timelines, which are noted by DMA_FENCE_NO_CONTEXT.
From: Mika Kuoppala
Replace the handcrafter loop when checking for fifo slots
with atomic wait for. This brings this wait in line with
the other waits on register access. We also get a readable
timeout constraint, so make it to fail after 10ms.
Chris suggested that we should fail silently as the
From: Mika Kuoppala
Remove the per-mmio checking of the FIFO debug register into the common
conditional mmio debug handling. Based on patch from Chris Wilson.
v2: postpone warn on fifodbg for unclaimed reg debugs
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915
Prepare for alternate GuC notification mechanism.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 10 +-
drivers/gpu/drm/i915/intel_uc.h | 7 +++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/dri
This is just for CI testing, *** DO NOT MERGE ***
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index b6a7e36..abd2894 100
We are using some scratch registers in MMIO based send function.
Make their base and count flexible in preparation of upcoming
GuC firmware/hardware changes.
Signed-off-by: Michal Wajdeczko
Suggested-by: Daniele Ceraolo Spurio
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
---
drivers/gpu/drm
== Series Details ==
Series: series starting with [v4,1/2] PCI / PM: Add needs_resume flag to avoid
suspend complete optimization
URL : https://patchwork.freedesktop.org/series/23803/
State : failure
== Summary ==
Series 23803v1 Series without cover letter
https://patchwork.freedesktop.org/ap
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move the GTFIFODBG to the
common mmio dbg framework
URL : https://patchwork.freedesktop.org/series/23804/
State : success
== Summary ==
Series 23804v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/ser
On Tue, May 02, 2017 at 01:21:41PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v4,1/2] PCI / PM: Add needs_resume flag to
> avoid suspend complete optimization
> URL : https://patchwork.freedesktop.org/series/23803/
> State : failure
>
> == Summary ==
>
>
== Series Details ==
Series: series starting with [1/3] drm/i915/guc: Move notification code into
virtual function
URL : https://patchwork.freedesktop.org/series/23805/
State : success
== Summary ==
Series 23805v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/23
From: Mika Kuoppala
Replace the handcrafter loop when checking for fifo slots
with atomic wait for. This brings this wait in line with
the other waits on register access. We also get a readable
timeout constraint, so make it to fail after 10ms.
Chris suggested that we should fail silently as the
== Series Details ==
Series: series starting with [1/2] drm/i915: Move the GTFIFODBG to the common
mmio dbg framework (rev4)
URL : https://patchwork.freedesktop.org/series/22571/
State : success
== Summary ==
Series 22571v4 Series without cover letter
https://patchwork.freedesktop.org/api/1.0
On Tue, May 02, 2017 at 01:24:58PM +0100, Tvrtko Ursulin wrote:
> On 28/04/2017 20:02, Chris Wilson wrote:
> >+if (!p->height) {
> >+for (bits = p->bitmap; (i = ffs(bits)); bits &= ~0u << i) {
>
> Would for_each_set_bit be more readable?
Downside is that we have to cast bitmap to
On Tue, May 02, 2017 at 01:24:58PM +0100, Tvrtko Ursulin wrote:
> On 28/04/2017 20:02, Chris Wilson wrote:
> >+prandom_seed_state(&prng, i915_selftest.random_seed);
> >+count = 0;
> >+kt = ktime_get();
> >+end_time = jiffies + HZ/10;
> >+do {
> >+u32 id = random_engi
Add some standard headers to the pull request tag annotation.
Signed-off-by: Sean Paul
---
dim | 25 -
dim.rst | 4
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/dim b/dim
index 8937803..0d52e9d 100755
--- a/dim
+++ b/dim
@@ -67,6 +67,9 @@
DIM_
On Tue, May 2, 2017 at 10:55 AM, Sean Paul wrote:
> Add some standard headers to the pull request tag annotation.
>
> Signed-off-by: Sean Paul
> ---
This time to Daniel's actual address.
Note that I couldn't add the headers as comments since git tag -m
skips anything prefixed with #. Hopefully
== Series Details ==
Series: series starting with [v4,1/2] PCI / PM: Add needs_resume flag to avoid
suspend complete optimization
URL : https://patchwork.freedesktop.org/series/23803/
State : warning
== Summary ==
Series 23803v1 Series without cover letter
https://patchwork.freedesktop.org/ap
On Tue, May 02, 2017 at 03:45:23PM +0100, Chris Wilson wrote:
> On Tue, May 02, 2017 at 01:24:58PM +0100, Tvrtko Ursulin wrote:
> > On 28/04/2017 20:02, Chris Wilson wrote:
> > >+ if (!p->height) {
> > >+ for (bits = p->bitmap; (i = ffs(bits)); bits &= ~0u << i) {
> >
> > Would for_each_
On 02/05/2017 15:45, Chris Wilson wrote:
On Tue, May 02, 2017 at 01:24:58PM +0100, Tvrtko Ursulin wrote:
On 28/04/2017 20:02, Chris Wilson wrote:
+ if (!p->height) {
+ for (bits = p->bitmap; (i = ffs(bits)); bits &= ~0u << i) {
Would for_each_set_bit be more readable?
D
== Series Details ==
Series: series starting with [v4,1/2] PCI / PM: Add needs_resume flag to avoid
suspend complete optimization
URL : https://patchwork.freedesktop.org/series/23803/
State : success
== Summary ==
Series 23803v1 Series without cover letter
https://patchwork.freedesktop.org/ap
On Tue, May 02, 2017 at 03:10:29PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v4,1/2] PCI / PM: Add needs_resume flag to
> avoid suspend complete optimization
> URL : https://patchwork.freedesktop.org/series/23803/
> State : warning
>
> == Summary ==
>
>
On 05/02/2017 09:17 AM, Mika Kuoppala wrote:
Chris Wilson writes:
On Fri, Apr 28, 2017 at 09:11:06AM +, Oscar Mateo wrote:
The new batchbuffer for CNL surpasses the 4096 byte mark.
Cc: Mika Kuoppala
Cc: Ben Widawsky
Signed-off-by: Oscar Mateo
Evil, 4k+ of nothing-ness that userspac
On 02/05/17 05:39, Michal Wajdeczko wrote:
Prepare for alternate GuC notification mechanism.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 10 +-
drivers/gpu/drm/i915/intel_uc.h | 7 +++
2 files changed, 16
On Tue, May 02, 2017 at 03:04:09PM +0300, Imre Deak wrote:
> Since
>
> commit bac2a909a096c9110525c18cbb8ce73c660d5f71
> Author: Rafael J. Wysocki
> Date: Wed Jan 21 02:17:42 2015 +0100
>
> PCI / PM: Avoid resuming PCI devices during system suspend
>
> PCI devices will default to allowing
On 02/05/17 05:39, Michal Wajdeczko wrote:
We are using some scratch registers in MMIO based send function.
Make their base and count flexible in preparation of upcoming
GuC firmware/hardware changes.
Signed-off-by: Michal Wajdeczko
Suggested-by: Daniele Ceraolo Spurio
Cc: Daniele Ceraolo Sp
Hi,
This is v3 of the series to add dma_buf import functions for vgem.
This is mostly a rebase to drm-misc/drm-misc-next with a fixup of
the resulting conflicts. More details can be found on the individual
patches.
Thanks,
Laura
Laura Abbott (3):
drm/vgem: Add a dummy platform device
drm/pri
The vgem driver is currently registered independent of any actual
device. Some usage of the dmabuf APIs require an actual device structure
to do anything. Register a dummy platform device for use with dmabuf.
Cc: intel-gfx@lists.freedesktop.org
Reviewed-by: Chris Wilson
Signed-off-by: Laura Abbot
The existing drm_gem_prime_import function uses the underlying
struct device of a drm_device for attaching to a dma_buf. Some drivers
(notably vgem) may not have an underlying device structure. Offer
an alternate function to attach using a platform device associated
with drm_device.
Cc: intel-gfx@
On Tue, May 02, 2017 at 06:51:01PM +0200, Daniel Vetter wrote:
> On Tue, May 02, 2017 at 03:04:09PM +0300, Imre Deak wrote:
> > Since
> >
> > commit bac2a909a096c9110525c18cbb8ce73c660d5f71
> > Author: Rafael J. Wysocki
> > Date: Wed Jan 21 02:17:42 2015 +0100
> >
> > PCI / PM: Avoid resum
Enable the GEM dma-buf import interfaces in addition to the export
interfaces. This lets vgem be used as a test source for other allocators
(e.g. Ion).
Cc: intel-gfx@lists.freedesktop.org
Reviewed-by: Chris Wilson
Signed-off-by: Laura Abbott
---
v3: Minor fixes suggested by Chris Wilson
---
dri
== Series Details ==
Series: dma_buf import support for vgem
URL : https://patchwork.freedesktop.org/series/23824/
State : success
== Summary ==
Series 23824v1 dma_buf import support for vgem
https://patchwork.freedesktop.org/api/1.0/series/23824/revisions/1/mbox/
Test gem_exec_suspend:
On 05/02/2017 11:49 AM, Chris Wilson wrote:
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI).
Users
Add some standard headers to the pull request tag annotation.
Changes in v2:
- Tweaked the template var name s/PULL/TAG/ (Daniel)
Signed-off-by: Sean Paul
---
dim | 25 -
dim.rst | 4
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/dim b/dim
in
On Mon, May 01, 2017 at 08:29:10PM -0500, Pierre-Louis Bossart wrote:
>
>
> On 04/28/2017 02:37 PM, Ville Syrjälä wrote:
> > On Fri, Apr 28, 2017 at 12:10:31PM -0500, Pierre-Louis Bossart wrote:
> >>
> >> On 04/28/2017 03:41 AM, Takashi Iwai wrote:
> >>> On Thu, 27 Apr 2017 18:02:19 +0200,
> >>>
On 02/05/17 04:49, Chris Wilson wrote:
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration t
On Tue, May 02, 2017 at 10:33:19AM +, Oscar Mateo wrote:
>
>
> On 05/02/2017 11:49 AM, Chris Wilson wrote:
> >We want to allow userspace to reconfigure the subslice configuration for
> >its own use case. To do so, we expose a context parameter to allow
> >adjustment of the RPCS register store
On Mon, May 01, 2017 at 06:17:09PM -0700, Lionel Landwerlin wrote:
Focusing on the bit I know best and leaving the hw mumbo jumbo to one
side...
> +static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv)
> +{
> + struct intel_engine_cs *engine = dev_priv->engine[RCS];
> +
On 5/2/17 1:27 PM, Ville Syrjälä wrote:
On Mon, May 01, 2017 at 08:29:10PM -0500, Pierre-Louis Bossart wrote:
On 04/28/2017 02:37 PM, Ville Syrjälä wrote:
On Fri, Apr 28, 2017 at 12:10:31PM -0500, Pierre-Louis Bossart wrote:
On 04/28/2017 03:41 AM, Takashi Iwai wrote:
On Thu, 27 Apr 2017 1
On Tue, May 02, 2017 at 10:02:07AM -0700, Laura Abbott wrote:
> The existing drm_gem_prime_import function uses the underlying
> struct device of a drm_device for attaching to a dma_buf. Some drivers
> (notably vgem) may not have an underlying device structure. Offer
> an alternate function to atta
On Tue, 02 May 2017 22:15:20 +0200,
Pierre-Louis Bossart wrote:
>
> On 5/2/17 1:27 PM, Ville Syrjälä wrote:
> > On Mon, May 01, 2017 at 08:29:10PM -0500, Pierre-Louis Bossart wrote:
> >>
> >>
> >> On 04/28/2017 02:37 PM, Ville Syrjälä wrote:
> >>> On Fri, Apr 28, 2017 at 12:10:31PM -0500, Pierre-L
On Tuesday, May 02, 2017 12:05:38 PM Imre Deak wrote:
> On Mon, May 01, 2017 at 10:36:13PM +0200, Rafael J. Wysocki wrote:
> > On Sunday, April 30, 2017 03:57:13 PM Imre Deak wrote:
> > > On Sat, Apr 29, 2017 at 12:21:57PM +0200, Rafael J. Wysocki wrote:
> > > > On Friday, April 28, 2017 11:33:02 P
On Tuesday, May 02, 2017 03:04:08 PM Imre Deak wrote:
> Some drivers - like i915 - may not support the system suspend direct
> complete optimization due to differences in their runtime and system
> suspend sequence. Add a flag that when set resumes the device before
> calling the driver's system su
Hello,
I would like to thank you for the good driver you provide.
There is only one thing missing for my complete joy...I would like to know
how to adjust overcan parameter (dunno if it's the right word : the output
display is a little bit larger than the physical screen by maybe an inch
(bottom)
On Tue, May 02, 2017 at 09:37:45AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 02/05/17 05:39, Michal Wajdeczko wrote:
> > Prepare for alternate GuC notification mechanism.
> >
> > Signed-off-by: Michal Wajdeczko
> > Cc: Joonas Lahtinen
> > Cc: Daniele Ceraolo Spurio
> > ---
> > drivers/gp
From: Robert Bragg
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to ma
On 05/02/2017 07:55 PM, Chris Wilson wrote:
On Tue, May 02, 2017 at 10:33:19AM +, Oscar Mateo wrote:
On 05/02/2017 11:49 AM, Chris Wilson wrote:
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adj
Cc: Dmitry Rogozhkin
Cc: Chris Wilson
Signed-off-by: Oscar Mateo
---
tests/pm_sseu.c | 105
1 file changed, 105 insertions(+)
diff --git a/tests/pm_sseu.c b/tests/pm_sseu.c
index 7d4b33c..1fb36c5 100644
--- a/tests/pm_sseu.c
+++ b/tests/
This allows userspace to shutdown slices at will for performance/power reasons
(because it doesn't have a use for more slices).
Cc: Dmitry Rogozhkin
Cc: Chris Wilson
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_engine_cs.c | 11 +++
1 file changed, 11 insertions(+)
diff -
Cc: Dmitry Rogozhkin
Cc: Chris Wilson
Signed-off-by: Oscar Mateo
---
benchmarks/Makefile.sources | 1 +
benchmarks/gem_slice_shutdown.c | 295
2 files changed, 296 insertions(+)
create mode 100644 benchmarks/gem_slice_shutdown.c
diff --git a/benc
On 05/02/2017 08:59 AM, Chris Wilson wrote:
On Mon, May 01, 2017 at 07:28:12AM +, Oscar Mateo wrote:
On 04/29/2017 08:31 AM, Chris Wilson wrote:
On Fri, Apr 28, 2017 at 05:26:09PM +, Oscar Mateo wrote:
This will be more useful later to support platforms that need to emit
HW commands
== Series Details ==
Series: drm/i915: Allow the UMD to configure their own power clock state
URL : https://patchwork.freedesktop.org/series/23846/
State : success
== Summary ==
Series 23846v1 drm/i915: Allow the UMD to configure their own power clock state
https://patchwork.freedesktop.org/ap
As we may unwind the requests, even though the request we are awaiting
has a global_seqno that seqno may be revoked during the await and so we
can not reliably use it as a barrier for all future awaits on the same
timeline.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Reviewed-by: Michał Win
Currently we filter out repeated use of the same timeline in the low
level i915_gem_request_await_request(), after having added the
dependency on the old request. However, we can lift this to
i915_gem_request_await_dma_fence() (before the dependency is added)
using the observation that requests alo
2 clflushes on two different objects are not ordered, and so do not
belong to the same timeline (context). Either we use a unique context
for each, or we reserve a special global context to mean unordered.
Ideally, we would reserve 0 to mean unordered (DMA_FENCE_NO_CONTEXT) to
have the same semanti
Rather than use a global modparam, we can just check to see if the
engine has semaphores configured upon it.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_request.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
With the addition of the inter-context intel_time.sync map, having a
very similar sync_seqno[] is confusing. Aide the reader by denoting that
this a pre-allocated array for storing semaphore sync points wrt to the
global seqno.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
driver
Track the latest fence waited upon on each context, and only add a new
asynchronous wait if the new fence is more recent than the recorded
fence for that context. This requires us to filter out unordered
timelines, which are noted by DMA_FENCE_NO_CONTEXT. However, in the
absence of a universal iden
By first unwrapping an incoming fence-array into its child fences, we
can simplify the internal branching, and so avoid triggering a potential
in the next patch when not squashing the child fences on the same timeline.
It will also have the advantage of keeping the (top-level) fence arrays
out of
== Series Details ==
Series: series starting with [1/7] drm/i915: Mark up clflushes as belonging to
an unordered timeline
URL : https://patchwork.freedesktop.org/series/23853/
State : success
== Summary ==
Series 23853v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/se
Sorry for the wait. This is not a complete review, just some quick
comments for now.
On Tue, 2017-04-18 at 16:48 -0700, Puthikorn Voravootivat wrote:
> Currently the intel_dp_aux_backlight driver requires eDP panel
> to not also support backlight adjustment via PWM pin to use
> this driver.
>
>
On Tue, 2017-04-18 at 16:48 -0700, Puthikorn Voravootivat wrote:
> intel_dp_aux_enable_backlight() assumed that the register
> BACKLIGHT_BRIGHTNESS_CONTROL_MODE can only has value 01
> (DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET) when initialize.
>
> This patch fixed that by handling all cases of that r
I915_GEM_GET_APERTURE ioctl is used to probe aperture size from userspace.
In gvt environment, each vm only use the ballooned part of aperture, so we
should return the actual available aperture size exclude the reserved part
by balloon.
v2: add 'reserved' in struct i915_address_space to record the
== Series Details ==
Series: drm/i915/gvt: return the actual aperture size under gvt environment
(rev3)
URL : https://patchwork.freedesktop.org/series/22910/
State : success
== Summary ==
Series 22910v3 drm/i915/gvt: return the actual aperture size under gvt
environment
https://patchwork.fre
Adjusting "blacklight" probably won't make a lot of difference even if
done correctly:) Typo in the patch subject.
-DK
On Tue, 2017-04-18 at 16:48 -0700, Puthikorn Voravootivat wrote:
> intel_dp_aux_enable_backlight() assumed that the register
> BACKLIGHT_BRIGHTNESS_CONTROL_MODE can only has val
On Wed, 2017-05-03 at 00:54 +, Pandiyan, Dhinakaran wrote:
> Sorry for the wait. This is not a complete review, just some quick
> comments for now.
>
>
> On Tue, 2017-04-18 at 16:48 -0700, Puthikorn Voravootivat wrote:
> > Currently the intel_dp_aux_backlight driver requires eDP panel
> > to
On Tue, Apr 18, 2017 at 04:48:23PM -0700, Puthikorn Voravootivat wrote:
Since this adds definitions in the DRM layer, you need to copy
the dri-de...@lists.freedesktop.org M-L.
> This patch adds the following definition
> - Bit mask for EDP_PWMGEN_BIT_COUNT and min/max cap
> register which only
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